tests: updates for stat name change

6 files changed, 48 insertions, 48 deletions

diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index ec6c3f639..ac46e69ac 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 11:58:35
+M5 compiled Apr 21 2011 12:29:56
+M5 started Apr 21 2011 13:11:19
 M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 8dc1a35af..b64b31530 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 274016                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 208580                       # Number of bytes of host memory used
-host_seconds                                   307.21                       # Real time elapsed on the host
-host_tick_rate                              111296260                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 170645                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211856                       # Number of bytes of host memory used
+host_seconds                                   493.30                       # Real time elapsed on the host
+host_tick_rate                               69310511                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.034191                       # Number of seconds simulated
@@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewLSQFullEvents                    45                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.iewSquashCycles                5601227                       # Number of cycles IEW is squashing
 system.cpu.iew.iewUnblockCycles                 20318                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked            1                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads         1076434                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         4810                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       361752                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads         9740                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      8840023                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores      2710213                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked             1                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads          1076434                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses         4810                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation       361752                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads         9740                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads      8840023                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores      2710213                       # Number of stores squashed
 system.cpu.iew.memOrderViolationEvents         361752                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       455682                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        1627472                       # Number of branches that were predicted taken incorrectly
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
index 573beb25f..e91437a5d 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:27:04
+M5 compiled Apr 21 2011 12:05:01
+M5 started Apr 21 2011 15:06:04
 M5 executing on maize
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
 Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
index cc9da8f96..e312dcfc6 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 180598                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 218960                       # Number of bytes of host memory used
-host_seconds                                  1044.69                       # Real time elapsed on the host
-host_tick_rate                              120412102                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 111275                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 221396                       # Number of bytes of host memory used
+host_seconds                                  1695.51                       # Real time elapsed on the host
+host_tick_rate                               74191752                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   188669132                       # Number of instructions simulated
 sim_seconds                                  0.125793                       # Number of seconds simulated
@@ -266,16 +266,16 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewLSQFullEvents                  2590                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.iewSquashCycles               27129630                       # Number of cycles IEW is squashing
 system.cpu.iew.iewUnblockCycles                  7356                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          954573                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        20572                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       222499                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads            3                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     20486294                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores      5462392                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads           954573                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses        20572                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation       222499                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads            3                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads     20486294                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores      5462392                       # Number of stores squashed
 system.cpu.iew.memOrderViolationEvents         222499                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      2295597                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        8864678                       # Number of branches that were predicted taken incorrectly
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
index 09f414a42..5be7bed53 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:39:55
+M5 compiled Apr 21 2011 13:30:37
+M5 started Apr 21 2011 13:53:57
 M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 84b97ca66..e5f49060a 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 200454                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 220376                       # Number of bytes of host memory used
-host_seconds                                  1104.31                       # Real time elapsed on the host
-host_tick_rate                               96698720                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 120975                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223752                       # Number of bytes of host memory used
+host_seconds                                  1829.83                       # Real time elapsed on the host
+host_tick_rate                               58358040                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   221363017                       # Number of instructions simulated
 sim_seconds                                  0.106785                       # Number of seconds simulated
@@ -233,16 +233,16 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewLSQFullEvents                 13026                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.iewSquashCycles               23161998                       # Number of cycles IEW is squashing
 system.cpu.iew.iewUnblockCycles                523918                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads        16343714                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        20445                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        35659                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads        45746                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     48346210                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     16601009                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads         16343714                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses        20445                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation        35659                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads        45746                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads     48346210                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores     16601009                       # Number of stores squashed
 system.cpu.iew.memOrderViolationEvents          35659                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       741660                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        2532614                       # Number of branches that were predicted taken incorrectly