diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-06-20 18:57:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-20 18:57:14 -0400 |
| commit | b5736ba4ef3ae82238c7c9811e182c8a13a58fdd (patch) | |
| tree | ce28586e5b2957d629b7041e78cc56cc7e1457ed /tests/long/70.twolf | |
| parent | affad299320e767b18c45a760c69a1ef287565bc (diff) | |
| download | gem5-b5736ba4ef3ae82238c7c9811e182c8a13a58fdd.tar.xz | |
alpha:o3:simple: update simout/err files
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning
Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
Diffstat (limited to 'tests/long/70.twolf')
9 files changed, 703 insertions, 730 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index ac46e69ac..f701d0797 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:11:19 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 19 2011 07:11:56 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index b64b31530..f1b3177ca 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,162 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 170645 # Simulator instruction rate (inst/s) -host_mem_usage 211856 # Number of bytes of host memory used -host_seconds 493.30 # Real time elapsed on the host -host_tick_rate 69310511 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 84179709 # Number of instructions simulated sim_seconds 0.034191 # Number of seconds simulated sim_ticks 34191076000 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted -system.cpu.commit.branches 10240685 # Number of branches committed -system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle -system.cpu.commit.count 91903055 # Number of instructions committed -system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. -system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. -system.cpu.commit.loads 19996198 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 26497301 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 84179709 # Number of Instructions Simulated -system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency -system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses -system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 30012251 # number of overall hits -system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses -system.cpu.dcache.overall_misses 8940 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 160 # number of replacements -system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use -system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 109 # number of writebacks -system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle -system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running -system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 32239873 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 31883201 # DTB hits -system.cpu.dtb.data_misses 356672 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 184031 # Simulator instruction rate (inst/s) +host_tick_rate 74747519 # Simulator tick rate (ticks/s) +host_mem_usage 197584 # Number of bytes of host memory used +host_seconds 457.42 # Real time elapsed on the host +sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 24961741 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 24606273 # DTB read hits system.cpu.dtb.read_misses 355468 # DTB read misses -system.cpu.dtb.write_accesses 7278132 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 24961741 # DTB read accesses system.cpu.dtb.write_hits 7276928 # DTB write hits system.cpu.dtb.write_misses 1204 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7278132 # DTB write accesses +system.cpu.dtb.data_hits 31883201 # DTB hits +system.cpu.dtb.data_misses 356672 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 32239873 # DTB accesses +system.cpu.itb.fetch_hits 17397269 # ITB hits +system.cpu.itb.fetch_misses 74 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 17397343 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 68382153 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched +system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle +system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total) @@ -174,111 +78,97 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads -system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency -system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses -system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 17386201 # number of overall hits -system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses -system.cpu.icache.overall_misses 11068 # number of overall misses -system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8218 # number of replacements -system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use -system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 12448390 # Number of branches executed -system.cpu.iew.exec_nop 11194543 # number of nop insts executed -system.cpu.iew.exec_rate 1.455255 # Inst execution rate -system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed -system.cpu.iew.exec_stores 7278167 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value -system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 64595544 # num instructions producing a value -system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle -system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 134796814 # number of integer regfile reads -system.cpu.int_regfile_writes 73485618 # number of integer regfile writes -system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads +system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued @@ -314,190 +204,300 @@ system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued -system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes +system.cpu.iq.rate 1.490981 # Inst issue rate system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle -system.cpu.iq.rate 1.490981 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 17397343 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 17397269 # ITB hits -system.cpu.itb.fetch_misses 74 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency +system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 11194543 # number of nop insts executed +system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed +system.cpu.iew.exec_branches 12448390 # Number of branches executed +system.cpu.iew.exec_stores 7278167 # Number of stores executed +system.cpu.iew.exec_rate 1.455255 # Inst execution rate +system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64595544 # num instructions producing a value +system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle +system.cpu.commit.count 91903055 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 26497301 # Number of memory references committed +system.cpu.commit.loads 19996198 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 10240685 # Number of branches committed +system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. +system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. +system.cpu.commit.function_calls 1029620 # Number of function calls committed. +system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 186605606 # The number of ROB reads +system.cpu.rob.rob_writes 260771760 # The number of ROB writes +system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated +system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads +system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 134796814 # number of integer regfile reads +system.cpu.int_regfile_writes 73485618 # number of integer regfile writes +system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads +system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes +system.cpu.misc_regfile_reads 712206 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 8218 # number of replacements +system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use +system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits +system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits +system.cpu.icache.overall_hits 17386201 # number of overall hits +system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses +system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11068 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 160 # number of replacements +system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use +system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 30012251 # number of overall hits +system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses +system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8940 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7279 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits +system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5098 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7279 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5098 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 712206 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 68382153 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running -system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 469 # count of serializing insts renamed -system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 186605606 # The number of ROB reads -system.cpu.rob.rob_writes 260771760 # The number of ROB writes -system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index 8a2d657fe..6101328db 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:02:07 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 20 2011 12:19:40 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 17088cdf6..f61998e0c 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5556970 # Simulator instruction rate (inst/s) -host_mem_usage 199664 # Number of bytes of host memory used -host_seconds 16.54 # Real time elapsed on the host -host_tick_rate 2778455792 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated sim_ticks 45951567500 # Number of ticks simulated -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 3424834 # Simulator instruction rate (inst/s) +host_tick_rate 1712417014 # Simulator tick rate (ticks/s) +host_mem_usage 187848 # Number of bytes of host memory used +host_seconds 26.83 # Real time elapsed on the host +sim_insts 91903056 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 19996198 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 19996208 # DTB read accesses system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 91903136 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.data_hits 26497301 # DTB hits +system.cpu.dtb.data_misses 33 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 26497334 # DTB accesses system.cpu.itb.fetch_hits 91903089 # ITB hits system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 91903136 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls system.cpu.numCycles 91903136 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 91903136 # Number of busy cycles -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_fp_insts 6862064 # number of float instructions system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 91903136 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index c82977f3d..e569eee9e 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:05:08 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 20 2011 12:46:11 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index ea7e649f7..c41863436 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,255 +1,255 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2623121 # Simulator instruction rate (inst/s) -host_mem_usage 207408 # Number of bytes of host memory used -host_seconds 35.04 # Real time elapsed on the host -host_tick_rate 3389091421 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118740 # Number of seconds simulated sim_ticks 118740049000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26495078 # number of overall hits -system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2223 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1530436 # Simulator instruction rate (inst/s) +host_tick_rate 1977344021 # Simulator tick rate (ticks/s) +host_mem_usage 196484 # Number of bytes of host memory used +host_seconds 60.05 # Real time elapsed on the host +sim_insts 91903056 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 19996198 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 19996208 # DTB read accesses system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.data_hits 26497301 # DTB hits +system.cpu.dtb.data_misses 33 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 26497334 # DTB accesses +system.cpu.itb.fetch_hits 91903090 # ITB hits +system.cpu.itb.fetch_misses 47 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 91903137 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 237480098 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_store_insts 6501126 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 237480098 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 6681 # number of replacements +system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use +system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits +system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits +system.cpu.icache.overall_hits 91894580 # number of overall hits +system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses +system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses +system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses -system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses +system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses -system.cpu.icache.overall_misses 8510 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use -system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 91903137 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 91903090 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 157 # number of replacements +system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use +system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 107 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 5968 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits +system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 4765 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5968 # number of overall hits -system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4765 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237480098 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 237480098 # Number of busy cycles -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |