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author | Korey Sewell <ksewell@umich.edu> | 2011-06-12 21:35:03 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-06-12 21:35:03 -0400 |
commit | 1aa4869ff046d0a039f132de49c8cfe28a6566cf (patch) | |
tree | 2523e4e0a795f08bdf506445ff2bf58d2b132544 /tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic | |
parent | fb8c95824144d1984539f7a918086f87858ff27d (diff) | |
download | gem5-1aa4869ff046d0a039f132de49c8cfe28a6566cf.tar.xz |
sparc: update long regressions
Diffstat (limited to 'tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic')
3 files changed, 31 insertions, 33 deletions
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr index 56e10add5..179231b2e 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: Don't know what interrupt to clear for console. -For more information see: http://www.m5sim.org/warn/7fe1004f hack: be nice to actually delete the event here diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index 62a971a25..39438a2c7 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -1,16 +1,17 @@ -M5 Simulator System +Redirecting stdout to build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout +Redirecting stderr to build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:08 -M5 started Apr 19 2011 12:22:10 -M5 executing on maize -command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic +gem5 compiled Jun 12 2011 07:35:14 +gem5 started Jun 12 2011 07:35:20 +gem5 executing on zizzer +command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... + 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 + + 0: system.t1000.htod: Real-time clock set to 1230768000 info: Entering event queue @ 0. Starting simulation... info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 3bd8ad178..4b265dc78 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4668188 # Simulator instruction rate (inst/s) -host_mem_usage 504368 # Number of bytes of host memory used -host_seconds 477.52 # Real time elapsed on the host -host_tick_rate 4677854 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 2229160714 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated sim_ticks 2233777512 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 2000000000 # Frequency of simulated ticks +host_inst_rate 2349387 # Simulator instruction rate (inst/s) +host_tick_rate 2354253 # Simulator tick rate (ticks/s) +host_mem_usage 524024 # Number of bytes of host memory used +host_seconds 948.83 # Real time elapsed on the host +sim_insts 2229160714 # Number of instructions simulated system.cpu.numCycles 2233777513 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 2233777513 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses -system.cpu.num_fp_insts 14608322 # number of float instructions -system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read -system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 2229160714 # Number of instructions executed system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses +system.cpu.num_func_calls 44037246 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls system.cpu.num_int_insts 1839325658 # number of integer instructions +system.cpu.num_fp_insts 14608322 # number of float instructions system.cpu.num_int_register_reads 4304894311 # number of times the integer registers were read system.cpu.num_int_register_writes 2108336490 # number of times the integer registers were written -system.cpu.num_load_insts 349807670 # Number of load instructions +system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read +system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written system.cpu.num_mem_refs 547951940 # number of memory refs +system.cpu.num_load_insts 349807670 # Number of load instructions system.cpu.num_store_insts 198144270 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 2233777513 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |