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authorGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
commitc3d41a2def15cdaf2ac3984315f452dacc6a0884 (patch)
tree5324ebec3add54b934a841eee901983ac3463a7f /tests/long/80.solaris-boot/ref/sparc/solaris
parentda2a4acc26ba264c3c4a12495776fd6a1c4fb133 (diff)
parent4acca8a0536d4445ed25b67edf571ae460446ab9 (diff)
downloadgem5-c3d41a2def15cdaf2ac3984315f452dacc6a0884.tar.xz
Merge with the main repo.
--HG-- rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'tests/long/80.solaris-boot/ref/sparc/solaris')
-rw-r--r--tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini25
-rwxr-xr-xtests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout8
-rw-r--r--tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt63
3 files changed, 75 insertions, 21 deletions
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 395184da9..409b736b6 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -19,7 +19,8 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
-memories=system.nvram system.physmem2 system.partition_desc system.physmem system.hypervisor_desc system.rom
+memories=system.physmem2 system.nvram system.partition_desc system.rom system.physmem system.hypervisor_desc
+num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
nvram_bin=/dist/m5/system/binaries/nvram1
@@ -41,20 +42,18 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[9]
[system.bridge]
type=Bridge
delay=100
-filter_ranges_a=
-filter_ranges_b=
nack_delay=8
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
+req_size=16
+resp_size=16
write_ack=false
-side_a=system.iobus.port[14]
-side_b=system.membus.port[2]
+master=system.iobus.port[14]
+slave=system.membus.port[2]
[system.cpu]
type=AtomicSimpleCPU
@@ -84,8 +83,8 @@ simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
-dcache_port=system.membus.port[10]
-icache_port=system.membus.port[9]
+dcache_port=system.membus.port[11]
+icache_port=system.membus.port[10]
[system.cpu.dtb]
type=SparcTLB
@@ -146,7 +145,7 @@ clock=2
header_cycles=1
use_default_range=false
width=64
-port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.side_a system.disk0.pio
+port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.master system.disk0.pio
[system.membus]
type=Bus
@@ -158,7 +157,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.badaddr_responder]
type=IsaFake
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index 6ef01a659..d81b5c20f 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -1,15 +1,15 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 27 2011 04:34:45
-gem5 started Nov 27 2011 04:35:04
-gem5 executing on chips
+gem5 compiled Jan 23 2012 04:05:05
+gem5 started Jan 23 2012 06:26:23
+gem5 executing on zizzer
command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second
-info: No kernel set for full system simulation. Assuming you know what you're doing...
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
0: system.t1000.htod: Real-time clock set to 1230768000
+info: No kernel set for full system simulation. Assuming you know what you're doing...
info: Entering event queue @ 0. Starting simulation...
info: Ignoring write to SPARC ERROR regsiter
info: Ignoring write to SPARC ERROR regsiter
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index a8935aa0a..21a50a501 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -2,12 +2,67 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.116889 # Number of seconds simulated
sim_ticks 2233777512 # Number of ticks simulated
+final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks
-host_inst_rate 941153 # Simulator instruction rate (inst/s)
-host_tick_rate 943102 # Simulator tick rate (ticks/s)
-host_mem_usage 535596 # Number of bytes of host memory used
-host_seconds 2368.54 # Real time elapsed on the host
+host_inst_rate 3505728 # Simulator instruction rate (inst/s)
+host_tick_rate 3512989 # Simulator tick rate (ticks/s)
+host_mem_usage 500940 # Number of bytes of host memory used
+host_seconds 635.86 # Real time elapsed on the host
sim_insts 2229160714 # Number of instructions simulated
+system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory
+system.hypervisor_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
+system.hypervisor_desc.bytes_written 0 # Number of bytes written to this memory
+system.hypervisor_desc.num_reads 9024 # Number of read requests responded to by this memory
+system.hypervisor_desc.num_writes 0 # Number of write requests responded to by this memory
+system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory
+system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s)
+system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s)
+system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory
+system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory
+system.physmem2.bytes_written 897268422 # Number of bytes written to this memory
+system.physmem2.num_reads 2403489130 # Number of read requests responded to by this memory
+system.physmem2.num_writes 187387796 # Number of write requests responded to by this memory
+system.physmem2.num_other 5403067 # Number of other requests responded to by this memory
+system.physmem2.bw_read 8786901931 # Total read bandwidth from this memory (bytes/s)
+system.physmem2.bw_inst_read 7447569684 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem2.bw_write 803364182 # Write bandwidth from this memory (bytes/s)
+system.physmem2.bw_total 9590266113 # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bytes_read 284 # Number of bytes read from this memory
+system.nvram.bytes_inst_read 0 # Number of instructions bytes read from this memory
+system.nvram.bytes_written 92 # Number of bytes written to this memory
+system.nvram.num_reads 284 # Number of read requests responded to by this memory
+system.nvram.num_writes 92 # Number of write requests responded to by this memory
+system.nvram.num_other 0 # Number of other requests responded to by this memory
+system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s)
+system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
+system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
+system.partition_desc.bytes_written 0 # Number of bytes written to this memory
+system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
+system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
+system.partition_desc.num_other 0 # Number of other requests responded to by this memory
+system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read 1128688 # Number of bytes read from this memory
+system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
+system.rom.bytes_written 0 # Number of bytes written to this memory
+system.rom.num_reads 195123 # Number of read requests responded to by this memory
+system.rom.num_writes 0 # Number of write requests responded to by this memory
+system.rom.num_other 0 # Number of other requests responded to by this memory
+system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read 709825348 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 15400223 # Number of bytes written to this memory
+system.physmem.num_reads 165224885 # Number of read requests responded to by this memory
+system.physmem.num_writes 1927067 # Number of write requests responded to by this memory
+system.physmem.num_other 14 # Number of other requests responded to by this memory
+system.physmem.bw_read 635538091 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s)
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed