diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
| commit | 93c0307d418e08db609818f19f5d2b02d45e7465 (patch) | |
| tree | 1f72a6617fb4a74d904a933bc48136fa0760bd19 /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt | |
| parent | f2db2a96d181f796e6e475121f10230b9d1d007f (diff) | |
| download | gem5-93c0307d418e08db609818f19f5d2b02d45e7465.tar.xz | |
tests: Update regressions for the new kernels and various preceeding fixes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 498e99dcf..85db7b5af 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.883224 # Nu sim_ticks 1883224346500 # Number of ticks simulated final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 293967 # Simulator instruction rate (inst/s) -host_op_rate 293967 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9864607727 # Simulator tick rate (ticks/s) -host_mem_usage 317632 # Number of bytes of host memory used -host_seconds 190.91 # Real time elapsed on the host +host_inst_rate 279379 # Simulator instruction rate (inst/s) +host_op_rate 279379 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9375076807 # Simulator tick rate (ticks/s) +host_mem_usage 311380 # Number of bytes of host memory used +host_seconds 200.88 # Real time elapsed on the host sim_insts 56120453 # Number of instructions simulated sim_ops 56120453 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -409,8 +409,6 @@ system.iocache.fast_writes 41552 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses @@ -425,16 +423,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency |