stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

1 files changed, 57 insertions, 5 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index 2f001f46a..ba2f5bb49 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  1.907083                       # Nu
 sim_ticks                                1907083088000                       # Number of ticks simulated
 final_tick                               1907083088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20329                       # Simulator instruction rate (inst/s)
-host_op_rate                                    20329                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              690572794                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384580                       # Number of bytes of host memory used
-host_seconds                                  2761.60                       # Real time elapsed on the host
+host_inst_rate                                  17729                       # Simulator instruction rate (inst/s)
+host_op_rate                                    17729                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              602270723                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 432228                       # Number of bytes of host memory used
+host_seconds                                  3166.49                       # Real time elapsed on the host
 sim_insts                                    56139550                       # Number of instructions simulated
 sim_ops                                      56139550                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst           1045632                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          24852608                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
@@ -299,6 +300,8 @@ system.physmem_1.memoryStateTime::REF     63681540000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT     40135521250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                15213605                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          13089935                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            512661                       # Number of conditional branches incorrect
@@ -345,6 +348,16 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.numPwrStateTransitions               12752                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples          6376                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     281609048.541405                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    439540029.573258                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         6376    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value        10500                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total            6376                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    111543794500                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1795539293500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        223105667                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -477,6 +490,7 @@ system.cpu.kern.mode_ticks::idle         1863670965500     97.72%    100.00% # n
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.cpu.tickCycles                        85299333                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                       137806334                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements           1394573                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.976747                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            13828974                       # Total number of references to valid blocks.
@@ -493,6 +507,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2           69
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          63880747                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         63880747                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data      7869575                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total         7869575                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      5576818                       # number of WriteReq hits
@@ -629,6 +644,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements           1471396                       # number of replacements
 system.cpu.icache.tags.tagsinuse           508.107952                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            19138982                       # Total number of references to valid blocks.
@@ -645,6 +661,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          405
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses          22083145                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses         22083145                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst     19138985                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        19138985                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      19138985                       # number of demand (read+write) hits
@@ -713,6 +730,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974
 system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           339491                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65257.604073                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            5020229                       # Total number of references to valid blocks.
@@ -735,6 +753,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55510
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         46558497                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        46558497                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       837991                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       837991                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks      1470820                       # number of WritebackClean hits
@@ -911,6 +930,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1963
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1250                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1250                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       2570147                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9623                       # Transaction distribution
@@ -964,6 +984,7 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51175                       # Transaction distribution
@@ -1018,6 +1039,7 @@ system.iobus.respLayer0.occupancy            23483000                       # La
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41685                       # number of replacements
 system.iocache.tags.tagsinuse                1.298739                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -1032,6 +1054,7 @@ system.iocache.tags.age_task_id_blocks_1023::2           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -1112,6 +1135,7 @@ system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261
 system.iocache.demand_avg_mshr_miss_latency::total 76193.945261                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 76193.945261                       # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
 system.membus.trans_dist::ReadResp             295608                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9623                       # Transaction distribution
@@ -1160,6 +1184,11 @@ system.membus.respLayer1.occupancy         2159448000                       # La
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy             943117                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1191,5 +1220,28 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907083088000                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------