diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt | 1409 |
1 files changed, 698 insertions, 711 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index c02ff892c..fcaff51da 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906049 # Number of seconds simulated -sim_ticks 1906048606500 # Number of ticks simulated -final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906052 # Number of seconds simulated +sim_ticks 1906052165500 # Number of ticks simulated +final_tick 1906052165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 268534 # Simulator instruction rate (inst/s) -host_op_rate 268534 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9116285517 # Simulator tick rate (ticks/s) -host_mem_usage 332204 # Number of bytes of host memory used -host_seconds 209.08 # Real time elapsed on the host -sim_insts 56145568 # Number of instructions simulated -sim_ops 56145568 # Number of ops (including micro ops) simulated +host_inst_rate 263346 # Simulator instruction rate (inst/s) +host_op_rate 263346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8940174363 # Simulator tick rate (ticks/s) +host_mem_usage 335264 # Number of bytes of host memory used +host_seconds 213.20 # Real time elapsed on the host +sim_insts 56145499 # Number of instructions simulated +sim_ops 56145499 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858688 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25904384 # Number of bytes read from this memory +system.physmem.bytes_read::total 25904320 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1044672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1044672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7563136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7563136 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7563072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7563072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 16323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388417 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404756 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118174 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118174 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 548083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13042035 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404755 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118173 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 548082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13041977 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13590621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3967966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3967966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3967966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13042035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13590562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 548082 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 548082 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3967925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3967925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3967925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 548082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13041977 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17558587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404756 # Number of read requests accepted -system.physmem.writeReqs 118174 # Number of write requests accepted -system.physmem.readBursts 404756 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118174 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25897280 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17558487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404755 # Number of read requests accepted +system.physmem.writeReqs 118173 # Number of write requests accepted +system.physmem.readBursts 404755 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25897216 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7561536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25904384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7563136 # Total written bytes from the system interface side +system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25904320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7563072 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303809 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25477 # Per bank write bursts system.physmem.perBankRdBursts::1 25704 # Per bank write bursts system.physmem.perBankRdBursts::2 25816 # Per bank write bursts -system.physmem.perBankRdBursts::3 25780 # Per bank write bursts +system.physmem.perBankRdBursts::3 25781 # Per bank write bursts system.physmem.perBankRdBursts::4 25083 # Per bank write bursts -system.physmem.perBankRdBursts::5 25011 # Per bank write bursts +system.physmem.perBankRdBursts::5 25010 # Per bank write bursts system.physmem.perBankRdBursts::6 24709 # Per bank write bursts system.physmem.perBankRdBursts::7 24576 # Per bank write bursts -system.physmem.perBankRdBursts::8 25197 # Per bank write bursts +system.physmem.perBankRdBursts::8 25196 # Per bank write bursts system.physmem.perBankRdBursts::9 25297 # Per bank write bursts system.physmem.perBankRdBursts::10 25389 # Per bank write bursts system.physmem.perBankRdBursts::11 25021 # Per bank write bursts -system.physmem.perBankRdBursts::12 24535 # Per bank write bursts +system.physmem.perBankRdBursts::12 24534 # Per bank write bursts system.physmem.perBankRdBursts::13 25530 # Per bank write bursts system.physmem.perBankRdBursts::14 25795 # Per bank write bursts -system.physmem.perBankRdBursts::15 25725 # Per bank write bursts +system.physmem.perBankRdBursts::15 25726 # Per bank write bursts system.physmem.perBankWrBursts::0 7822 # Per bank write bursts system.physmem.perBankWrBursts::1 7672 # Per bank write bursts system.physmem.perBankWrBursts::2 8075 # Per bank write bursts -system.physmem.perBankWrBursts::3 7744 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts system.physmem.perBankWrBursts::4 7196 # Per bank write bursts system.physmem.perBankWrBursts::5 7016 # Per bank write bursts system.physmem.perBankWrBursts::6 6702 # Per bank write bursts system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7310 # Per bank write bursts +system.physmem.perBankWrBursts::8 7309 # Per bank write bursts system.physmem.perBankWrBursts::9 6908 # Per bank write bursts -system.physmem.perBankWrBursts::10 7272 # Per bank write bursts +system.physmem.perBankWrBursts::10 7271 # Per bank write bursts system.physmem.perBankWrBursts::11 7002 # Per bank write bursts system.physmem.perBankWrBursts::12 7086 # Per bank write bursts system.physmem.perBankWrBursts::13 7981 # Per bank write bursts system.physmem.perBankWrBursts::14 7993 # Per bank write bursts -system.physmem.perBankWrBursts::15 7943 # Per bank write bursts +system.physmem.perBankWrBursts::15 7947 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1906039923500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1906043365500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404756 # Read request sizes (log2) +system.physmem.readPktSize::6 404755 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118174 # Write request sizes (log2) +system.physmem.writePktSize::6 118173 # Write request sizes (log2) system.physmem.rdQLenPdf::0 402408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -148,124 +148,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 519.546832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.268868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 407.153797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14837 23.04% 23.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11098 17.23% 40.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4944 7.68% 47.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3257 5.06% 53.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2526 3.92% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1968 3.06% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4176 6.48% 66.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1357 2.11% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20237 31.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64400 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5299 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 519.089377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 317.985274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 407.069012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14849 23.04% 23.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11122 17.25% 40.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4951 7.68% 47.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3330 5.17% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2494 3.87% 57.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1955 3.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4176 6.48% 66.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1342 2.08% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20238 31.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64457 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.462207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2902.463532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5289 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5302 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.283855 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.921998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.156721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4666 88.00% 88.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 22 0.41% 88.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 20 0.38% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 187 3.53% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 6 0.11% 92.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.47% 92.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.81% 93.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 93.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.15% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.34% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 6 0.11% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 18 0.34% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.47% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 27 0.51% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.04% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 172 3.24% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.13% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.06% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 7 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 8 0.15% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads -system.physmem.totQLat 2637486000 # Total ticks spent queuing -system.physmem.totMemAccLat 10224579750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6518.02 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.326531 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.072850 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.540172 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4687 88.57% 88.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.64% 89.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 32 0.60% 89.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 42 0.79% 90.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 211 3.99% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 8 0.15% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 13 0.25% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 25 0.47% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 188 3.55% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.06% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 3 0.06% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.09% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 11 0.21% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.17% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads +system.physmem.totQLat 2635925000 # Total ticks spent queuing +system.physmem.totMemAccLat 10223000000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6514.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25268.02 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25264.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s @@ -275,71 +263,71 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing -system.physmem.readRowHits 362820 # Number of row buffer hits during reads -system.physmem.writeRowHits 95574 # Number of row buffer hits during writes +system.physmem.avgWrQLen 26.36 # Average write queue length when enqueuing +system.physmem.readRowHits 362809 # Number of row buffer hits during reads +system.physmem.writeRowHits 95530 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes -system.physmem.avgGap 3644923.65 # Average gap between requests -system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 237573000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 129628125 # Energy for precharge commands per rank (pJ) +system.physmem.writeRowHitRate 80.84 # Row buffer hit rate for writes +system.physmem.avgGap 3644944.17 # Average gap between requests +system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238124880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 129929250 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67955758245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1084015546500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278788854350 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.912874 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1803098707000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states +system.physmem_0.writeEnergy 380084400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67910384250 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084060020000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278789321900 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.910378 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1803172860750 # Time in different power states +system.physmem_0.memoryStateTime::REF 63647220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39297448000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39230820500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249291000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136021875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68412640320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1083614781000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278871129755 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.956034 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1802432810250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states +system.physmem_1.actEnergy 249170040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135955875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579406400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385540560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68468592375 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1083570372000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278882999570 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.959521 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1802360809750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63647220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 39963358500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 40042885250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15009028 # Number of BP lookups -system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370758 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9666577 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5199223 # Number of BTB hits +system.cpu.branchPred.lookups 15006509 # Number of BP lookups +system.cpu.branchPred.condPredicted 13016597 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 371031 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9764467 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5201318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.785564 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807911 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 31459 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.267813 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807808 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31462 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9243045 # DTB read hits -system.cpu.dtb.read_misses 17179 # DTB read misses +system.cpu.dtb.read_hits 9242631 # DTB read hits +system.cpu.dtb.read_misses 17134 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 765860 # DTB read accesses -system.cpu.dtb.write_hits 6388437 # DTB write hits +system.cpu.dtb.read_accesses 765515 # DTB read accesses +system.cpu.dtb.write_hits 6388389 # DTB write hits system.cpu.dtb.write_misses 2336 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298458 # DTB write accesses -system.cpu.dtb.data_hits 15631482 # DTB hits -system.cpu.dtb.data_misses 19515 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064318 # DTB accesses -system.cpu.itb.fetch_hits 4012772 # ITB hits -system.cpu.itb.fetch_misses 6839 # ITB misses -system.cpu.itb.fetch_acv 666 # ITB acv -system.cpu.itb.fetch_accesses 4019611 # ITB accesses +system.cpu.dtb.write_acv 160 # DTB write access violations +system.cpu.dtb.write_accesses 298460 # DTB write accesses +system.cpu.dtb.data_hits 15631020 # DTB hits +system.cpu.dtb.data_misses 19470 # DTB misses +system.cpu.dtb.data_acv 371 # DTB access violations +system.cpu.dtb.data_accesses 1063975 # DTB accesses +system.cpu.itb.fetch_hits 4014011 # ITB hits +system.cpu.itb.fetch_misses 6826 # ITB misses +system.cpu.itb.fetch_acv 642 # ITB acv +system.cpu.itb.fetch_accesses 4020837 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -352,39 +340,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 221706697 # number of cpu cycles simulated +system.cpu.numCycles 221712638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56145568 # Number of instructions committed -system.cpu.committedOps 56145568 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2506376 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5532 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3590390516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.948784 # CPI: cycles per instruction -system.cpu.ipc 0.253243 # IPC: instructions per cycle +system.cpu.committedInsts 56145499 # Number of instructions committed +system.cpu.committedOps 56145499 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2504937 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5531 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3590391693 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.948894 # CPI: cycles per instruction +system.cpu.ipc 0.253235 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211538 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211539 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74805 40.93% 40.93% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105906 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182748 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105907 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182749 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837271633000 96.39% 96.39% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 67985179000 3.57% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1837274169000 96.39% 96.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 83596500 0.00% 96.40% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 707455500 0.04% 96.43% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 67985922500 3.57% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1906051143500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693436 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814860 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814855 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -423,7 +411,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175581 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175582 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -432,103 +420,103 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192472 # number of callpals executed +system.cpu.kern.callpal::total 192473 # number of callpals executed system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.324370 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324541 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392706 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 38725166000 2.03% 2.03% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4529345500 0.24% 2.27% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862796622000 97.73% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 84511215 # Number of cycles that the object actually ticked -system.cpu.idleCycles 137195482 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 84517271 # Number of cycles that the object actually ticked +system.cpu.idleCycles 137195367 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1395430 # number of replacements system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13774435 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.867732 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.867484 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63671171 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63671171 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182827 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182827 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63669791 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63669791 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576828 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576828 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182828 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199029 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199029 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13392891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13392891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13392891 # number of overall hits -system.cpu.dcache.overall_hits::total 13392891 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201631 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201631 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 575205 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 575205 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17224 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17224 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1776836 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses -system.cpu.dcache.overall_misses::total 1776836 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974912500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 46974912500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956321000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33956321000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80931233500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80931233500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80931233500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80931233500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152051 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200051 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200051 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13392545 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392545 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392545 # number of overall hits +system.cpu.dcache.overall_hits::total 13392545 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201618 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 575220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 575220 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17222 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17222 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776838 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776838 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776838 # number of overall misses +system.cpu.dcache.overall_misses::total 1776838 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46968047500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46968047500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964546500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33964546500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 234897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80932594000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80932594000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80932594000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80932594000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9017335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9017335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152048 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152048 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200050 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200050 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15169727 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15169727 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15169727 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15169727 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093498 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093498 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086098 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086098 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117130 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45547.947869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45547.947869 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 15169383 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15169383 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15169383 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15169383 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133256 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133256 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093501 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093501 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117133 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117133 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117133 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117133 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39087.336824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39087.336824 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59046.184938 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59046.184938 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13639.385669 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13639.385669 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45548.662287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45548.662287 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,84 +525,84 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838232 # number of writebacks -system.cpu.dcache.writebacks::total 838232 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127276 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127276 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270800 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270800 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838230 # number of writebacks +system.cpu.dcache.writebacks::total 838230 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127262 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127262 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270814 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 270814 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 398076 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 398076 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 398076 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 398076 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074355 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074355 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304405 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304405 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17221 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17221 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378760 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378760 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378760 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378760 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074356 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074356 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304406 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378762 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378762 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378762 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378762 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272477000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272477000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217466000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217466000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089868500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61089868500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089868500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61089868500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529366500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529366500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691875000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691875000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119139 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119139 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43812536500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43812536500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17276327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17276327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217413000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217413000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61088864000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61088864000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61088864000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61088864000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529368000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529368000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162483000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162483000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691851000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691851000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119143 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119143 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049480 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086083 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086083 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090889 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090889 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40784.835087 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40784.835087 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.765083 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.765083 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224699.553200 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224699.553200 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222966.239884 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222966.239884 # average overall mshr uncacheable latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086073 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086073 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090891 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090891 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090891 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090891 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40780.278139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40780.278139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56754.227906 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56754.227906 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12626.342993 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12626.342993 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.040664 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.040664 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.040664 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.040664 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.715316 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.715316 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224696.903574 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224696.903574 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222964.790434 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222964.790434 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1460396 # number of replacements -system.cpu.icache.tags.tagsinuse 508.105648 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18947783 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1460907 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.969876 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1460482 # number of replacements +system.cpu.icache.tags.tagsinuse 508.105568 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18950550 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1460993 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.971007 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 50119711500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.105648 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 508.105568 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -622,44 +610,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 103 system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21869952 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21869952 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18947786 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18947786 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18947786 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18947786 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18947786 # number of overall hits -system.cpu.icache.overall_hits::total 18947786 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1461083 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1461083 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1461083 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1461083 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1461083 # number of overall misses -system.cpu.icache.overall_misses::total 1461083 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009954000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21009954000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21009954000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21009954000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21009954000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21009954000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20408869 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20408869 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20408869 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20408869 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20408869 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20408869 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071591 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071591 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071591 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071591 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071591 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071591 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.712857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14379.712857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14379.712857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14379.712857 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21872887 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21872887 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18950553 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18950553 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18950553 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18950553 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18950553 # number of overall hits +system.cpu.icache.overall_hits::total 18950553 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1461167 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1461167 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1461167 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1461167 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1461167 # number of overall misses +system.cpu.icache.overall_misses::total 1461167 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009920000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21009920000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21009920000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21009920000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21009920000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21009920000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20411720 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20411720 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20411720 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20411720 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20411720 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20411720 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071585 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071585 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071585 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071585 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071585 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071585 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14378.862923 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14378.862923 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14378.862923 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14378.862923 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14378.862923 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14378.862923 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -668,147 +656,147 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1460396 # number of writebacks -system.cpu.icache.writebacks::total 1460396 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1461083 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1461083 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1461083 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1461083 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1461083 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1461083 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548871000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19548871000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548871000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19548871000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548871000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19548871000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071591 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071591 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071591 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.712857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.712857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1460482 # number of writebacks +system.cpu.icache.writebacks::total 1460482 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1461167 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1461167 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1461167 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1461167 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1461167 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1461167 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548753000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19548753000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548753000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19548753000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548753000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19548753000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071585 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071585 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071585 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13378.862923 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13378.862923 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13378.862923 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13378.862923 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13378.862923 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13378.862923 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 339568 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65260.797416 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4999517 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404730 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.352722 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 339567 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65260.796606 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4999675 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404729 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.353142 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 9687465000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251440 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150100 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 54046.207258 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.432786 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.156561 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.824680 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087347 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087348 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.083773 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.995801 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2929 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55509 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5613 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2925 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55513 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46396433 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46396433 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 838232 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 838232 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1459802 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1459802 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 46397707 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 46397707 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 838230 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 838230 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1459876 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1459876 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187755 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187755 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1444697 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1444697 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819338 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 819338 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1444697 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1007093 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2451790 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1444697 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1007093 # number of overall hits -system.cpu.l2cache.overall_hits::total 2451790 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116659 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116659 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187761 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187761 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1444783 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1444783 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819335 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 819335 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1444783 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1007096 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2451879 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1444783 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1007096 # number of overall hits +system.cpu.l2cache.overall_hits::total 2451879 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116656 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116656 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16324 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 16324 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272207 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 272207 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272208 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 272208 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 16324 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388866 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405190 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388864 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405188 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 16324 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388866 # number of overall misses -system.cpu.l2cache.overall_misses::total 405190 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 404000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 404000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837606000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14837606000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2142680000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2142680000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680454000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680454000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2142680000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48518060000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50660740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2142680000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48518060000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50660740000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 838232 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 838232 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1459802 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1459802 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1461021 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1461021 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091545 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1091545 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1461021 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1395959 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2856980 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1461021 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1395959 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2856980 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383225 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383225 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011173 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011173 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249378 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249378 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011173 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278565 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141825 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011173 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278565 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141825 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.838058 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.838058 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131259.495222 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131259.495222 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.035572 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.035572 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125029.591056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125029.591056 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 388864 # number of overall misses +system.cpu.l2cache.overall_misses::total 405188 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 397000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 397000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14841518500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14841518500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2141533000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2141533000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33675448500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33675448500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2141533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48516967000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50658500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2141533000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48516967000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50658500000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 838230 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 838230 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1459876 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1459876 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304417 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304417 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1461107 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1461107 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091543 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1091543 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1461107 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1395960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2857067 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1461107 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1395960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2857067 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809524 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383211 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383211 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011172 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011172 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249379 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249379 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011172 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278564 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141820 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011172 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278564 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141820 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23352.941176 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23352.941176 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127224.647682 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127224.647682 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131189.230581 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131189.230581 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123712.192515 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123712.192515 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131189.230581 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124765.900160 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125024.679902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131189.230581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124765.900160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125024.679902 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -817,129 +805,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76662 # number of writebacks -system.cpu.l2cache.writebacks::total 76662 # number of writebacks -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116659 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116659 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 76661 # number of writebacks +system.cpu.l2cache.writebacks::total 76661 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116656 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116656 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16324 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16324 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272207 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272207 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272208 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272208 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 16324 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388866 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405190 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388864 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405188 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 16324 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388866 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405190 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388864 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405188 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13671016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13671016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1979440000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1979440000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960462500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960462500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1979440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631478500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46610918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1979440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631478500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46610918500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442671000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442671000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494502500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494502500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011173 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249378 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249378 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141825 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1175000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1175000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13674958500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13674958500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978293000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978293000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30955575000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30955575000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978293000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44630533500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46608826500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978293000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44630533500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46608826500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442672500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442672500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494478500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494478500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383211 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383211 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011172 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249379 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249379 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141820 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141820 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69117.647059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69117.647059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117224.647682 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117224.647682 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121189.230581 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121189.230581 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113720.298448 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113720.298448 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.758869 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.758869 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213196.799667 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213196.799667 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211044.721585 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211044.721585 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1248 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5713060 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856101 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1990 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1247 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2559702 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559783 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9624 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 956425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1459802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 818923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 956411 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1460482 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 820279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461167 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4381906 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8601216 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186932672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041565 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 329974237 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 423215 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3296619 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001032 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032108 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4382756 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4220664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8603420 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186981696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041437 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 330023133 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 423201 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3296691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001034 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032145 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3293217 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3402 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3293281 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3410 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3296619 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5168164000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3296691 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5168333000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191892463 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2192017465 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105680997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105681496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -983,39 +971,39 @@ system.iobus.pkt_size_system.bridge.master::total 44381 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5419000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 784500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 786000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 186500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 186000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14813500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14810500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5936500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215092991 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215720167 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.290814 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.290842 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1748612865000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.290814 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080676 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080676 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1748612862000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.290842 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080678 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080678 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1029,14 +1017,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21944383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21944383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429292608 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5429292608 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21944383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21944383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21944383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21944383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244742784 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5244742784 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1053,19 +1041,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126846.144509 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126846.144509 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130662.606084 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130662.606084 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126846.144509 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126846.144509 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 77 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126221.187524 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126221.187524 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.833333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1079,14 +1067,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13294383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351692608 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3351692608 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13294383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13294383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13294383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13294383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165341974 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165341974 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1095,63 +1083,62 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76846.144509 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80662.606084 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80662.606084 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.848816 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.848816 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6934 # Transaction distribution system.membus.trans_dist::ReadResp 295622 # Transaction distribution system.membus.trans_dist::WriteReq 9624 # Transaction distribution system.membus.trans_dist::WriteResp 9624 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118174 # Transaction distribution -system.membus.trans_dist::CleanEvict 262081 # Transaction distribution -system.membus.trans_dist::UpgradeReq 178 # Transaction distribution -system.membus.trans_dist::UpgradeResp 178 # Transaction distribution -system.membus.trans_dist::ReadExReq 116499 # Transaction distribution -system.membus.trans_dist::ReadExResp 116499 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288704 # Transaction distribution -system.membus.trans_dist::BadAddressError 16 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118173 # Transaction distribution +system.membus.trans_dist::CleanEvict 262241 # Transaction distribution +system.membus.trans_dist::UpgradeReq 175 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 116498 # Transaction distribution +system.membus.trans_dist::ReadExResp 116498 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288705 # Transaction distribution +system.membus.trans_dist::BadAddressError 17 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148839 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181807 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265232 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44381 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854173 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854045 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33511901 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33511773 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 843925 # Request fanout histogram +system.membus.snoop_fanout::samples 843910 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843925 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843910 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843925 # Request fanout histogram -system.membus.reqLayer0.occupancy 29573500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843910 # Request fanout histogram +system.membus.reqLayer0.occupancy 29565500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319381154 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319337462 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160244574 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2159897250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |