diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3669 |
1 files changed, 1846 insertions, 1823 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 683e407e9..05acb9522 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,126 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903124 # Number of seconds simulated -sim_ticks 1903123778500 # Number of ticks simulated -final_tick 1903123778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.905068 # Number of seconds simulated +sim_ticks 1905067807000 # Number of ticks simulated +final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 103415 # Simulator instruction rate (inst/s) -host_op_rate 103415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3505224116 # Simulator tick rate (ticks/s) -host_mem_usage 322696 # Number of bytes of host memory used -host_seconds 542.94 # Real time elapsed on the host -sim_insts 56148221 # Number of instructions simulated -sim_ops 56148221 # Number of ops (including micro ops) simulated +host_inst_rate 162284 # Simulator instruction rate (inst/s) +host_op_rate 162284 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5403466257 # Simulator tick rate (ticks/s) +host_mem_usage 375680 # Number of bytes of host memory used +host_seconds 352.56 # Real time elapsed on the host +sim_insts 57215334 # Number of instructions simulated +sim_ops 57215334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 744192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24296448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 865344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24709248 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 238144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1067328 # Number of bytes read from this memory -system.physmem.bytes_read::total 26347072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 744192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 238144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5275328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 118912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 545600 # Number of bytes read from this memory +system.physmem.bytes_read::total 26240064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 865344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 118912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 984256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5157696 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7934656 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 379632 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7817024 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386082 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16677 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411673 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82427 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8525 # Number of read requests responded to by this memory +system.physmem.num_reads::total 410001 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 80589 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123979 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 391037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12766615 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 122141 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 454233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12970272 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 125133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 560830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13844119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 391037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 125133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2771931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1397349 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4169280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2771931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 391037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12766615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 125133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 560830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18013399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411673 # Number of read requests accepted -system.physmem.writeReqs 123979 # Number of write requests accepted -system.physmem.readBursts 411673 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123979 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26335040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue -system.physmem.bytesWritten 7932928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26347072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7934656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_read::cpu1.inst 62419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 286394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13773822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 454233 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 62419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2707356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1395923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4103279 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2707356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 454233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12970272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1396427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 62419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 286394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17877100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410001 # Number of read requests accepted +system.physmem.writeReqs 122141 # Number of write requests accepted +system.physmem.readBursts 410001 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122141 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26227648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12416 # Total number of bytes read from write queue +system.physmem.bytesWritten 7815104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26240064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7817024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3444 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25632 # Per bank write bursts -system.physmem.perBankRdBursts::1 25720 # Per bank write bursts -system.physmem.perBankRdBursts::2 26346 # Per bank write bursts -system.physmem.perBankRdBursts::3 25660 # Per bank write bursts -system.physmem.perBankRdBursts::4 25672 # Per bank write bursts -system.physmem.perBankRdBursts::5 25150 # Per bank write bursts -system.physmem.perBankRdBursts::6 25568 # Per bank write bursts -system.physmem.perBankRdBursts::7 25491 # Per bank write bursts -system.physmem.perBankRdBursts::8 25973 # Per bank write bursts -system.physmem.perBankRdBursts::9 26167 # Per bank write bursts -system.physmem.perBankRdBursts::10 25812 # Per bank write bursts -system.physmem.perBankRdBursts::11 25687 # Per bank write bursts -system.physmem.perBankRdBursts::12 26023 # Per bank write bursts -system.physmem.perBankRdBursts::13 25844 # Per bank write bursts -system.physmem.perBankRdBursts::14 25108 # Per bank write bursts -system.physmem.perBankRdBursts::15 25632 # Per bank write bursts -system.physmem.perBankWrBursts::0 8431 # Per bank write bursts -system.physmem.perBankWrBursts::1 7989 # Per bank write bursts -system.physmem.perBankWrBursts::2 8275 # Per bank write bursts -system.physmem.perBankWrBursts::3 7382 # Per bank write bursts -system.physmem.perBankWrBursts::4 7684 # Per bank write bursts -system.physmem.perBankWrBursts::5 7400 # Per bank write bursts -system.physmem.perBankWrBursts::6 7193 # Per bank write bursts -system.physmem.perBankWrBursts::7 7021 # Per bank write bursts -system.physmem.perBankWrBursts::8 7374 # Per bank write bursts -system.physmem.perBankWrBursts::9 7755 # Per bank write bursts -system.physmem.perBankWrBursts::10 7777 # Per bank write bursts -system.physmem.perBankWrBursts::11 7454 # Per bank write bursts -system.physmem.perBankWrBursts::12 8052 # Per bank write bursts -system.physmem.perBankWrBursts::13 8097 # Per bank write bursts -system.physmem.perBankWrBursts::14 7762 # Per bank write bursts -system.physmem.perBankWrBursts::15 8306 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6364 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25988 # Per bank write bursts +system.physmem.perBankRdBursts::1 25697 # Per bank write bursts +system.physmem.perBankRdBursts::2 25753 # Per bank write bursts +system.physmem.perBankRdBursts::3 25768 # Per bank write bursts +system.physmem.perBankRdBursts::4 25192 # Per bank write bursts +system.physmem.perBankRdBursts::5 25524 # Per bank write bursts +system.physmem.perBankRdBursts::6 25779 # Per bank write bursts +system.physmem.perBankRdBursts::7 25095 # Per bank write bursts +system.physmem.perBankRdBursts::8 25528 # Per bank write bursts +system.physmem.perBankRdBursts::9 25751 # Per bank write bursts +system.physmem.perBankRdBursts::10 25719 # Per bank write bursts +system.physmem.perBankRdBursts::11 25446 # Per bank write bursts +system.physmem.perBankRdBursts::12 25795 # Per bank write bursts +system.physmem.perBankRdBursts::13 25643 # Per bank write bursts +system.physmem.perBankRdBursts::14 25930 # Per bank write bursts +system.physmem.perBankRdBursts::15 25199 # Per bank write bursts +system.physmem.perBankWrBursts::0 8301 # Per bank write bursts +system.physmem.perBankWrBursts::1 7506 # Per bank write bursts +system.physmem.perBankWrBursts::2 7807 # Per bank write bursts +system.physmem.perBankWrBursts::3 7337 # Per bank write bursts +system.physmem.perBankWrBursts::4 6902 # Per bank write bursts +system.physmem.perBankWrBursts::5 7063 # Per bank write bursts +system.physmem.perBankWrBursts::6 7447 # Per bank write bursts +system.physmem.perBankWrBursts::7 6982 # Per bank write bursts +system.physmem.perBankWrBursts::8 7245 # Per bank write bursts +system.physmem.perBankWrBursts::9 7339 # Per bank write bursts +system.physmem.perBankWrBursts::10 7570 # Per bank write bursts +system.physmem.perBankWrBursts::11 7510 # Per bank write bursts +system.physmem.perBankWrBursts::12 8378 # Per bank write bursts +system.physmem.perBankWrBursts::13 8362 # Per bank write bursts +system.physmem.perBankWrBursts::14 8512 # Per bank write bursts +system.physmem.perBankWrBursts::15 7850 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 1903119235000 # Total gap between requests +system.physmem.totGap 1905063366000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411673 # Read request sizes (log2) +system.physmem.readPktSize::6 410001 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123979 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -161,357 +161,367 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64910 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 527.930488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.008348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.202697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14944 23.02% 23.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11454 17.65% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5213 8.03% 48.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2920 4.50% 53.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2279 3.51% 56.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1787 2.75% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1551 2.39% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1716 2.64% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23046 35.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64910 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5635 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.021650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2812.727565 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5632 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64430 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 528.357101 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.789036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.784578 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14909 23.14% 23.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11361 17.63% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5102 7.92% 48.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2869 4.45% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2286 3.55% 56.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1687 2.62% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1558 2.42% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1655 2.57% 64.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23003 35.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64430 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.305712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2843.118152 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5512 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5635 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.996806 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.958563 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.289473 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4843 85.94% 85.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 143 2.54% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.18% 88.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 227 4.03% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 45 0.80% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.07% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 10 0.18% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.18% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 34 0.60% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.11% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.16% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 41 0.73% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 13 0.23% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.04% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 176 3.12% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.09% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.05% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.11% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 6 0.11% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 10 0.18% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.11% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5635 # Writes before turning the bus around for reads -system.physmem.totQLat 3887945250 # Total ticks spent queuing -system.physmem.totMemAccLat 11603289000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2057425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9448.57 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5515 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5515 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.141614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.970992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.024334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4751 86.15% 86.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 123 2.23% 88.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.27% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 231 4.19% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 39 0.71% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 12 0.22% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 8 0.15% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.07% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.42% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.05% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 94.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 28 0.51% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 10 0.18% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 17 0.31% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 177 3.21% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.05% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.07% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.04% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.09% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.09% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.15% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5515 # Writes before turning the bus around for reads +system.physmem.totQLat 3875472500 # Total ticks spent queuing +system.physmem.totMemAccLat 11559353750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9456.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28198.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28206.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing -system.physmem.readRowHits 371100 # Number of row buffer hits during reads -system.physmem.writeRowHits 99427 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.20 # Row buffer hit rate for writes -system.physmem.avgGap 3552902.32 # Average gap between requests -system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1802319562500 # Time in different power states -system.physmem.memoryStateTime::REF 63549460000 # Time in different power states +system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.10 # Average write queue length when enqueuing +system.physmem.readRowHits 369467 # Number of row buffer hits during reads +system.physmem.writeRowHits 98020 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.25 # Row buffer hit rate for writes +system.physmem.avgGap 3579990.62 # Average gap between requests +system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1804432107750 # Time in different power states +system.physmem.memoryStateTime::REF 63614200000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37254262500 # Time in different power states +system.physmem.memoryStateTime::ACT 37016700250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18054612 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296849 # Transaction distribution -system.membus.trans_dist::ReadResp 296569 # Transaction distribution -system.membus.trans_dist::WriteReq 12351 # Transaction distribution -system.membus.trans_dist::WriteResp 12351 # Transaction distribution -system.membus.trans_dist::Writeback 82427 # Transaction distribution +system.membus.trans_dist::ReadReq 296853 # Transaction distribution +system.membus.trans_dist::ReadResp 296773 # Transaction distribution +system.membus.trans_dist::WriteReq 13665 # Transaction distribution +system.membus.trans_dist::WriteResp 13665 # Transaction distribution +system.membus.trans_dist::Writeback 80589 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5284 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1479 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3444 # Transaction distribution -system.membus.trans_dist::ReadExReq 122594 # Transaction distribution -system.membus.trans_dist::ReadExResp 122459 # Transaction distribution -system.membus.trans_dist::BadAddressError 280 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 916085 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 955737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1039031 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68194 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31621440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31689634 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34349922 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34349922 # Total data (bytes) -system.membus.snoop_data_through_bus 10240 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35504996 # Layer occupancy (ticks) +system.membus.trans_dist::UpgradeReq 14563 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9639 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6364 # Transaction distribution +system.membus.trans_dist::ReadExReq 121274 # Transaction distribution +system.membus.trans_dist::ReadExResp 120582 # Transaction distribution +system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1056989 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78682 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31396800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31475482 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34135770 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 18692 # Total snoops (count) +system.membus.snoop_fanout::samples 557285 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 557285 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 557285 # Request fanout histogram +system.membus.reqLayer0.occupancy 40450499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1560042750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1545398747 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 374000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 102000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3834491323 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3825672402 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43141738 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43153245 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 345839 # number of replacements -system.l2c.tags.tagsinuse 65302.356632 # Cycle average of tags in use -system.l2c.tags.total_refs 2646364 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411006 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.438748 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7093732750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53566.898021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4193.415796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5564.276304 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1386.450480 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 591.316031 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.817366 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063986 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.084904 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021156 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996435 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2289 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6029 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6100 # 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number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015261 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.332577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006860 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.130622 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952645 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.878444 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.938855 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636364 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.735714 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.694561 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.433880 # 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average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65621.866792 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78042.483221 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76936.266874 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 66289.489183 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 342.897864 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2364.289668 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 694.387873 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3896.682540 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1825.165049 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2611.343373 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82509.538600 # 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number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12381383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12381383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512854560 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512854560 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12381383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12381383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -750,35 +764,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 13702956 # Number of BP lookups -system.cpu0.branchPred.condPredicted 11991857 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 276088 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8588922 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4683455 # Number of BTB hits +system.cpu0.branchPred.lookups 14962614 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13045209 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 300344 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9143692 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5116520 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 54.529020 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 677984 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 15448 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 55.956828 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 756655 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 14726 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7950804 # DTB read hits -system.cpu0.dtb.read_misses 30543 # DTB read misses -system.cpu0.dtb.read_acv 546 # DTB read access violations -system.cpu0.dtb.read_accesses 683229 # DTB read accesses -system.cpu0.dtb.write_hits 5159026 # DTB write hits -system.cpu0.dtb.write_misses 6845 # DTB write misses -system.cpu0.dtb.write_acv 353 # DTB write access violations -system.cpu0.dtb.write_accesses 234573 # DTB write accesses -system.cpu0.dtb.data_hits 13109830 # DTB hits -system.cpu0.dtb.data_misses 37388 # DTB misses -system.cpu0.dtb.data_acv 899 # DTB access violations -system.cpu0.dtb.data_accesses 917802 # DTB accesses -system.cpu0.itb.fetch_hits 1312718 # ITB hits -system.cpu0.itb.fetch_misses 29261 # ITB misses -system.cpu0.itb.fetch_acv 629 # ITB acv -system.cpu0.itb.fetch_accesses 1341979 # ITB accesses +system.cpu0.dtb.read_hits 8668714 # DTB read hits +system.cpu0.dtb.read_misses 31568 # DTB read misses +system.cpu0.dtb.read_acv 533 # DTB read access violations +system.cpu0.dtb.read_accesses 683834 # DTB read accesses +system.cpu0.dtb.write_hits 5507711 # DTB write hits +system.cpu0.dtb.write_misses 6832 # DTB write misses +system.cpu0.dtb.write_acv 377 # DTB write access violations +system.cpu0.dtb.write_accesses 235007 # DTB write accesses +system.cpu0.dtb.data_hits 14176425 # DTB hits +system.cpu0.dtb.data_misses 38400 # DTB misses +system.cpu0.dtb.data_acv 910 # DTB access violations +system.cpu0.dtb.data_accesses 918841 # DTB accesses +system.cpu0.itb.fetch_hits 1355401 # ITB hits +system.cpu0.itb.fetch_misses 29256 # ITB misses +system.cpu0.itb.fetch_acv 621 # ITB acv +system.cpu0.itb.fetch_accesses 1384657 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -791,304 +805,305 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 99665250 # number of cpu cycles simulated +system.cpu0.numCycles 108456707 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 22511576 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 60582407 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13702956 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5361439 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 70984108 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 933480 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 621 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 27412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1463366 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 292819 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7109889 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 200075 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 95746858 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.632735 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.928110 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24325754 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 66694894 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 14962614 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5873175 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 76828249 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1001726 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 825 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30281 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1454626 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 459540 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 204 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7777949 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 213350 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103600342 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.643771 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.943909 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 84335489 88.08% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 757900 0.79% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1598110 1.67% 90.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 658612 0.69% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2290747 2.39% 93.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 510807 0.53% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 540667 0.56% 94.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 744782 0.78% 95.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4309744 4.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 91056774 87.89% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 810107 0.78% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1760430 1.70% 90.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 739408 0.71% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2516394 2.43% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557837 0.54% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 633248 0.61% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 717698 0.69% 95.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4808446 4.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 95746858 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.137490 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.607859 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18154184 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 68366814 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7221268 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1568077 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 436514 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 432928 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 30567 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53177978 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 98719 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 436514 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18925396 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 44877173 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16564638 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 7942906 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7000229 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 51314401 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 200370 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1702156 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 121650 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3596195 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 34369689 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 62476617 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 62360377 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 107565 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30276917 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4092764 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1298231 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 191875 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11393500 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8037568 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5366781 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1135735 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 800748 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 45795204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1644687 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 45103865 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 41971 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5328763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2477826 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1134880 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 95746858 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.471074 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.201865 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103600342 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.137959 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614945 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19762809 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 73625982 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8017389 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1725855 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 468306 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 492047 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33030 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 58728782 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 102789 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 468306 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 20585060 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48251734 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17899835 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8819055 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7576350 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56729728 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 201548 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2018005 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 142949 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3756211 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 38050244 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 69305662 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69181835 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 114815 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33467059 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4583177 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1358842 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 197413 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12487165 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8791454 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5770533 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1295730 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 947864 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50680779 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1726956 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49798033 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52306 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5972660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2859786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1187974 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103600342 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.480674 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.214257 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 76985468 80.41% 80.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8252195 8.62% 89.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3430688 3.58% 92.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2350675 2.46% 95.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2374207 2.48% 97.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1175968 1.23% 98.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 779493 0.81% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 300669 0.31% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 97495 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 83011266 80.13% 80.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8965198 8.65% 88.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3720190 3.59% 92.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2652497 2.56% 94.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2683429 2.59% 97.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1272361 1.23% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 837773 0.81% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 348219 0.34% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109409 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 95746858 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103600342 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 143906 17.61% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 398143 48.73% 66.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 274956 33.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 174041 19.05% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 435557 47.67% 66.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 304020 33.28% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30829458 68.35% 68.36% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46395 0.10% 68.46% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 26948 0.06% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8252345 18.30% 86.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5217820 11.57% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 725236 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34383436 69.05% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54432 0.11% 69.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 27661 0.06% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8987932 18.05% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5577936 11.20% 98.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 760973 1.53% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 45103865 # Type of FU issued -system.cpu0.iq.rate 0.452554 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 817005 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018114 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 186342910 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 52562719 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43916640 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 470653 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 221373 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 216432 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 45663938 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 253152 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 522094 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49798033 # Type of FU issued +system.cpu0.iq.rate 0.459151 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 913618 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018346 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203658933 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 58161397 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48529720 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 503398 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 236532 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 231367 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50437037 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 270834 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 558638 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 946690 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4799 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15752 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 387148 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1034329 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17854 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 485625 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13610 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 357638 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18828 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348593 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 436514 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 41413967 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1424350 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50298451 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 103444 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8037568 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5366781 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1456887 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 31578 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1238658 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15752 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 134081 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 309122 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 443203 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 44677716 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8001376 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 426148 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 468306 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 44263410 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1515089 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 55600538 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 120472 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8791454 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5770533 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1526368 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 47186 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1245112 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17854 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151677 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 326896 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 478573 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49327282 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8721913 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 470750 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2858560 # number of nop insts executed -system.cpu0.iew.exec_refs 13178604 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7039370 # Number of branches executed -system.cpu0.iew.exec_stores 5177228 # Number of stores executed -system.cpu0.iew.exec_rate 0.448278 # Inst execution rate -system.cpu0.iew.wb_sent 44227196 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44133072 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22691402 # num instructions producing a value -system.cpu0.iew.wb_consumers 31140086 # num instructions consuming a value +system.cpu0.iew.exec_nop 3192803 # number of nop insts executed +system.cpu0.iew.exec_refs 14249477 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7854369 # Number of branches executed +system.cpu0.iew.exec_stores 5527564 # Number of stores executed +system.cpu0.iew.exec_rate 0.454811 # Inst execution rate +system.cpu0.iew.wb_sent 48871282 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48761087 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25232648 # num instructions producing a value +system.cpu0.iew.wb_consumers 34850080 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.442813 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.728688 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.724034 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5846321 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 509807 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 407712 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 94708833 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.468364 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.405169 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6529157 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 538982 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 437949 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102449449 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.477940 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.411753 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 79035549 83.45% 83.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6314508 6.67% 90.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3292930 3.48% 93.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1802282 1.90% 95.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1366338 1.44% 96.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 489382 0.52% 97.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 366889 0.39% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 390234 0.41% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1650721 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 85074848 83.04% 83.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6905483 6.74% 89.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3794087 3.70% 93.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1998795 1.95% 95.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1509892 1.47% 96.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 553563 0.54% 97.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 413229 0.40% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 408476 0.40% 98.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1791076 1.75% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 94708833 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 44358216 # Number of instructions committed -system.cpu0.commit.committedOps 44358216 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102449449 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48964739 # Number of instructions committed +system.cpu0.commit.committedOps 48964739 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12070511 # Number of memory references committed -system.cpu0.commit.loads 7090878 # Number of loads committed -system.cpu0.commit.membars 170277 # Number of memory barriers committed -system.cpu0.commit.branches 6663650 # Number of branches committed -system.cpu0.commit.fp_insts 213529 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 41141903 # Number of committed integer instructions. -system.cpu0.commit.function_calls 549728 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2498518 5.63% 5.63% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 28814427 64.96% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 45393 0.10% 70.69% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 26477 0.06% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7261155 16.37% 87.13% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 4985127 11.24% 98.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 725236 1.63% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13042033 # Number of memory references committed +system.cpu0.commit.loads 7757125 # Number of loads committed +system.cpu0.commit.membars 182252 # Number of memory barriers committed +system.cpu0.commit.branches 7421354 # Number of branches committed +system.cpu0.commit.fp_insts 228314 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45387875 # Number of committed integer instructions. +system.cpu0.commit.function_calls 614232 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2794177 5.71% 5.71% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32097051 65.55% 71.26% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 53183 0.11% 71.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 27190 0.06% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7939377 16.21% 87.64% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5290905 10.81% 98.45% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 760973 1.55% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 44358216 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1650721 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 48964739 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1791076 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 143064224 # The number of ROB reads -system.cpu0.rob.rob_writes 101447849 # The number of ROB writes -system.cpu0.timesIdled 414726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3918392 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3706577488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41863465 # Number of Instructions Simulated -system.cpu0.committedOps 41863465 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.380721 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.380721 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.420041 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.420041 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 58777310 # number of integer regfile reads -system.cpu0.int_regfile_writes 31962259 # number of integer regfile writes -system.cpu0.fp_regfile_reads 106639 # number of floating regfile reads -system.cpu0.fp_regfile_writes 106808 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1588469 # number of misc regfile reads -system.cpu0.misc_regfile_writes 729535 # number of misc regfile writes +system.cpu0.rob.rob_reads 155949601 # The number of ROB reads +system.cpu0.rob.rob_writes 112132496 # The number of ROB writes +system.cpu0.timesIdled 444606 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4856365 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3701678908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46174329 # Number of Instructions Simulated +system.cpu0.committedOps 46174329 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.348853 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.348853 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.425740 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.425740 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65048250 # number of integer regfile reads +system.cpu0.int_regfile_writes 35377381 # number of integer regfile writes +system.cpu0.fp_regfile_reads 113752 # number of floating regfile reads +system.cpu0.fp_regfile_writes 114375 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1675774 # number of misc regfile reads +system.cpu0.misc_regfile_writes 759002 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1120,50 +1135,61 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 115690704 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2250904 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2250609 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 841911 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2231724 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2231628 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13665 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13665 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 804733 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5326 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6878 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 312265 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 312265 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 280 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1525692 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2740000 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 708608 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1000724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5975024 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48817472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 104660497 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22674112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39558737 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 215710818 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 215700578 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4473152 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5085967365 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeReq 14709 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9717 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 24426 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295921 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295921 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1632137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3219560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 626624 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 407513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5885834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52223552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123671600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20051136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14868394 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 210814682 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 92075 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3391171 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012307 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110253 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3349435 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41736 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3391171 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4911486557 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 720000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3437989936 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3677796473 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4906988127 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5655554210 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1597018302 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1411093549 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1654443775 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1434388 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7370 # Transaction distribution -system.iobus.trans_dist::ReadResp 7370 # Transaction distribution -system.iobus.trans_dist::WriteReq 53903 # Transaction distribution -system.iobus.trans_dist::WriteResp 53903 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 701201756 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 55215 # Transaction distribution +system.iobus.trans_dist::WriteResp 55217 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 2 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 464 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1174,30 +1200,29 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39092 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122546 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68194 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729818 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729818 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9847000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 41714 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 78682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2740322 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12481000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 347000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1217,267 +1242,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374411689 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374418188 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26741000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28049000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42019262 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42021755 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 762211 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.848890 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6309809 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 762721 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.272762 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26485928250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.848890 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993845 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7872808 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7872808 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6309809 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6309809 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6309809 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6309809 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6309809 # number of overall hits -system.cpu0.icache.overall_hits::total 6309809 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 800080 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 800080 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 800080 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 800080 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 800080 # number of overall misses -system.cpu0.icache.overall_misses::total 800080 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11341096711 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11341096711 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11341096711 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11341096711 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11341096711 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11341096711 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7109889 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7109889 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7109889 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7109889 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7109889 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7109889 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112531 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.112531 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112531 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.112531 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112531 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.112531 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14174.953393 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14174.953393 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3387 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 815495 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.595712 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6922237 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 816007 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.483061 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485869250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.595712 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995304 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995304 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 411 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8594091 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8594091 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6922237 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6922237 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6922237 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6922237 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6922237 # number of overall hits +system.cpu0.icache.overall_hits::total 6922237 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 855710 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 855710 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 855710 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 855710 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 855710 # number of overall misses +system.cpu0.icache.overall_misses::total 855710 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12231378721 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12231378721 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12231378721 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12231378721 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12231378721 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12231378721 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7777947 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7777947 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7777947 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7777947 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7777947 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7777947 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110017 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110017 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110017 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110017 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110017 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110017 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14293.836371 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14293.836371 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14293.836371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14293.836371 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4554 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 181 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.907407 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.160221 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37161 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 37161 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37161 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 37161 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37161 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 37161 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 762919 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 762919 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 762919 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 762919 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 762919 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 762919 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9350852559 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9350852559 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9350852559 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9350852559 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9350852559 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9350852559 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.107304 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.107304 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.107304 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39566 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 39566 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 39566 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 39566 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 39566 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 39566 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 816144 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 816144 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 816144 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 816144 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 816144 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 816144 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10088624022 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10088624022 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10088624022 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10088624022 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10088624022 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10088624022 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104931 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.104931 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.104931 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12361.328420 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1069035 # number of replacements -system.cpu0.dcache.tags.tagsinuse 482.779727 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9141371 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1069547 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.546956 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1223787 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.953471 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9930066 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1224299 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.110818 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.779727 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942929 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.942929 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.953471 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988190 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988190 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 49546788 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 49546788 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5665393 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5665393 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3152024 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3152024 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147109 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147109 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 170256 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 170256 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8817417 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8817417 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8817417 # number of overall hits -system.cpu0.dcache.overall_hits::total 8817417 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1322171 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1322171 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1644281 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1644281 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16610 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16610 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2966452 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2966452 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2966452 # number of overall misses -system.cpu0.dcache.overall_misses::total 2966452 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36169344894 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36169344894 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74324803897 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 74324803897 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 267182493 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 267182493 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4788059 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4788059 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 110494148791 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 110494148791 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6987564 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6987564 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4796305 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4796305 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 163719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 171022 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 171022 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11783869 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11783869 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11783869 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11783869 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.189218 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.189218 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342822 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.342822 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101454 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101454 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004479 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004479 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251738 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.251738 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251738 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.251738 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27356.026485 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6250.729765 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6250.729765 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3702426 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3454 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 160595 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 88 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.054429 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 39.250000 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 53654077 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 53654077 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6167393 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6167393 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3426848 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3426848 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 149101 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 149101 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171294 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171294 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9594241 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9594241 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9594241 # number of overall hits +system.cpu0.dcache.overall_hits::total 9594241 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1498647 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1498647 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1667216 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1667216 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19081 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19081 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4721 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4721 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3165863 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3165863 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3165863 # number of overall misses +system.cpu0.dcache.overall_misses::total 3165863 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39188841077 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39188841077 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77581958562 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77581958562 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288599741 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 288599741 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35650235 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 35650235 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 116770799639 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 116770799639 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 116770799639 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 116770799639 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7666040 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7666040 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5094064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5094064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168182 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 168182 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 176015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12760104 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12760104 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12760104 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12760104 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195492 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.195492 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327286 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.327286 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026822 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026822 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248106 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248106 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248106 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248106 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26149.480883 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26149.480883 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46533.837584 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46533.837584 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15124.979875 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15124.979875 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7551.416014 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7551.416014 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36884.350220 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36884.350220 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3791444 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2983 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 159835 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.720987 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 34.287356 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 568073 # number of writebacks -system.cpu0.dcache.writebacks::total 568073 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 499697 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 499697 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1402831 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1402831 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1902528 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1902528 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1902528 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1902528 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 822474 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 822474 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 241450 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 241450 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12284 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12284 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1063924 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1063924 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1063924 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1063924 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24909734008 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24909734008 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10782476086 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10782476086 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 145144507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145144507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3254941 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3254941 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35692210094 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35692210094 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35692210094 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35692210094 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 992378000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 992378000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1672126998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1672126998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2664504998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2664504998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117705 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117705 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075031 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075031 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004479 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004479 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090286 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090286 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4249.270235 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4249.270235 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 710527 # number of writebacks +system.cpu0.dcache.writebacks::total 710527 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 518299 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 518299 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1417662 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1417662 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4443 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4443 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1935961 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1935961 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1935961 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1935961 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 980348 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 980348 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249554 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249554 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1229902 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1229902 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1229902 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1229902 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27067717433 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27067717433 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11277928082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11277928082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147839258 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147839258 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26206765 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26206765 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38345645515 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38345645515 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38345645515 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38345645515 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1453124500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1453124500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2199080998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2199080998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3652205498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3652205498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127882 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127882 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026822 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026822 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096387 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096387 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27610.315350 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27610.315350 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45192.335454 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45192.335454 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10099.689712 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10099.689712 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5551.104639 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5551.104639 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1485,35 +1510,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 5770916 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5004196 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 122577 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3556553 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1526133 # Number of BTB hits +system.cpu1.branchPred.lookups 4639832 # Number of BP lookups +system.cpu1.branchPred.condPredicted 4063901 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 82203 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2874870 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1132301 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 42.910453 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 301064 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7748 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 39.386164 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 224009 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7064 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3015540 # DTB read hits -system.cpu1.dtb.read_misses 12269 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 293761 # DTB read accesses -system.cpu1.dtb.write_hits 1836726 # DTB write hits -system.cpu1.dtb.write_misses 2353 # DTB write misses -system.cpu1.dtb.write_acv 39 # DTB write access violations -system.cpu1.dtb.write_accesses 109652 # DTB write accesses -system.cpu1.dtb.data_hits 4852266 # DTB hits -system.cpu1.dtb.data_misses 14622 # DTB misses -system.cpu1.dtb.data_acv 44 # DTB access violations -system.cpu1.dtb.data_accesses 403413 # DTB accesses -system.cpu1.itb.fetch_hits 632341 # ITB hits -system.cpu1.itb.fetch_misses 5352 # ITB misses -system.cpu1.itb.fetch_acv 51 # ITB acv -system.cpu1.itb.fetch_accesses 637693 # ITB accesses +system.cpu1.dtb.read_hits 2413283 # DTB read hits +system.cpu1.dtb.read_misses 10075 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 292262 # DTB read accesses +system.cpu1.dtb.write_hits 1597058 # DTB write hits +system.cpu1.dtb.write_misses 2093 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 110264 # DTB write accesses +system.cpu1.dtb.data_hits 4010341 # DTB hits +system.cpu1.dtb.data_misses 12168 # DTB misses +system.cpu1.dtb.data_acv 43 # DTB access violations +system.cpu1.dtb.data_accesses 402526 # DTB accesses +system.cpu1.itb.fetch_hits 608432 # ITB hits +system.cpu1.itb.fetch_misses 5602 # ITB misses +system.cpu1.itb.fetch_acv 65 # ITB acv +system.cpu1.itb.fetch_accesses 614034 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1526,554 +1551,552 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 26335588 # number of cpu cycles simulated +system.cpu1.numCycles 19085086 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9800268 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 22981944 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5770916 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1827197 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14019681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 419510 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 307 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 208449 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 196331 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2522136 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 89875 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 24458620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.939626 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.331670 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8490084 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17874574 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4639832 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1356310 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9216388 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 327612 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 219924 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 67319 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1967111 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 67009 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 18184335 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.982966 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.394246 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20375648 83.31% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 230665 0.94% 84.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 464859 1.90% 86.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 295118 1.21% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 600413 2.45% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 204861 0.84% 90.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 257669 1.05% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 270860 1.11% 92.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1758527 7.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15065350 82.85% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 205923 1.13% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 307986 1.69% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 226074 1.24% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 391185 2.15% 89.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151633 0.83% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 170482 0.94% 90.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 296956 1.63% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1368746 7.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 24458620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.219130 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.872657 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8213195 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 12716086 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2925937 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 406668 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 196733 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 189397 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 13167 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 19294426 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 40930 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 196733 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8443455 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3954170 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 7253500 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 3074788 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1535972 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 18421784 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 5378 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 385976 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 36959 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 551165 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 12165906 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 21959681 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 21890085 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 63650 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 10221482 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1944424 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 582778 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 59316 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3316426 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3128488 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1940399 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 395849 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 259099 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 16224994 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 722304 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 15758531 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 26415 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2553169 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1203962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 524576 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 24458620 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644294 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.366216 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 18184335 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.243113 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.936573 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6979571 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8518725 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2274233 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 256003 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 155802 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 137194 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8084 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14619784 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 26597 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 155802 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7159934 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 614392 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6924569 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2350603 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 979033 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13886683 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 9133 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 71770 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16856 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 365854 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9047331 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16422939 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16337871 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 78141 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7835755 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1211576 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 562751 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 58900 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2353285 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2494844 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1679253 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 277357 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 156260 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12201401 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 661557 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11978627 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22551 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1735034 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 788886 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 473891 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 18184335 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.658733 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.375592 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 17964380 73.45% 73.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2773024 11.34% 84.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1191873 4.87% 89.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 895755 3.66% 93.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 840464 3.44% 96.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 400907 1.64% 98.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 238226 0.97% 99.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 113179 0.46% 99.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 40812 0.17% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 13164849 72.40% 72.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2231541 12.27% 84.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 929377 5.11% 89.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 639609 3.52% 93.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 582340 3.20% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 317160 1.74% 98.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 211313 1.16% 99.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 78701 0.43% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 29445 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 24458620 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 18184335 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 56470 15.54% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 184321 50.72% 66.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 122598 33.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24291 8.14% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 162499 54.43% 62.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 111756 37.43% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 10371294 65.81% 65.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 24284 0.15% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11773 0.07% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3139820 19.92% 86.00% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1865147 11.84% 97.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 340936 2.16% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7464610 62.32% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 20078 0.17% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 12377 0.10% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2524426 21.07% 83.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1623488 13.55% 97.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 328371 2.74% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 15758531 # Type of FU issued -system.cpu1.iq.rate 0.598374 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 363389 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023060 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 56111313 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 19387392 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 15262127 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 254173 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 119441 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 117263 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 15982004 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 136398 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 157695 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11978627 # Type of FU issued +system.cpu1.iq.rate 0.627643 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 298546 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.024923 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 42145115 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14453685 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11556214 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 317571 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 148430 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 146304 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12102736 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 170919 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 117615 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 453605 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1302 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 6552 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 197079 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 314973 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1097 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4259 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 145447 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5589 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 74646 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 424 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 56672 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 196733 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 3102898 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 407577 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 17959821 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 47400 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3128488 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1940399 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 647154 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 24325 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 312873 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 6552 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 58721 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 143362 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 202083 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 15559963 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3035862 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 198568 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 155802 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 328818 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 249531 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13597003 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 38106 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2494844 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1679253 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 593871 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4649 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 243688 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4259 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 37580 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 120039 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 157619 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11824953 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2433073 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 153674 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1012523 # number of nop insts executed -system.cpu1.iew.exec_refs 4881099 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2446532 # Number of branches executed -system.cpu1.iew.exec_stores 1845237 # Number of stores executed -system.cpu1.iew.exec_rate 0.590834 # Inst execution rate -system.cpu1.iew.wb_sent 15420680 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 15379390 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 7566791 # num instructions producing a value -system.cpu1.iew.wb_consumers 10761562 # num instructions consuming a value +system.cpu1.iew.exec_nop 734045 # number of nop insts executed +system.cpu1.iew.exec_refs 4040076 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1766091 # Number of branches executed +system.cpu1.iew.exec_stores 1607003 # Number of stores executed +system.cpu1.iew.exec_rate 0.619591 # Inst execution rate +system.cpu1.iew.wb_sent 11733612 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11702518 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5498346 # num instructions producing a value +system.cpu1.iew.wb_consumers 7839453 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.583977 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.703131 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.613176 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.701369 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2776166 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 197728 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 185190 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 23976589 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.630910 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.597118 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1874564 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 187666 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 145503 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 17835799 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.653281 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.639800 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 18550941 77.37% 77.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2272481 9.48% 86.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1151381 4.80% 91.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 578443 2.41% 94.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 385291 1.61% 95.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 189866 0.79% 96.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 157998 0.66% 97.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 143488 0.60% 97.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 546700 2.28% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 13664737 76.61% 76.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1906046 10.69% 87.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 699754 3.92% 91.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 424730 2.38% 93.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 316948 1.78% 95.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133544 0.75% 96.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 114109 0.64% 96.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 155571 0.87% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 420360 2.36% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 23976589 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 15127070 # Number of instructions committed -system.cpu1.commit.committedOps 15127070 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 17835799 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 11651787 # Number of instructions committed +system.cpu1.commit.committedOps 11651787 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4418203 # Number of memory references committed -system.cpu1.commit.loads 2674883 # Number of loads committed -system.cpu1.commit.membars 66521 # Number of memory barriers committed -system.cpu1.commit.branches 2263870 # Number of branches committed -system.cpu1.commit.fp_insts 115331 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 13957396 # Number of committed integer instructions. -system.cpu1.commit.function_calls 240978 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 845832 5.59% 5.59% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 9417463 62.26% 67.85% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 23911 0.16% 68.01% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.01% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 11769 0.08% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 2741404 18.12% 86.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1743996 11.53% 97.75% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 340936 2.25% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3713677 # Number of memory references committed +system.cpu1.commit.loads 2179871 # Number of loads committed +system.cpu1.commit.membars 62781 # Number of memory barriers committed +system.cpu1.commit.branches 1664922 # Number of branches committed +system.cpu1.commit.fp_insts 144632 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 10748857 # Number of committed integer instructions. +system.cpu1.commit.function_calls 187454 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 614300 5.27% 5.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6897823 59.20% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 19873 0.17% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 12372 0.11% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2242652 19.25% 84.01% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1534637 13.17% 97.18% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 328371 2.82% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 15127070 # Class of committed instruction -system.cpu1.commit.bw_lim_events 546700 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 11651787 # Class of committed instruction +system.cpu1.commit.bw_lim_events 420360 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 41251186 # The number of ROB reads -system.cpu1.rob.rob_writes 36287802 # The number of ROB writes -system.cpu1.timesIdled 194891 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1876968 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3779240330 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 14284756 # Number of Instructions Simulated -system.cpu1.committedOps 14284756 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.843615 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.843615 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.542413 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.542413 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20099122 # number of integer regfile reads -system.cpu1.int_regfile_writes 11015819 # number of integer regfile writes -system.cpu1.fp_regfile_reads 63024 # number of floating regfile reads -system.cpu1.fp_regfile_writes 62672 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1065455 # number of misc regfile reads -system.cpu1.misc_regfile_writes 283847 # number of misc regfile writes -system.cpu1.icache.tags.replacements 353746 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.553851 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 2153244 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 354258 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.078180 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 47615844250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.553851 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985457 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.985457 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 30855147 # The number of ROB reads +system.cpu1.rob.rob_writes 27397116 # The number of ROB writes +system.cpu1.timesIdled 166983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 900751 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3790431319 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11041005 # Number of Instructions Simulated +system.cpu1.committedOps 11041005 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.728564 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.728564 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.578515 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.578515 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 15169687 # number of integer regfile reads +system.cpu1.int_regfile_writes 8276758 # number of integer regfile writes +system.cpu1.fp_regfile_reads 77475 # number of floating regfile reads +system.cpu1.fp_regfile_writes 77542 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1124646 # number of misc regfile reads +system.cpu1.misc_regfile_writes 280447 # number of misc regfile writes +system.cpu1.icache.tags.replacements 312757 # number of replacements +system.cpu1.icache.tags.tagsinuse 471.042243 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1644085 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 313269 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.248157 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1879134143250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.042243 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920004 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.920004 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2876460 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2876460 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 2153244 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2153244 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2153244 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2153244 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2153244 # number of overall hits -system.cpu1.icache.overall_hits::total 2153244 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 368891 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 368891 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 368891 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 368891 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 368891 # number of overall misses -system.cpu1.icache.overall_misses::total 368891 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5137931940 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5137931940 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5137931940 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5137931940 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5137931940 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5137931940 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2522135 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2522135 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2522135 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2522135 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2522135 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2522135 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146261 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.146261 # 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number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1967111 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1967111 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164213 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.164213 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164213 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.164213 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.164213 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.164213 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.170952 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.170952 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.170952 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13529.170952 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.170952 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.170952 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 24.127273 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 354325 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 354325 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4259071697 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4259071697 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4259071697 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4259071697 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4259071697 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4259071697 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140486 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.140486 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.140486 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9701 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 9701 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 9701 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 9701 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 9701 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 9701 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 313325 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 313325 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 313325 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 313325 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 313325 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 313325 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3639863451 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3639863451 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3639863451 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3639863451 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3639863451 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3639863451 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.159282 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.159282 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.159282 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11616.894442 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360788 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2745761 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2745761 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1686404 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1686404 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54261 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 54261 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 49669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4432165 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4432165 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4432165 # 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average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 560522 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 381 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 27149 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.646138 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 20.052632 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 140166 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.227589 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3241153 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 140473 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.073139 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 39570817000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.227589 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.961382 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.961382 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15302146 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15302146 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1936775 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1936775 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1212075 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1212075 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45668 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 45668 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44613 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 44613 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3148850 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3148850 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3148850 # number of overall hits +system.cpu1.dcache.overall_hits::total 3148850 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 269383 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 269383 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 265424 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 265424 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8139 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8139 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4996 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 4996 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 534807 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 534807 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 534807 # number of overall misses +system.cpu1.dcache.overall_misses::total 534807 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4084517434 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4084517434 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8552113041 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8552113041 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77678496 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77678496 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 36778735 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 36778735 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12636630475 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12636630475 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12636630475 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12636630475 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2206158 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2206158 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1477499 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1477499 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 53807 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 53807 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49609 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 49609 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3683657 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3683657 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3683657 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3683657 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.122105 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.122105 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179644 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.179644 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.151263 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.151263 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100708 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100708 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.145184 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.145184 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.145184 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.145184 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15162.491449 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15162.491449 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32220.571768 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32220.571768 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9543.985256 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9543.985256 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.636309 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.636309 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23628.393935 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23628.393935 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23628.393935 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23628.393935 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 376916 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 344 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 18544 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.325496 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 31.272727 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 273838 # number of writebacks -system.cpu1.dcache.writebacks::total 273838 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229504 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 229504 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 313811 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 313811 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1705 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1705 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 543315 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 543315 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 543315 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 543315 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 295391 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 295391 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65078 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65078 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7192 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7192 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 360469 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 360469 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 360469 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 360469 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3818838154 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3818838154 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2138006676 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2138006676 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81043507 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81043507 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4153902 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4153902 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5956844830 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5956844830 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5956844830 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5956844830 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 490391500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 490391500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 941927000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 941927000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1432318500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1432318500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038590 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038590 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132545 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.132545 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015825 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015825 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.081330 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.081330 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5284.862595 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5284.862595 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 94206 # number of writebacks +system.cpu1.dcache.writebacks::total 94206 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165989 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 165989 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 215339 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 215339 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 381328 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 381328 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 381328 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 381328 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 103394 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 103394 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 50085 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 50085 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7484 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7484 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4996 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 4996 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 153479 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 153479 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 153479 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 153479 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1212902508 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1212902508 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1317911046 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1317911046 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54853004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54853004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26784265 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26784265 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2530813554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2530813554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2530813554 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2530813554 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29140000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29140000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 708818500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 708818500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737958500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737958500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046866 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046866 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033899 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.139090 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.139090 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100708 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100708 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041665 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.041665 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041665 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.041665 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11730.879045 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11730.879045 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26313.487990 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26313.487990 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7329.369856 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7329.369856 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.141914 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.141914 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2082,32 +2105,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4820 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 161850 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55184 39.67% 39.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 39.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.38% 41.15% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.16% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81844 58.84% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139099 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 54289 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54273 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 110633 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865924468000 98.05% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 60967000 0.00% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 531593000 0.03% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8367000 0.00% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36597541500 1.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903122936500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983782 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6701 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 170162 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 59106 40.33% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.42% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.31% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 339 0.23% 41.96% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 85060 58.04% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 146561 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 58406 49.14% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.62% 50.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 339 0.29% 51.15% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 58067 48.85% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 118868 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864755925000 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61031500 0.00% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 543238000 0.03% 97.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 152147500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39554606000 2.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1905066948000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988157 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.663127 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.795354 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682659 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811048 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed @@ -2139,60 +2162,60 @@ system.cpu0.kern.syscall::144 2 0.89% 99.11% # nu system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 105 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2905 1.98% 2.05% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132721 90.43% 92.52% # number of callpals executed -system.cpu0.kern.callpal::rdps 6135 4.18% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rti 4306 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 439 0.28% 0.28% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3223 2.08% 2.37% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 139738 90.30% 92.70% # number of callpals executed +system.cpu0.kern.callpal::rdps 6333 4.09% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.80% # number of callpals executed +system.cpu0.kern.callpal::rti 4427 2.86% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 146768 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6331 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches +system.cpu0.kern.callpal::total 154756 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6973 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1341 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1341 -system.cpu0.kern.mode_good::user 1342 +system.cpu0.kern.mode_good::kernel 1340 +system.cpu0.kern.mode_good::user 1341 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.211815 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.192170 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.349668 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901148119000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1974809500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.322468 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1903068198000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1998742000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2906 # number of times the context was actually changed +system.cpu0.kern.swap_context 3224 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3853 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 75635 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26441 39.26% 39.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 2.85% 42.12% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 105 0.16% 42.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 38878 57.73% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 67346 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25959 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 3.57% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.20% 51.98% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25854 48.02% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53840 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1868834322000 98.22% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532397000 0.03% 98.24% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 48831000 0.00% 98.25% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33374320500 1.75% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1902789870500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981771 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2621 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 71304 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23839 38.11% 38.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.08% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 439 0.70% 41.89% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 36346 58.11% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 62548 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 23162 48.01% 48.01% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 3.99% 51.99% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 439 0.91% 52.90% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22723 47.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 48248 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872982420000 98.33% 98.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531501500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 197949500 0.01% 98.37% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31046317000 1.63% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904758188000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.971601 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.665003 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.799454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.625186 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771376 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed @@ -2208,35 +2231,35 @@ system.cpu1.kern.syscall::74 10 9.90% 97.03% # nu system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1334 1.92% 1.95% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 1.95% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 1.96% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62422 89.83% 91.80% # number of callpals executed -system.cpu1.kern.callpal::rdps 2621 3.77% 95.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.57% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.58% # number of callpals executed -system.cpu1.kern.callpal::rti 2896 4.17% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 339 0.52% 0.52% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1674 2.58% 3.11% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.11% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.13% # number of callpals executed +system.cpu1.kern.callpal::swpipl 56749 87.55% 90.68% # number of callpals executed +system.cpu1.kern.callpal::rdps 2425 3.74% 94.42% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.42% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.43% # number of callpals executed +system.cpu1.kern.callpal::rti 3435 5.30% 99.73% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.21% 99.93% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 69486 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1712 # number of protection mode switches +system.cpu1.kern.callpal::total 64819 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1725 # number of protection mode switches system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2056 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 462 +system.cpu1.kern.mode_switch::idle 2719 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 758 system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 67 -system.cpu1.kern.mode_switch_good::kernel 0.269860 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 363 +system.cpu1.kern.mode_switch_good::kernel 0.439420 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.032588 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.221955 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 38841912000 2.04% 2.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 712477500 0.04% 2.08% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862932175500 97.92% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1335 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.133505 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.313288 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6292990000 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 709362000 0.04% 0.37% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1897439269000 99.63% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1675 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |