diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
| commit | 08f7a8bc005507117ffda41f283adecf7e4d24f2 (patch) | |
| tree | d3588f01b572538601360998b89e23607549934c /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | |
| parent | 93a8423dea8f8194d83df85a5b3043f9beaf0a1e (diff) | |
| download | gem5-08f7a8bc005507117ffda41f283adecf7e4d24f2.tar.xz | |
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2802 |
1 files changed, 1401 insertions, 1401 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 8dbc85977..3aeb18f28 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.899762 # Number of seconds simulated -sim_ticks 1899762444000 # Number of ticks simulated -final_tick 1899762444000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.897808 # Number of seconds simulated +sim_ticks 1897807508000 # Number of ticks simulated +final_tick 1897807508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165662 # Simulator instruction rate (inst/s) -host_op_rate 165662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5547317951 # Simulator tick rate (ticks/s) -host_mem_usage 338604 # Number of bytes of host memory used -host_seconds 342.47 # Real time elapsed on the host -sim_insts 56733550 # Number of instructions simulated -sim_ops 56733550 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 853120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24660608 # Number of bytes read from this memory +host_inst_rate 93562 # Simulator instruction rate (inst/s) +host_op_rate 93562 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3130145601 # Simulator tick rate (ticks/s) +host_mem_usage 338704 # Number of bytes of host memory used +host_seconds 606.30 # Real time elapsed on the host +sim_insts 56726638 # Number of instructions simulated +sim_ops 56726638 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 852800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24659584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 536896 # Number of bytes read from this memory -system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 853120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7795456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7795456 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13330 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385322 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 123904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 537024 # Number of bytes read from this memory +system.physmem.bytes_read::total 28824960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 852800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7794816 # Number of bytes written to this memory +system.physmem.bytes_written::total 7794816 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385306 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121804 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121804 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12980890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15173333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 514052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4103385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4103385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4103385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12980890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 282612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19276718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450402 # Total number of read requests seen -system.physmem.writeReqs 121804 # Total number of write requests seen -system.physmem.cpureqs 579957 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28825728 # Total number of bytes read from memory -system.physmem.bytesWritten 7795456 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7795456 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5038 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28521 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28417 # Track reads on a per bank basis +system.physmem.num_reads::cpu1.inst 1936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8391 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121794 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121794 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12993722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1397217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 65288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15188558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 65288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 514649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4107274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4107274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4107274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12993722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1397217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 65288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 282971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19295833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450390 # Total number of read requests seen +system.physmem.writeReqs 121794 # Total number of write requests seen +system.physmem.cpureqs 577229 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28824960 # Total number of bytes read from memory +system.physmem.bytesWritten 7794816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28824960 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7794816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5032 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28516 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28182 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28018 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28421 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28180 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28277 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27882 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27807 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27954 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7961 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 28103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28047 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27949 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7958 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7706 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7580 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7703 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7676 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7587 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7293 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7271 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7481 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7325 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7481 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7700 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7581 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7706 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7677 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7592 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7617 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7480 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7323 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7475 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2713 # Number of times wr buffer was full causing retry -system.physmem.totGap 1899757983000 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry +system.physmem.totGap 1897802972000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450402 # Categorize read packet sizes +system.physmem.readPktSize::6 450390 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121804 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 319830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33225 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121794 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 319842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33247 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1403 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -138,224 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5295 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5295 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5295 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5295 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see -system.physmem.totQLat 7756175500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15561175500 # Sum of mem lat for all requests -system.physmem.totBusLat 2251705000 # Total cycles spent in databus access -system.physmem.totBankLat 5553295000 # Total cycles spent in bank access -system.physmem.avgQLat 17222.89 # Average queueing delay per request -system.physmem.avgBankLat 12331.31 # Average bank access latency per request +system.physmem.wrQLenPdf::23 2130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.totQLat 7744912500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15549496250 # Sum of mem lat for all requests +system.physmem.totBusLat 2251660000 # Total cycles spent in databus access +system.physmem.totBankLat 5552923750 # Total cycles spent in bank access +system.physmem.avgQLat 17198.23 # Average queueing delay per request +system.physmem.avgBankLat 12330.73 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34554.21 # Average memory access latency -system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.10 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34528.96 # Average memory access latency +system.physmem.avgRdBW 15.19 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.19 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.95 # Average write queue length over time -system.physmem.readRowHits 422281 # Number of row buffer hits during reads -system.physmem.writeRowHits 93689 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.90 # Average write queue length over time +system.physmem.readRowHits 422298 # Number of row buffer hits during reads +system.physmem.writeRowHits 93666 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.92 # Row buffer hit rate for writes -system.physmem.avgGap 3320059.53 # Average gap between requests -system.l2c.replacements 343507 # number of replacements -system.l2c.tagsinuse 65280.658491 # Cycle average of tags in use -system.l2c.total_refs 2577629 # Total number of references to valid blocks. -system.l2c.sampled_refs 408521 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.309661 # Average number of references to valid blocks. +system.physmem.writeRowHitRate 76.91 # Row buffer hit rate for writes +system.physmem.avgGap 3316770.43 # Average gap between requests +system.l2c.replacements 343496 # number of replacements +system.l2c.tagsinuse 65280.770120 # Cycle average of tags in use +system.l2c.total_refs 2576734 # Total number of references to valid blocks. +system.l2c.sampled_refs 408507 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.307686 # Average number of references to valid blocks. system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53803.217874 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5298.496684 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5899.097985 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 206.030699 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 73.815249 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820972 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080849 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.090013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003144 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001126 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996104 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 850473 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 731190 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 225422 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 71980 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1879065 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820673 # number of Writeback hits -system.l2c.Writeback_hits::total 820673 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 273 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 443 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 45 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits +system.l2c.occ_blocks::writebacks 53812.537758 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5294.598219 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5895.682544 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 204.689512 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 73.262087 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.821114 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.080789 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.089961 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003123 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001118 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996106 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 850039 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 731128 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 225279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 71901 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1878347 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820480 # number of Writeback hits +system.l2c.Writeback_hits::total 820480 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 168 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 274 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 442 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 153356 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26453 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179809 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 850473 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 884546 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 225422 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 98433 # number of demand (read+write) hits -system.l2c.demand_hits::total 2058874 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 850473 # number of overall hits -system.l2c.overall_hits::cpu0.data 884546 # number of overall hits -system.l2c.overall_hits::cpu1.inst 225422 # number of overall hits -system.l2c.overall_hits::cpu1.data 98433 # number of overall hits -system.l2c.overall_hits::total 2058874 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13332 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273019 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1945 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 885 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 153309 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26446 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179755 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 850039 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 884437 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 225279 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 98347 # number of demand (read+write) hits +system.l2c.demand_hits::total 2058102 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 850039 # number of overall hits +system.l2c.overall_hits::cpu0.data 884437 # number of overall hits +system.l2c.overall_hits::cpu1.inst 225279 # number of overall hits +system.l2c.overall_hits::cpu1.data 98347 # number of overall hits +system.l2c.overall_hits::total 2058102 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13328 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273010 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1952 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 891 # number of ReadReq misses system.l2c.ReadReq_misses::total 289181 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2705 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1140 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3845 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2698 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1139 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3837 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 440 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 460 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 900 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 112844 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7619 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120463 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13332 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 385863 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1945 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8504 # number of demand (read+write) misses -system.l2c.demand_misses::total 409644 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13332 # number of overall misses -system.l2c.overall_misses::cpu0.data 385863 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1945 # number of overall misses -system.l2c.overall_misses::cpu1.data 8504 # number of overall misses -system.l2c.overall_misses::total 409644 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 919052500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11905171000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 147649500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 64290999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 13036163999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1055000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5020958 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 6075958 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_misses::cpu0.data 112836 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7617 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120453 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13328 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 385846 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1952 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8508 # number of demand (read+write) misses +system.l2c.demand_misses::total 409634 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13328 # number of overall misses +system.l2c.overall_misses::cpu0.data 385846 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1952 # number of overall misses +system.l2c.overall_misses::cpu1.data 8508 # number of overall misses +system.l2c.overall_misses::total 409634 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 910367500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11910960000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 149515000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 66485999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 13037328499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1032000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 4998458 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 6030458 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1306998 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7474090498 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 738521500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8212611998 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 919052500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19379261498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 147649500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 802812499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21248775997 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 919052500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19379261498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 147649500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 802812499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21248775997 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 863805 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1004209 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 227367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 72865 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2168246 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820673 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820673 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2875 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 158500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1306498 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7467468497 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 736712000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8204180497 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 910367500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 19378428497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 149515000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 803197999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21241508996 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 910367500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 19378428497 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 149515000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 803197999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21241508996 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 863367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1004138 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 227231 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 72792 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2167528 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 820480 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 820480 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2866 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4288 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 485 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 483 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4279 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 484 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 484 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 968 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 266200 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 34072 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300272 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 863805 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1270409 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 227367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 106937 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2468518 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 863805 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1270409 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 227367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 106937 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2468518 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015434 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.271875 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008554 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.012146 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133371 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940870 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806794 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.896688 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.907216 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.952381 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 266145 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 34063 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300208 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 863367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1270283 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 227231 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 106855 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2467736 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 863367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1270283 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 227231 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 106855 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2467736 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015437 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.271885 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008590 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.012240 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.133415 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941382 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806086 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.896705 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.909091 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.950413 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.929752 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.423907 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.423964 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.223615 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.401180 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015434 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.303731 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008554 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.079523 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165947 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015434 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.303731 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008554 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.079523 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165947 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68935.831083 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 43605.650156 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75912.339332 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 72645.196610 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 45079.600662 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 390.018484 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4404.349123 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1580.223147 # average UpgradeReq miss latency +system.l2c.ReadExReq_miss_rate::total 0.401232 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015437 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.303748 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008590 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.079622 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.165996 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015437 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.303748 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008590 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.079622 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.165996 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68304.884454 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 43628.292004 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76595.799180 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74619.527497 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 45083.627552 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 382.505560 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4388.461809 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1571.659630 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2609.086364 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 345.652174 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1452.220000 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66233.831644 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96931.552697 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 68175.389937 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 68935.831083 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50223.165989 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75912.339332 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 94404.103833 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51871.322409 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 68935.831083 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50223.165989 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75912.339332 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 94404.103833 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51871.322409 # average overall miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 344.565217 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1451.664444 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66179.840627 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96719.443350 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 68111.051589 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 68304.884454 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50223.219878 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76595.799180 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 94405.030442 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51854.848465 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 68304.884454 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50223.219878 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76595.799180 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 94405.030442 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51854.848465 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,8 +364,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80284 # number of writebacks -system.l2c.writebacks::total 80284 # number of writebacks +system.l2c.writebacks::writebacks 80274 # number of writebacks +system.l2c.writebacks::total 80274 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits @@ -378,111 +378,111 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13331 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273019 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1929 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 884 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 13327 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273010 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1936 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 890 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 289163 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2705 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1140 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3845 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2698 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1139 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3837 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 440 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 460 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 900 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 112844 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7619 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 120463 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13331 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 385863 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1929 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8503 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 409626 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13331 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 385863 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1929 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8503 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 409626 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 752774551 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8562507308 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122885880 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 53311432 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 9491479171 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27258667 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11426097 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 38684764 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::cpu0.data 112836 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7617 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 120453 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13327 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 385846 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1936 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8507 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 409616 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13327 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 385846 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1936 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8507 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 409616 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 744135298 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8568292303 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124663136 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 55431194 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 9492521931 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27188160 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11417094 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 38605254 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4415934 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4604459 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 9020393 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6098954840 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 645340483 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6744295323 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 752774551 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 14661462148 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 122885880 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 698651915 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16235774494 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 752774551 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 14661462148 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 122885880 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 698651915 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16235774494 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363373000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28764500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1392137500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2009193000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 611400000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2620593000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3372566000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 640164500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4012730500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271875 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012132 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.133363 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940870 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806794 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.896688 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.907216 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952381 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6092451578 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 643571973 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6736023551 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 744135298 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 14660743881 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 124663136 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 699003167 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16228545482 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 744135298 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 14660743881 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 124663136 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 699003167 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16228545482 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1360923000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28763500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389686500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2006926500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 610979500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2617906000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3367849500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 639743000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4007592500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015436 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271885 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008520 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012227 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133407 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941382 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806086 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.896705 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909091 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.950413 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.929752 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.423907 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.423964 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.223615 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.401180 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.303731 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.079514 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165940 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.303731 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.079514 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165940 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31362.312909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60307.049774 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 32823.975305 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10077.141220 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892105 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.056957 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::total 0.401232 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015436 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.303748 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008520 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.079613 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165989 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015436 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.303748 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008520 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.079613 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165989 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31384.536475 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62282.240449 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 32827.581437 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10077.153447 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.787533 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.311962 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10036.213636 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.693478 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.658889 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54047.666159 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84701.467778 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 55986.446652 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37996.548381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82165.343408 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39635.605391 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37996.548381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82165.343408 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39635.605391 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53993.863466 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84491.528555 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 55922.422447 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37996.360934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82167.998942 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39618.924754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37996.360934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82167.998942 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39618.924754 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -494,14 +494,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.501565 # Cycle average of tags in use +system.iocache.tagsinuse 0.485600 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1705456155000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.501565 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.031348 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.031348 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 0.485600 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030350 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030350 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -512,12 +512,12 @@ system.iocache.overall_misses::tsunami.ide 41729 # system.iocache.overall_misses::total 41729 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21380998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21380998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10589255806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10589255806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10610636804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10610636804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10610636804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10610636804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10586785423 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10586785423 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10608166421 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10608166421 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10608166421 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10608166421 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -536,17 +536,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120796.598870 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254843.468570 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 254843.468570 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 254274.888063 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 254274.888063 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 281737 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254784.015763 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 254784.015763 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 254215.687436 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 254215.687436 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 254215.687436 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 254215.687436 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 281558 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 26988 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 26875 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.439343 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.476577 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -562,12 +562,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41729 system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12176249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8427244570 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8427244570 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8439420819 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8439420819 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8439420819 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8439420819 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8424787682 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8424787682 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8436963931 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8436963931 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8436963931 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8436963931 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -578,12 +578,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202812.008327 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 202812.008327 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202752.880295 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 202752.880295 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202184.666084 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 202184.666084 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202184.666084 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 202184.666084 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -597,35 +597,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12335027 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10393813 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 330568 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7867422 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5239774 # Number of BTB hits +system.cpu0.branchPred.lookups 12324830 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10383801 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 330699 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7879276 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5243296 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.600902 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 784891 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32664 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.545403 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 784421 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32635 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8753494 # DTB read hits -system.cpu0.dtb.read_misses 29787 # DTB read misses -system.cpu0.dtb.read_acv 536 # DTB read access violations -system.cpu0.dtb.read_accesses 623801 # DTB read accesses -system.cpu0.dtb.write_hits 5745053 # DTB write hits -system.cpu0.dtb.write_misses 8131 # DTB write misses -system.cpu0.dtb.write_acv 346 # DTB write access violations -system.cpu0.dtb.write_accesses 207769 # DTB write accesses -system.cpu0.dtb.data_hits 14498547 # DTB hits -system.cpu0.dtb.data_misses 37918 # DTB misses -system.cpu0.dtb.data_acv 882 # DTB access violations -system.cpu0.dtb.data_accesses 831570 # DTB accesses -system.cpu0.itb.fetch_hits 986254 # ITB hits -system.cpu0.itb.fetch_misses 27996 # ITB misses -system.cpu0.itb.fetch_acv 985 # ITB acv -system.cpu0.itb.fetch_accesses 1014250 # ITB accesses +system.cpu0.dtb.read_hits 8754095 # DTB read hits +system.cpu0.dtb.read_misses 29935 # DTB read misses +system.cpu0.dtb.read_acv 546 # DTB read access violations +system.cpu0.dtb.read_accesses 624217 # DTB read accesses +system.cpu0.dtb.write_hits 5744304 # DTB write hits +system.cpu0.dtb.write_misses 8066 # DTB write misses +system.cpu0.dtb.write_acv 350 # DTB write access violations +system.cpu0.dtb.write_accesses 207709 # DTB write accesses +system.cpu0.dtb.data_hits 14498399 # DTB hits +system.cpu0.dtb.data_misses 38001 # DTB misses +system.cpu0.dtb.data_acv 896 # DTB access violations +system.cpu0.dtb.data_accesses 831926 # DTB accesses +system.cpu0.itb.fetch_hits 984231 # ITB hits +system.cpu0.itb.fetch_misses 30400 # ITB misses +system.cpu0.itb.fetch_acv 951 # ITB acv +system.cpu0.itb.fetch_accesses 1014631 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,134 +638,134 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 101860002 # number of cpu cycles simulated +system.cpu0.numCycles 101829868 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24837828 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63180848 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12335027 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6024665 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11886569 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1686741 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36619319 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 32566 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195803 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 292498 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7637223 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223881 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 74953254 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.842937 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.180655 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24831231 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63164825 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12324830 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6027717 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11886034 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1687418 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36616651 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 32610 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 197530 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 292271 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 247 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7635312 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223745 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74945500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.842810 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.180311 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63066685 84.14% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 761791 1.02% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1555671 2.08% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 698950 0.93% 88.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2562608 3.42% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 513718 0.69% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 568258 0.76% 93.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 822289 1.10% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4403284 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63059466 84.14% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 761662 1.02% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1556791 2.08% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 699013 0.93% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2562383 3.42% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 515928 0.69% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568129 0.76% 93.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 822428 1.10% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4399700 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74953254 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121098 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.620271 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26053984 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36115594 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10809914 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 920077 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1053684 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 507198 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35097 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62027396 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105101 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1053684 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27061357 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14627985 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18001405 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10130422 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4078399 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58721682 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6643 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 642092 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1424191 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39329555 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71492090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71110334 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 381756 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34559979 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4769568 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1435328 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 208629 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11112444 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9161053 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6009456 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1123532 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 742915 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52110985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1787265 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 50968553 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87650 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5843461 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2979197 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1210641 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 74953254 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.680005 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329199 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74945500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.121034 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.620298 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26048767 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36112585 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10811010 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 918999 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1054138 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507624 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35116 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62016567 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105227 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1054138 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27056479 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14636567 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17989986 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10129953 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4078375 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58716570 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6669 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 641571 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1425002 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39326634 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71486416 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71104766 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 381650 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34557314 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4769312 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1434958 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 208601 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11111126 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9162338 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6008284 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124943 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 741369 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52108127 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1785217 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50965376 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88359 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5842472 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2979590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1208696 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74945500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680033 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329236 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52302643 69.78% 69.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10307098 13.75% 83.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4640048 6.19% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3056236 4.08% 93.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2433864 3.25% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1212107 1.62% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 643283 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 306838 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51137 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52296103 69.78% 69.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10307056 13.75% 83.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4639666 6.19% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3056082 4.08% 93.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2432821 3.25% 97.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1212271 1.62% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 643524 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 306857 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 51120 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74953254 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74945500 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 83602 12.51% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 310944 46.54% 59.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 273567 40.95% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83315 12.44% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 310574 46.36% 58.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 276009 41.20% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35163137 68.99% 69.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56167 0.11% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35160159 68.99% 69.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56163 0.11% 69.11% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued @@ -793,114 +793,114 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9108259 17.87% 87.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5813234 11.41% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 806455 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9109271 17.87% 87.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5812211 11.40% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 806271 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 50968553 # Type of FU issued -system.cpu0.iq.rate 0.500378 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 668113 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013108 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 177097926 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59488760 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 49954313 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 548196 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 265355 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 258816 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51345953 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 286939 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 543981 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50965376 # Type of FU issued +system.cpu0.iq.rate 0.500495 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 669898 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 177086282 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59482873 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 49950097 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 548226 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 265331 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 258806 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51344519 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 286981 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 543841 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1095536 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3484 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12649 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 447527 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1097645 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3519 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12633 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 446832 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18428 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 123543 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18414 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 123451 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1053684 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10434033 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 794004 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57098821 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 607587 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9161053 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6009456 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1574353 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 581874 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5211 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12649 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164505 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 346352 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 510857 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50581166 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8806339 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 387386 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1054138 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10442164 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 794127 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57094083 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 608812 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9162338 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6008284 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1572405 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 581948 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5528 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12633 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164589 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 346313 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 510902 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50577895 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8807105 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387480 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3200571 # number of nop insts executed -system.cpu0.iew.exec_refs 14573024 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8058196 # Number of branches executed -system.cpu0.iew.exec_stores 5766685 # Number of stores executed -system.cpu0.iew.exec_rate 0.496575 # Inst execution rate -system.cpu0.iew.wb_sent 50300704 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50213129 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25063994 # num instructions producing a value -system.cpu0.iew.wb_consumers 33773959 # num instructions consuming a value +system.cpu0.iew.exec_nop 3200739 # number of nop insts executed +system.cpu0.iew.exec_refs 14572965 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8058105 # Number of branches executed +system.cpu0.iew.exec_stores 5765860 # Number of stores executed +system.cpu0.iew.exec_rate 0.496690 # Inst execution rate +system.cpu0.iew.wb_sent 50296670 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50208903 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25061095 # num instructions producing a value +system.cpu0.iew.wb_consumers 33769433 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.492962 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742110 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.493067 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742124 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6307351 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 576624 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 477479 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 73899570 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685982 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.603952 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6306622 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 576521 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 477545 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73891362 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.686006 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.603918 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 54870784 74.25% 74.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7931577 10.73% 84.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4331737 5.86% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2351789 3.18% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1313178 1.78% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 548800 0.74% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466874 0.63% 97.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 433224 0.59% 97.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1651607 2.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54863146 74.25% 74.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7931478 10.73% 84.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4331360 5.86% 90.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2351860 3.18% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1314304 1.78% 95.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 548181 0.74% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466916 0.63% 97.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 432440 0.59% 97.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1651677 2.24% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 73899570 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50693798 # Number of instructions committed -system.cpu0.commit.committedOps 50693798 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73891362 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50689891 # Number of instructions committed +system.cpu0.commit.committedOps 50689891 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13627446 # Number of memory references committed -system.cpu0.commit.loads 8065517 # Number of loads committed -system.cpu0.commit.membars 196376 # Number of memory barriers committed -system.cpu0.commit.branches 7658577 # Number of branches committed +system.cpu0.commit.refs 13626145 # Number of memory references committed +system.cpu0.commit.loads 8064693 # Number of loads committed +system.cpu0.commit.membars 196335 # Number of memory barriers committed +system.cpu0.commit.branches 7657959 # Number of branches committed system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46944411 # Number of committed integer instructions. -system.cpu0.commit.function_calls 646517 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1651607 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 46940801 # Number of committed integer instructions. +system.cpu0.commit.function_calls 646411 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1651677 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129054613 # The number of ROB reads -system.cpu0.rob.rob_writes 115056832 # The number of ROB writes -system.cpu0.timesIdled 1051988 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26906748 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3697658339 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47774945 # Number of Instructions Simulated -system.cpu0.committedOps 47774945 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47774945 # Number of Instructions Simulated -system.cpu0.cpi 2.132080 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.132080 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.469026 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.469026 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66569976 # number of integer regfile reads -system.cpu0.int_regfile_writes 36353057 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127037 # number of floating regfile reads -system.cpu0.fp_regfile_writes 128676 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1691103 # number of misc regfile reads -system.cpu0.misc_regfile_writes 806046 # number of misc regfile writes +system.cpu0.rob.rob_reads 129041756 # The number of ROB reads +system.cpu0.rob.rob_writes 115048006 # The number of ROB writes +system.cpu0.timesIdled 1051806 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26884368 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693778600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47771172 # Number of Instructions Simulated +system.cpu0.committedOps 47771172 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47771172 # Number of Instructions Simulated +system.cpu0.cpi 2.131618 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.131618 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.469127 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.469127 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66565111 # number of integer regfile reads +system.cpu0.int_regfile_writes 36349916 # number of integer regfile writes +system.cpu0.fp_regfile_reads 127030 # number of floating regfile reads +system.cpu0.fp_regfile_writes 128672 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1690077 # number of misc regfile reads +system.cpu0.misc_regfile_writes 805917 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,245 +932,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 863258 # number of replacements -system.cpu0.icache.tagsinuse 510.308888 # Cycle average of tags in use -system.cpu0.icache.total_refs 6729374 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 863770 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.790701 # Average number of references to valid blocks. +system.cpu0.icache.replacements 862820 # number of replacements +system.cpu0.icache.tagsinuse 510.307143 # Cycle average of tags in use +system.cpu0.icache.total_refs 6727960 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 863332 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.793016 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.308888 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996697 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996697 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6729374 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6729374 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6729374 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6729374 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6729374 # number of overall hits -system.cpu0.icache.overall_hits::total 6729374 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 907848 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 907848 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 907848 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 907848 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 907848 # number of overall misses -system.cpu0.icache.overall_misses::total 907848 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12809117491 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12809117491 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12809117491 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12809117491 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12809117491 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12809117491 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7637222 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7637222 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7637222 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7637222 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7637222 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7637222 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118871 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118871 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118871 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118871 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118871 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118871 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14109.319502 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14109.319502 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14109.319502 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14109.319502 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5737 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 510.307143 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996694 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996694 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6727960 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6727960 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6727960 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6727960 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6727960 # number of overall hits +system.cpu0.icache.overall_hits::total 6727960 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 907351 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 907351 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 907351 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 907351 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 907351 # number of overall misses +system.cpu0.icache.overall_misses::total 907351 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12784635489 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12784635489 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12784635489 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12784635489 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12784635489 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12784635489 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7635311 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7635311 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7635311 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7635311 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7635311 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7635311 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118836 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118836 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118836 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118836 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118836 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118836 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14090.066015 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14090.066015 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14090.066015 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14090.066015 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5023 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 178 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 35.633540 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.219101 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43927 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43927 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43927 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43927 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43927 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43927 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863921 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 863921 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 863921 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 863921 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 863921 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 863921 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10545414492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10545414492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10545414492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10545414492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10545414492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10545414492 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113120 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113120 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113120 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12206.456947 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43874 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43874 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43874 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43874 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43874 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43874 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863477 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 863477 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 863477 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 863477 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 863477 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 863477 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10532261990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10532261990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10532261990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10532261990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10532261990 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10532261990 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113090 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113090 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113090 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12197.501485 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12197.501485 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12197.501485 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1272639 # number of replacements -system.cpu0.dcache.tagsinuse 505.727163 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10328741 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1273151 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.112738 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1272509 # number of replacements +system.cpu0.dcache.tagsinuse 505.757504 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10329025 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1273021 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.113790 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.727163 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987748 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987748 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6350419 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6350419 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3622179 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3622179 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160143 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160143 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184450 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 184450 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9972598 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9972598 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9972598 # number of overall hits -system.cpu0.dcache.overall_hits::total 9972598 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1584754 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1584754 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1737731 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1737731 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20393 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20393 # number of LoadLockedReq misses +system.cpu0.dcache.occ_blocks::cpu0.data 505.757504 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987808 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987808 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6350853 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6350853 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3621976 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3621976 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160250 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 160250 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184435 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 184435 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9972829 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9972829 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9972829 # number of overall hits +system.cpu0.dcache.overall_hits::total 9972829 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1585015 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1585015 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1737486 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1737486 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2991 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2991 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3322485 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3322485 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3322485 # number of overall misses -system.cpu0.dcache.overall_misses::total 3322485 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34254700500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34254700500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66543857651 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 66543857651 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293744000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 293744000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21938000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 21938000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 100798558151 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 100798558151 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 100798558151 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 100798558151 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935173 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7935173 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359910 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5359910 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180536 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 180536 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187441 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187441 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13295083 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13295083 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13295083 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13295083 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199713 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199713 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324209 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324209 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112958 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112958 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015957 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015957 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249903 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249903 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249903 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249903 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21615.153204 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21615.153204 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.531997 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.531997 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14404.158290 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14404.158290 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7334.670679 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7334.670679 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30338.303454 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30338.303454 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2157066 # number of cycles access was blocked +system.cpu0.dcache.demand_misses::cpu0.data 3322501 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3322501 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3322501 # number of overall misses +system.cpu0.dcache.overall_misses::total 3322501 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34267378500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34267378500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66512674680 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 66512674680 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293615500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 293615500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21928500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 21928500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 100780053180 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 100780053180 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 100780053180 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 100780053180 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7935868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359462 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5359462 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180668 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 180668 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187426 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187426 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13295330 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13295330 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13295330 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13295330 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199728 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199728 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324190 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324190 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113014 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113014 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015958 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015958 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249900 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249900 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249900 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249900 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21619.592559 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21619.592559 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38280.984526 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38280.984526 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14380.228230 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14380.228230 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7331.494483 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7331.494483 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30332.587764 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30332.587764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30332.587764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30332.587764 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2151725 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 2274 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48232 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48206 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.722715 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.636041 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 324.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 748565 # number of writebacks -system.cpu0.dcache.writebacks::total 748565 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585493 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 585493 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465453 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1465453 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4489 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4489 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2050946 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2050946 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2050946 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2050946 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999261 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 999261 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272278 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272278 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15904 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 748436 # number of writebacks +system.cpu0.dcache.writebacks::total 748436 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585810 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 585810 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465270 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1465270 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4533 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4533 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2051080 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2051080 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2051080 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2051080 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999205 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 999205 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272216 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272216 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15885 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15885 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2991 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2991 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271539 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1271539 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271539 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1271539 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21490960000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21490960000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698199220 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9698199220 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183494500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183494500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15956000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15956000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31189159220 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31189159220 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31189159220 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31189159220 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454907000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454907000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2130479499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2130479499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3585386499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3585386499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125928 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125928 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050799 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050799 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088093 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088093 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015957 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095640 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095640 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21506.853565 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21506.853565 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35618.739744 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35618.739744 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.632042 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.632042 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5334.670679 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5334.670679 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271421 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1271421 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271421 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1271421 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21496696000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21496696000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9690926222 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9690926222 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183269000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183269000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31187622222 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31187622222 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31187622222 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31187622222 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1452303000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1452303000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128092999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128092999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3580395999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3580395999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125910 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125910 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050792 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050792 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087924 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087924 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015958 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015958 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095629 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095629 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095629 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095629 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21513.799471 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21513.799471 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35600.134533 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35600.134533 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.236387 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.236387 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5331.494483 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5331.494483 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24529.736588 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24529.736588 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24529.736588 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24529.736588 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1178,35 +1178,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2650086 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2188228 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 78181 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1530727 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 883629 # Number of BTB hits +system.cpu1.branchPred.lookups 2647984 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2186587 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 77884 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1531761 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 883024 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.726100 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 184091 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8336 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.647636 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 183996 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8305 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1963408 # DTB read hits -system.cpu1.dtb.read_misses 10761 # DTB read misses -system.cpu1.dtb.read_acv 27 # DTB read access violations -system.cpu1.dtb.read_accesses 325022 # DTB read accesses -system.cpu1.dtb.write_hits 1266270 # DTB write hits -system.cpu1.dtb.write_misses 2185 # DTB write misses +system.cpu1.dtb.read_hits 1962214 # DTB read hits +system.cpu1.dtb.read_misses 10693 # DTB read misses +system.cpu1.dtb.read_acv 25 # DTB read access violations +system.cpu1.dtb.read_accesses 324562 # DTB read accesses +system.cpu1.dtb.write_hits 1265832 # DTB write hits +system.cpu1.dtb.write_misses 2093 # DTB write misses system.cpu1.dtb.write_acv 66 # DTB write access violations -system.cpu1.dtb.write_accesses 133146 # DTB write accesses -system.cpu1.dtb.data_hits 3229678 # DTB hits -system.cpu1.dtb.data_misses 12946 # DTB misses -system.cpu1.dtb.data_acv 93 # DTB access violations -system.cpu1.dtb.data_accesses 458168 # DTB accesses -system.cpu1.itb.fetch_hits 437746 # ITB hits -system.cpu1.itb.fetch_misses 6892 # ITB misses -system.cpu1.itb.fetch_acv 236 # ITB acv -system.cpu1.itb.fetch_accesses 444638 # ITB accesses +system.cpu1.dtb.write_accesses 133005 # DTB write accesses +system.cpu1.dtb.data_hits 3228046 # DTB hits +system.cpu1.dtb.data_misses 12786 # DTB misses +system.cpu1.dtb.data_acv 91 # DTB access violations +system.cpu1.dtb.data_accesses 457567 # DTB accesses +system.cpu1.itb.fetch_hits 437198 # ITB hits +system.cpu1.itb.fetch_misses 6975 # ITB misses +system.cpu1.itb.fetch_acv 228 # ITB acv +system.cpu1.itb.fetch_accesses 444173 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1219,134 +1219,134 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16144974 # number of cpu cycles simulated +system.cpu1.numCycles 16140506 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6121442 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12493756 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2650086 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1067720 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2240899 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 409596 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6344466 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65860 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 57508 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1513677 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 52961 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15118787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.826373 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.200485 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6118318 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12482084 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2647984 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1067020 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2239129 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 408271 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6344159 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65784 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 57491 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1512128 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 52849 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15112669 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.825935 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199937 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12877888 85.18% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 143885 0.95% 86.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 241695 1.60% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 180531 1.19% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 309762 2.05% 90.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 120449 0.80% 91.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 135595 0.90% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 201831 1.33% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 907151 6.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12873540 85.18% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 143819 0.95% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 241770 1.60% 87.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 180451 1.19% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 309857 2.05% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 119919 0.79% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 135082 0.89% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 201991 1.34% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 906240 6.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15118787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164143 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.773848 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6052870 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6602402 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2094481 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 114057 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 254976 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 116126 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7500 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12249807 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22555 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 254976 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6262682 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 497209 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5456490 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1996397 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 651031 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11355545 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 56660 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 160008 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7474719 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13559101 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13415671 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 143430 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6386740 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1087979 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 456269 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 43986 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2005882 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2076975 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1341554 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 190968 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 103806 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9970569 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 502731 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9700952 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 30075 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1449475 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 723922 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 361264 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15118787 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.641649 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.316312 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15112669 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164058 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.773339 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6050197 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6601549 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2093593 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 113312 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 254017 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 116024 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7481 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12238533 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22436 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 254017 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6259861 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 497059 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5456265 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1994881 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 650584 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11345893 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 56627 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 159750 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7468114 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13547421 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13404114 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 143307 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6384399 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1083715 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 455985 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 44016 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2004753 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2075172 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1340696 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 190596 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 106471 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9962736 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 502412 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9694977 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 29943 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1444595 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 720781 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 360981 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15112669 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.641513 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.316207 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10852712 71.78% 71.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1956314 12.94% 84.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 839077 5.55% 90.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 560111 3.70% 93.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 472963 3.13% 97.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 218451 1.44% 98.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 140254 0.93% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 70720 0.47% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8185 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10849099 71.79% 71.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1954888 12.94% 84.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 839816 5.56% 90.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 558366 3.69% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 473326 3.13% 97.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 218082 1.44% 98.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 140204 0.93% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 70683 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8205 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15118787 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15112669 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3675 1.85% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 107078 53.97% 55.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 87636 44.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3691 1.86% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 106885 53.95% 55.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 87531 44.18% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6050828 62.37% 62.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16408 0.17% 62.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6046898 62.37% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16423 0.17% 62.58% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued @@ -1374,353 +1374,353 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2054303 21.18% 83.89% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1289929 13.30% 97.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 273346 2.82% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2053041 21.18% 83.88% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1289229 13.30% 97.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 273248 2.82% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9700952 # Type of FU issued -system.cpu1.iq.rate 0.600865 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 198389 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020450 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 34541883 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11823308 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9430294 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 207272 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 101213 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 98067 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9787736 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 108079 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94689 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9694977 # Type of FU issued +system.cpu1.iq.rate 0.600661 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 198107 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020434 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 34523477 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11810363 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9424990 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 207196 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 101110 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 98065 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9781516 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 108042 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94596 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 288018 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 887 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1813 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 126704 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 286791 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 870 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1822 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 126158 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 10289 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.cacheBlocked 10101 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 254976 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 327284 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 41516 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10988492 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 148711 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2076975 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1341554 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 455253 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 34417 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1886 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1813 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 35814 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 100493 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 136307 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9610649 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1981550 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 90303 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 254017 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 327186 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 41525 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10980256 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 148232 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2075172 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1340696 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 454941 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 34335 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2140 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1822 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 35734 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 100242 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 135976 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9604840 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1980291 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 90137 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 515192 # number of nop insts executed -system.cpu1.iew.exec_refs 3256018 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1435370 # Number of branches executed -system.cpu1.iew.exec_stores 1274468 # Number of stores executed -system.cpu1.iew.exec_rate 0.595272 # Inst execution rate -system.cpu1.iew.wb_sent 9557675 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9528361 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4461159 # num instructions producing a value -system.cpu1.iew.wb_consumers 6259469 # num instructions consuming a value +system.cpu1.iew.exec_nop 515108 # number of nop insts executed +system.cpu1.iew.exec_refs 3254225 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1434575 # Number of branches executed +system.cpu1.iew.exec_stores 1273934 # Number of stores executed +system.cpu1.iew.exec_rate 0.595077 # Inst execution rate +system.cpu1.iew.wb_sent 9552134 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9523055 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4457844 # num instructions producing a value +system.cpu1.iew.wb_consumers 6254214 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.590175 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712706 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.590010 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712774 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1504147 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 141467 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 128937 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14863811 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.633307 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.576989 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1499365 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 141431 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 128632 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14858652 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633306 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.577285 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11340708 76.30% 76.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1645490 11.07% 87.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 614395 4.13% 91.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 372484 2.51% 94.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 264045 1.78% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 106401 0.72% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 110365 0.74% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 108140 0.73% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 301783 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11337498 76.30% 76.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1644581 11.07% 87.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 614314 4.13% 91.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 371520 2.50% 94.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 264064 1.78% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 106187 0.71% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 110282 0.74% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 108223 0.73% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 301983 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14863811 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9413351 # Number of instructions committed -system.cpu1.commit.committedOps 9413351 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14858652 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9410077 # Number of instructions committed +system.cpu1.commit.committedOps 9410077 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3003807 # Number of memory references committed -system.cpu1.commit.loads 1788957 # Number of loads committed -system.cpu1.commit.membars 45075 # Number of memory barriers committed -system.cpu1.commit.branches 1347256 # Number of branches committed +system.cpu1.commit.refs 3002919 # Number of memory references committed +system.cpu1.commit.loads 1788381 # Number of loads committed +system.cpu1.commit.membars 45067 # Number of memory barriers committed +system.cpu1.commit.branches 1346773 # Number of branches committed system.cpu1.commit.fp_insts 96765 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8723626 # Number of committed integer instructions. -system.cpu1.commit.function_calls 150668 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 301783 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 8720568 # Number of committed integer instructions. +system.cpu1.commit.function_calls 150616 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 301983 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25388124 # The number of ROB reads -system.cpu1.rob.rob_writes 22088528 # The number of ROB writes -system.cpu1.timesIdled 132804 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1026187 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3782762516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8958605 # Number of Instructions Simulated -system.cpu1.committedOps 8958605 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8958605 # Number of Instructions Simulated -system.cpu1.cpi 1.802175 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.802175 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.554885 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.554885 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12390777 # number of integer regfile reads -system.cpu1.int_regfile_writes 6781957 # number of integer regfile writes -system.cpu1.fp_regfile_reads 53541 # number of floating regfile reads -system.cpu1.fp_regfile_writes 53239 # number of floating regfile writes -system.cpu1.misc_regfile_reads 527070 # number of misc regfile reads -system.cpu1.misc_regfile_writes 221606 # number of misc regfile writes -system.cpu1.icache.replacements 226821 # number of replacements -system.cpu1.icache.tagsinuse 470.843395 # Cycle average of tags in use -system.cpu1.icache.total_refs 1277714 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 227333 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.620451 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 25374737 # The number of ROB reads +system.cpu1.rob.rob_writes 22071443 # The number of ROB writes +system.cpu1.timesIdled 132837 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1027837 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3778857265 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8955466 # Number of Instructions Simulated +system.cpu1.committedOps 8955466 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8955466 # Number of Instructions Simulated +system.cpu1.cpi 1.802308 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.802308 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554844 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554844 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12383422 # number of integer regfile reads +system.cpu1.int_regfile_writes 6777735 # number of integer regfile writes +system.cpu1.fp_regfile_reads 53544 # number of floating regfile reads +system.cpu1.fp_regfile_writes 53234 # number of floating regfile writes +system.cpu1.misc_regfile_reads 526951 # number of misc regfile reads +system.cpu1.misc_regfile_writes 221547 # number of misc regfile writes +system.cpu1.icache.replacements 226688 # number of replacements +system.cpu1.icache.tagsinuse 470.806939 # Cycle average of tags in use +system.cpu1.icache.total_refs 1276285 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 227200 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.617452 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 1874198606000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.843395 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919616 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919616 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1277714 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1277714 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1277714 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1277714 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1277714 # number of overall hits -system.cpu1.icache.overall_hits::total 1277714 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 235963 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 235963 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 235963 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 235963 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 235963 # number of overall misses -system.cpu1.icache.overall_misses::total 235963 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3262757999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3262757999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3262757999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3262757999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3262757999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3262757999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1513677 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1513677 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1513677 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1513677 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1513677 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1513677 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155887 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.155887 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155887 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.155887 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155887 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.155887 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13827.413616 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13827.413616 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13827.413616 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13827.413616 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 255 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 470.806939 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919545 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919545 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1276285 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1276285 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1276285 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1276285 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1276285 # number of overall hits +system.cpu1.icache.overall_hits::total 1276285 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 235843 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 235843 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 235843 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 235843 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 235843 # number of overall misses +system.cpu1.icache.overall_misses::total 235843 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3268518999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3268518999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3268518999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3268518999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3268518999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3268518999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1512128 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1512128 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1512128 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1512128 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1512128 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1512128 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155968 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.155968 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155968 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.155968 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155968 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.155968 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13858.876452 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13858.876452 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13858.876452 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13858.876452 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.153846 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 227395 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 227395 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 227395 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 227395 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 227395 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 227395 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711257499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711257499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711257499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2711257499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711257499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2711257499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150227 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.150227 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.150227 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11923.118358 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8582 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8582 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8582 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8582 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8582 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8582 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 227261 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 227261 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 227261 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 227261 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 227261 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 227261 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711595499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711595499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711595499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2711595499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711595499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2711595499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150292 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.150292 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.150292 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11931.635868 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11931.635868 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11931.635868 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 108831 # number of replacements -system.cpu1.dcache.tagsinuse 491.507176 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2642897 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 109233 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.195042 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 108752 # number of replacements +system.cpu1.dcache.tagsinuse 491.542258 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2641634 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 109154 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.200982 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 39074075000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.507176 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.959975 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.959975 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1619180 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1619180 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 952866 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 952866 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33989 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 33989 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32614 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 32614 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2572046 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2572046 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2572046 # number of overall hits -system.cpu1.dcache.overall_hits::total 2572046 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 209251 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 209251 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 220110 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 220110 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5396 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5396 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3146 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3146 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 429361 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 429361 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 429361 # number of overall misses -system.cpu1.dcache.overall_misses::total 429361 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3173212000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3173212000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7555840185 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7555840185 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56288500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 56288500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22631500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 22631500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10729052185 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10729052185 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10729052185 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10729052185 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1828431 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1828431 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172976 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1172976 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39385 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 39385 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35760 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35760 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3001407 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3001407 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3001407 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3001407 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114443 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.114443 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187651 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187651 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137006 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137006 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087975 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087975 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143053 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.143053 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143053 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.143053 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15164.620480 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15164.620480 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34327.564331 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34327.564331 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10431.523351 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10431.523351 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7193.738080 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7193.738080 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24988.418103 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24988.418103 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 240297 # number of cycles access was blocked +system.cpu1.dcache.occ_blocks::cpu1.data 491.542258 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.960043 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.960043 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1618348 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1618348 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 952576 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 952576 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33975 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 33975 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 32610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2570924 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2570924 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2570924 # number of overall hits +system.cpu1.dcache.overall_hits::total 2570924 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 209179 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 209179 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 220095 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 220095 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5405 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5405 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3147 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3147 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 429274 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 429274 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 429274 # number of overall misses +system.cpu1.dcache.overall_misses::total 429274 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3175995000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3175995000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7543341183 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7543341183 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56499500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 56499500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22652500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22652500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10719336183 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10719336183 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10719336183 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10719336183 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1827527 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1827527 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172671 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1172671 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39380 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 39380 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35757 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 35757 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3000198 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3000198 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3000198 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3000198 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114460 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114460 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187687 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.187687 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137252 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137252 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088011 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088011 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143082 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.143082 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143082 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.143082 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15183.144580 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15183.144580 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34273.114714 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34273.114714 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10453.191489 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10453.191489 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7198.125199 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7198.125199 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24970.848882 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24970.848882 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24970.848882 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24970.848882 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 239004 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3869 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3894 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 62.108297 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.377504 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 72108 # number of writebacks -system.cpu1.dcache.writebacks::total 72108 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129790 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 129790 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180827 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 180827 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 598 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 598 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 310617 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 310617 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 310617 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 310617 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79461 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 79461 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39283 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 39283 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4798 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4798 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3146 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3146 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 118744 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 118744 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 118744 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 118744 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 970446000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 970446000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1118523985 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1118523985 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38903500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38903500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16339500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16339500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088969985 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2088969985 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088969985 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2088969985 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30978500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30978500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647630000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647630000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678608500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678608500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043459 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043459 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033490 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033490 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121823 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121823 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039563 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039563 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12212.859138 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12212.859138 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28473.486877 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28473.486877 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.274281 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.274281 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5193.738080 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5193.738080 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 72044 # number of writebacks +system.cpu1.dcache.writebacks::total 72044 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129793 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 129793 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180819 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 180819 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 604 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 604 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 310612 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 310612 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 310612 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 310612 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79386 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 79386 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39276 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 39276 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4801 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4801 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3147 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3147 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 118662 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 118662 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 118662 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 118662 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 971821000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 971821000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1116428485 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1116428485 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39070500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39070500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16358500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16358500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088249485 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2088249485 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088249485 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2088249485 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30977500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30977500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647178500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647178500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678156000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678156000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043439 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043439 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033493 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033493 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121915 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121915 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088011 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088011 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039551 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039551 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039551 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039551 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.717683 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12241.717683 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28425.208397 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28425.208397 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8137.992085 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8137.992085 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5198.125199 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5198.125199 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17598.300088 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17598.300088 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17598.300088 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17598.300088 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1729,32 +1729,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6548 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 181674 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64152 40.43% 40.43% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 136 0.09% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.21% 41.73% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6549 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 181634 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64148 40.44% 40.44% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.52% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.21% 41.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92254 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158662 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63162 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 136 0.11% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.50% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 92227 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158624 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63158 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.50% 50.80% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 62971 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128389 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864385169000 98.14% 98.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63278000 0.00% 98.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567602000 0.03% 98.17% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 94599000 0.00% 98.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34650950500 1.82% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1899761598500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 62964 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128371 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862438042500 98.14% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62559000 0.00% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567042000 0.03% 98.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 94587500 0.00% 98.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34644439500 1.83% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897806670500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984567 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682583 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809198 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682707 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809279 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1793,53 +1793,53 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # nu system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151918 91.03% 93.32% # number of callpals executed -system.cpu0.kern.callpal::rdps 6167 3.70% 97.02% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151888 91.03% 93.33% # number of callpals executed +system.cpu0.kern.callpal::rdps 6165 3.69% 97.02% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4490 2.69% 99.72% # number of callpals executed +system.cpu0.kern.callpal::rti 4486 2.69% 99.72% # number of callpals executed system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 166884 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6992 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches +system.cpu0.kern.callpal::total 166848 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1259 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1257 -system.cpu0.kern.mode_good::user 1258 +system.cpu0.kern.mode_good::kernel 1258 +system.cpu0.kern.mode_good::user 1259 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.179777 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.180023 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.304848 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897853280000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1908310500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.305202 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1895901736500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1904926000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3470 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2463 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 58134 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18218 36.94% 36.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 3.90% 40.84% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2462 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58111 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18212 36.94% 36.94% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 3.90% 40.85% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28877 58.55% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49317 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17831 47.44% 47.44% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.12% 52.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 28864 58.55% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49296 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17825 47.44% 47.44% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 5.12% 52.56% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17534 46.65% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37587 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874537930000 98.69% 98.69% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532213500 0.03% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 134642000 0.01% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24250176000 1.28% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1899454961500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978757 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 17528 46.65% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37573 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872585348000 98.69% 98.69% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531683000 0.03% 98.71% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 134630500 0.01% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24248440000 1.28% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897500101500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978750 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.607196 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.762151 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.607262 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.762192 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1869,30 +1869,30 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # nu system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43997 85.81% 88.44% # number of callpals executed -system.cpu1.kern.callpal::rdps 2594 5.06% 93.50% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43980 85.81% 88.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2592 5.06% 93.50% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed -system.cpu1.kern.callpal::rti 3097 6.04% 99.56% # number of callpals executed +system.cpu1.kern.callpal::rti 3095 6.04% 99.56% # number of callpals executed system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 51275 # number of callpals executed +system.cpu1.kern.callpal::total 51254 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2438 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 709 -system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_switch::user 489 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 710 +system.cpu1.kern.mode_good::user 489 system.cpu1.kern.mode_good::idle 221 -system.cpu1.kern.mode_switch_good::kernel 0.497893 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.498596 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090648 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.325977 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4822300000 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 832322500 0.04% 0.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893789827000 99.70% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.090722 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.326512 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4824136000 0.25% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 831285000 0.04% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1891834463500 99.70% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1141 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |