diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3642 |
1 files changed, 1818 insertions, 1824 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 8de825134..353384b9f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903702 # Number of seconds simulated -sim_ticks 1903702212500 # Number of ticks simulated -final_tick 1903702212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904274 # Number of seconds simulated +sim_ticks 1904273734500 # Number of ticks simulated +final_tick 1904273734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94355 # Simulator instruction rate (inst/s) -host_op_rate 94355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3162860632 # Simulator tick rate (ticks/s) -host_mem_usage 314400 # Number of bytes of host memory used -host_seconds 601.89 # Real time elapsed on the host -sim_insts 56791782 # Number of instructions simulated -sim_ops 56791782 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 898816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24768192 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 430592 # Number of bytes read from this memory -system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 898816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7790720 # Number of bytes written to this memory -system.physmem.bytes_written::total 7790720 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387003 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6728 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121730 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121730 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 472141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13010539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 226187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15141931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 472141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4092405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4092405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4092405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 472141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13010539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 226187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19234336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450402 # Total number of read requests seen -system.physmem.writeReqs 121730 # Total number of write requests seen -system.physmem.cpureqs 577215 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28825728 # Total number of bytes read from memory -system.physmem.bytesWritten 7790720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7790720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5081 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28459 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28620 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7644 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6897 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7004 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7923 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8079 # Track writes on a per bank basis +host_inst_rate 95291 # Simulator instruction rate (inst/s) +host_op_rate 95291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3200085877 # Simulator tick rate (ticks/s) +host_mem_usage 314408 # Number of bytes of host memory used +host_seconds 595.07 # Real time elapsed on the host +sim_insts 56704659 # Number of instructions simulated +sim_ops 56704659 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 939456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24909888 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 36288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 341184 # Number of bytes read from this memory +system.physmem.bytes_read::total 28877632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 939456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 36288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 975744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7866880 # Number of bytes written to this memory +system.physmem.bytes_written::total 7866880 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389217 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 567 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5331 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451213 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122920 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122920 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 493341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13081044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1392035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 179168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15164643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 493341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4131171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4131171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4131171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 493341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13081044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1392035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 179168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19295814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451213 # Total number of read requests seen +system.physmem.writeReqs 122920 # Total number of write requests seen +system.physmem.cpureqs 579004 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28877632 # Total number of bytes read from memory +system.physmem.bytesWritten 7866880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28877632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7866880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4871 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28452 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28334 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27691 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7420 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7615 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7448 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7267 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7422 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7420 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8140 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8013 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7323 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 1903701167000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1904269209000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450402 # Categorize read packet sizes +system.physmem.readPktSize::6 451213 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121730 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1498 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122920 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1488 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -138,395 +138,398 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 910.430717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 224.153261 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2362.806871 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14303 35.57% 35.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6082 15.12% 50.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3751 9.33% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2511 6.24% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1745 4.34% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1426 3.55% 74.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1071 2.66% 76.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 838 2.08% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 669 1.66% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 518 1.29% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 558 1.39% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 522 1.30% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 270 0.67% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 231 0.57% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 190 0.47% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 283 0.70% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 119 0.30% 87.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 115 0.29% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 106 0.26% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 202 0.50% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 170 0.42% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 105 0.26% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 478 1.19% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 629 1.56% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 105 0.26% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 36 0.09% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 35 0.09% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 97 0.24% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 7 0.02% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 13 0.03% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 52 0.13% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 1 0.00% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.01% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.01% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 9 0.02% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 8 0.02% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 10 0.02% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 7 0.02% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 9 0.02% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 4 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 4 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 2 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 4 0.01% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 3 0.01% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2430 6.04% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 3741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 904.415372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.615874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2354.830128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14269 35.13% 35.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6234 15.35% 50.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3791 9.33% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2540 6.25% 66.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1773 4.36% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1547 3.81% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1102 2.71% 76.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 849 2.09% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 692 1.70% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 549 1.35% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 540 1.33% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 500 1.23% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 249 0.61% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 230 0.57% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 188 0.46% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 304 0.75% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 110 0.27% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 108 0.27% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 118 0.29% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 201 0.49% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 117 0.29% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 501 1.23% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 643 1.58% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 97 0.24% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 31 0.08% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 107 0.26% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 9 0.02% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 14 0.03% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 38 0.09% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 3 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 4 0.01% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 21 0.05% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 11 0.03% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 2 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.01% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 3 0.01% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 5 0.01% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.01% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 1 0.00% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.00% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2429 5.98% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.03% 99.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 251 0.62% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 8 0.02% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 248 0.61% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 7 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17219 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40212 # Bytes accessed per row activation -system.physmem.totQLat 6402871500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13861687750 # Sum of mem lat for all requests -system.physmem.totBusLat 2251705000 # Total cycles spent in databus access -system.physmem.totBankLat 5207111250 # Total cycles spent in bank access -system.physmem.avgQLat 14217.83 # Average queueing delay per request -system.physmem.avgBankLat 11562.60 # Average bank access latency per request +system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40619 # Bytes accessed per row activation +system.physmem.totQLat 6391304750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13854944750 # Sum of mem lat for all requests +system.physmem.totBusLat 2255690000 # Total cycles spent in databus access +system.physmem.totBankLat 5207950000 # Total cycles spent in bank access +system.physmem.avgQLat 14167.07 # Average queueing delay per request +system.physmem.avgBankLat 11544.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30780.43 # Average memory access latency -system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30711.10 # Average memory access latency +system.physmem.avgRdBW 15.16 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.13 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.16 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.13 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.34 # Average write queue length over time -system.physmem.readRowHits 434557 # Number of row buffer hits during reads -system.physmem.writeRowHits 97288 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.92 # Row buffer hit rate for writes -system.physmem.avgGap 3327381.04 # Average gap between requests -system.membus.throughput 19293384 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296598 # Transaction distribution -system.membus.trans_dist::ReadResp 296521 # Transaction distribution -system.membus.trans_dist::WriteReq 13135 # Transaction distribution -system.membus.trans_dist::WriteResp 13135 # Transaction distribution -system.membus.trans_dist::Writeback 121730 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10421 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6167 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5084 # Transaction distribution -system.membus.trans_dist::ReadExReq 162105 # Transaction distribution -system.membus.trans_dist::ReadExResp 161668 # Transaction distribution +system.physmem.avgWrQLen 14.33 # Average write queue length over time +system.physmem.readRowHits 435283 # Number of row buffer hits during reads +system.physmem.writeRowHits 98148 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes +system.physmem.avgGap 3316773.66 # Average gap between requests +system.membus.throughput 19353836 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296513 # Transaction distribution +system.membus.trans_dist::ReadResp 296436 # Transaction distribution +system.membus.trans_dist::WriteReq 13046 # Transaction distribution +system.membus.trans_dist::WriteResp 13046 # Transaction distribution +system.membus.trans_dist::Writeback 122920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9558 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5502 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4874 # Transaction distribution +system.membus.trans_dist::ReadExReq 162935 # Transaction distribution +system.membus.trans_dist::ReadExResp 162546 # Transaction distribution system.membus.trans_dist::BadAddressError 77 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921574 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 961398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 40658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1045233 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 962210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 40482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1046240 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1086045 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 74458 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31309568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31384026 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 74458 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36616448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36690906 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36690906 # Total data (bytes) -system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 38097999 # Layer occupancy (ticks) +system.membus.pkt_count::total 1086876 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31436416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31510170 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 36744512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36818266 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36818266 # Total data (bytes) +system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 37871498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1605971749 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1615737499 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 99000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3826622399 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3831920118 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376246245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376228744 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 343505 # number of replacements -system.l2c.tagsinuse 65255.093992 # Cycle average of tags in use -system.l2c.total_refs 2579423 # Total number of references to valid blocks. -system.l2c.sampled_refs 408514 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.314161 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6822436750 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53604.114045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5280.498450 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6105.169912 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 200.990170 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 64.321415 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.817934 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080574 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093157 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003067 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000981 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995714 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 854455 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 729616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 224847 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 72618 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1881536 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 819443 # number of Writeback hits -system.l2c.Writeback_hits::total 819443 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 291 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 461 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 69 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 152110 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27598 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179708 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 854455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 881726 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 224847 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 100216 # number of demand (read+write) hits -system.l2c.demand_hits::total 2061244 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 854455 # number of overall hits -system.l2c.overall_hits::cpu0.data 881726 # number of overall hits -system.l2c.overall_hits::cpu1.inst 224847 # number of overall hits -system.l2c.overall_hits::cpu1.data 100216 # number of overall hits -system.l2c.overall_hits::total 2061244 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14046 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273516 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1243 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 442 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289247 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2692 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1131 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3823 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 459 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 486 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 945 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114088 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6344 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120432 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14046 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387604 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1243 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6786 # number of demand (read+write) misses -system.l2c.demand_misses::total 409679 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14046 # number of overall misses -system.l2c.overall_misses::cpu0.data 387604 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1243 # number of overall misses -system.l2c.overall_misses::cpu1.data 6786 # number of overall misses -system.l2c.overall_misses::total 409679 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1212902500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17141442000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 111720500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 37403000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18503468000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 969500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5036492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 6005992 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 803000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 136500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 939500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9233070997 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 696312000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9929382997 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1212902500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26374512997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 111720500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 733715000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 28432850997 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1212902500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26374512997 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 111720500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 733715000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 28432850997 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 868501 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1003132 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 226090 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 73060 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2170783 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 819443 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 819443 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2862 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1422 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4284 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 502 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 512 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1014 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 266198 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 33942 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300140 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 868501 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1269330 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 226090 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 107002 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2470923 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 868501 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1269330 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 226090 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 107002 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2470923 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016173 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.272662 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005498 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006050 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133245 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940601 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795359 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.892390 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.914343 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.949219 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.931953 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.428583 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.186907 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.401253 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.305361 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005498 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.063419 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165800 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.305361 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005498 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.063419 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165800 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86352.164317 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 62670.710306 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 89879.726468 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 84622.171946 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 63971.166512 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 360.141159 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4453.131742 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1571.015433 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1749.455338 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 280.864198 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 994.179894 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80929.379050 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109759.142497 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 82448.045345 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 86352.164317 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 68044.996948 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 89879.726468 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 108121.868553 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69402.754344 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 86352.164317 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 68044.996948 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 89879.726468 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 108121.868553 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69402.754344 # average overall miss latency +system.l2c.tags.replacements 344278 # number of replacements +system.l2c.tags.tagsinuse 65254.004539 # Cycle average of tags in use +system.l2c.tags.total_refs 2578331 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 409473 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.296706 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53538.058266 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5369.862130 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6148.232371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 134.758747 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 63.093024 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.816926 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081938 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.093815 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000963 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995697 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 876771 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 739535 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 198332 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 63825 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1878463 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 821103 # number of Writeback hits +system.l2c.Writeback_hits::total 821103 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 177 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 256 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 433 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 156398 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 23000 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179398 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 876771 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 895933 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 198332 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 86825 # number of demand (read+write) hits +system.l2c.demand_hits::total 2057861 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 876771 # number of overall hits +system.l2c.overall_hits::cpu0.data 895933 # number of overall hits +system.l2c.overall_hits::cpu1.inst 198332 # number of overall hits +system.l2c.overall_hits::cpu1.data 86825 # number of overall hits +system.l2c.overall_hits::total 2057861 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 14688 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273591 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 576 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 306 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289161 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2677 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1042 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3719 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 416 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 449 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 865 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 116243 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5041 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121284 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 14688 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 389834 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 576 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 5347 # number of demand (read+write) misses +system.l2c.demand_misses::total 410445 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 14688 # number of overall misses +system.l2c.overall_misses::cpu0.data 389834 # number of overall misses +system.l2c.overall_misses::cpu1.inst 576 # number of overall misses +system.l2c.overall_misses::cpu1.data 5347 # number of overall misses +system.l2c.overall_misses::total 410445 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1267720492 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17201796982 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 49661500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 29444499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18548623473 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1381450 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 4584270 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 5965720 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 930960 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 99997 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1030957 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9514647474 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 547564734 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10062212208 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1267720492 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 26716444456 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 49661500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 577009233 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 28610835681 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1267720492 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 26716444456 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 49661500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 577009233 # number of overall miss cycles +system.l2c.overall_miss_latency::total 28610835681 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 891459 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1013126 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 198908 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 64131 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2167624 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 821103 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 821103 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2854 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1298 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4152 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 462 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 469 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 931 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 272641 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28041 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300682 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 891459 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1285767 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 198908 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 92172 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2468306 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 891459 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1285767 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 198908 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 92172 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2468306 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016476 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.270046 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.002896 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.004771 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.133400 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937982 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.802773 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.895713 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.900433 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.957356 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.929108 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.426359 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.179772 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.403363 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016476 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.303192 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.002896 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.058011 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166286 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016476 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.303192 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.002896 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.058011 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166286 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86309.946351 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 62874.133221 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 86217.881944 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 96223.852941 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 64146.352631 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 516.044079 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4399.491363 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1604.119387 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2237.884615 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 222.710468 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1191.857803 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81851.358568 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108622.244396 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 82964.053033 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 86309.946351 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 68532.874136 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 86217.881944 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 107912.704881 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 69706.868596 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 86309.946351 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 68532.874136 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 86217.881944 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 107912.704881 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 69706.868596 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,125 +538,125 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80210 # number of writebacks -system.l2c.writebacks::total 80210 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 81400 # number of writebacks +system.l2c.writebacks::total 81400 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 14045 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273516 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1227 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 441 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289229 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2692 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1131 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3823 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 459 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 486 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 945 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114088 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6344 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 120432 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 14045 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387604 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1227 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6785 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 409661 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 14045 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387604 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1227 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6785 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 409661 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1038052755 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13797110266 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 95353250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 31872500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 14962388771 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27111154 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11319121 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 38430275 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4611942 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4862486 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 9474428 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7837488031 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 618325539 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8455813570 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1038052755 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21634598297 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 95353250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 650198039 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 23418202341 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1038052755 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21634598297 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 95353250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 650198039 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 23418202341 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367369000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22027500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389396500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2032851000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 593731500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2626582500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3400220000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 615759000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4015979000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.272662 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006036 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.133237 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940601 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795359 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.892390 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914343 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949219 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.931953 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428583 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.186907 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.401253 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305361 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.063410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165793 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305361 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.063410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165793 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50443.521644 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72273.242630 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 51731.979750 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10071.008172 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.064545 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.386869 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.803922 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.115226 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.849735 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68696.865849 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 97466.194672 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70212.348628 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 14680 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273590 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 567 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 306 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289143 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2677 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1042 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3719 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 416 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 449 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 865 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 116243 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5041 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121284 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 14680 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389833 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 567 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 5347 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 410427 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 14680 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389833 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 567 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 5347 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 410427 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1080994508 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13790759768 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 41895250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 25609501 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 14939259027 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26999133 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10444004 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 37443137 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4166407 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4502447 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 8668854 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8081951526 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 484942766 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8566894292 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1080994508 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 21872711294 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 41895250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 510552267 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 23506153319 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1080994508 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 21872711294 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 41895250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 510552267 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 23506153319 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372582500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16978000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389560500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2039994500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 567881499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2607875999 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3412577000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 584859499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3997436499 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016467 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270045 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.002851 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.004771 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133392 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.802773 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.895713 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.900433 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.957356 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.929108 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.426359 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.179772 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.403363 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016467 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.303191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002851 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.058011 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166279 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016467 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.303191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002851 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.058011 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166279 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73637.228065 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50406.666062 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73889.329806 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 83691.179739 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 51667.372293 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10085.593201 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.036468 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.065878 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.401442 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.721604 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10021.796532 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69526.350197 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96199.715533 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70634.991359 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73637.228065 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56107.900804 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73889.329806 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95483.872639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57272.434121 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73637.228065 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56107.900804 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73889.329806 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95483.872639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57272.434121 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -664,15 +667,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41695 # number of replacements -system.iocache.tagsinuse 0.492474 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1710349466000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.492474 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.030780 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.030780 # Average percentage of cache occupancy +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.488928 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.488928 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030558 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030558 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -681,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41727 # n system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21568883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21568883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10518241771 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10518241771 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10539810654 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10539810654 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10539810654 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10539810654 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21574383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21574383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10460928278 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10460928278 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10482502661 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10482502661 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10482502661 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10482502661 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -705,19 +708,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123250.760000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123250.760000 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 253134.428451 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 253134.428451 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 252589.705802 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 252589.705802 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 276539 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123282.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123282.188571 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251755.108731 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251755.108731 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 251216.302658 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 251216.302658 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 272971 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27281 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27017 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.136689 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.103675 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -731,14 +734,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41727 system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12468133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8356835276 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8356835276 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8369303409 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8369303409 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8369303409 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8369303409 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12472883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12472883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8298854290 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8298854290 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8311327173 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8311327173 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8311327173 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8311327173 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -747,14 +750,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71246.474286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71246.474286 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 201117.522045 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 201117.522045 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71273.617143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71273.617143 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199722.138285 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199722.138285 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -768,35 +771,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12372167 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10430268 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 327512 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8051050 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5251093 # Number of BTB hits +system.cpu0.branchPred.lookups 12622908 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10616030 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 342195 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8196943 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5349460 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.222462 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 787082 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28165 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.261647 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 815211 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29656 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8811099 # DTB read hits -system.cpu0.dtb.read_misses 30390 # DTB read misses -system.cpu0.dtb.read_acv 555 # DTB read access violations -system.cpu0.dtb.read_accesses 626499 # DTB read accesses -system.cpu0.dtb.write_hits 5759352 # DTB write hits -system.cpu0.dtb.write_misses 7345 # DTB write misses -system.cpu0.dtb.write_acv 331 # DTB write access violations -system.cpu0.dtb.write_accesses 208988 # DTB write accesses -system.cpu0.dtb.data_hits 14570451 # DTB hits -system.cpu0.dtb.data_misses 37735 # DTB misses -system.cpu0.dtb.data_acv 886 # DTB access violations -system.cpu0.dtb.data_accesses 835487 # DTB accesses -system.cpu0.itb.fetch_hits 988720 # ITB hits -system.cpu0.itb.fetch_misses 28459 # ITB misses -system.cpu0.itb.fetch_acv 940 # ITB acv -system.cpu0.itb.fetch_accesses 1017179 # ITB accesses +system.cpu0.dtb.read_hits 9003860 # DTB read hits +system.cpu0.dtb.read_misses 33263 # DTB read misses +system.cpu0.dtb.read_acv 538 # DTB read access violations +system.cpu0.dtb.read_accesses 672573 # DTB read accesses +system.cpu0.dtb.write_hits 5893133 # DTB write hits +system.cpu0.dtb.write_misses 8284 # DTB write misses +system.cpu0.dtb.write_acv 368 # DTB write access violations +system.cpu0.dtb.write_accesses 235576 # DTB write accesses +system.cpu0.dtb.data_hits 14896993 # DTB hits +system.cpu0.dtb.data_misses 41547 # DTB misses +system.cpu0.dtb.data_acv 906 # DTB access violations +system.cpu0.dtb.data_accesses 908149 # DTB accesses +system.cpu0.itb.fetch_hits 1042149 # ITB hits +system.cpu0.itb.fetch_misses 31540 # ITB misses +system.cpu0.itb.fetch_acv 1064 # ITB acv +system.cpu0.itb.fetch_accesses 1073689 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -809,269 +812,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 113576100 # number of cpu cycles simulated +system.cpu0.numCycles 115698572 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24795587 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63494847 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12372167 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6038175 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11937811 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1694344 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37245698 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31806 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195246 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 359396 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7671411 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 221670 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 75653727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839282 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177028 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25430461 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 64765722 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12622908 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6164671 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12173111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1754282 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37681561 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 33129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 206182 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 360791 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 463 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7843120 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 77014869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.840951 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.178782 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63715916 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 763032 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1559362 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 696709 0.92% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2577784 3.41% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 516509 0.68% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 573501 0.76% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 819035 1.08% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4431879 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64841758 84.19% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 778083 1.01% 85.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1579221 2.05% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 722075 0.94% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2615191 3.40% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 535253 0.69% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 589170 0.77% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 842021 1.09% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4512097 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 75653727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.108933 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559051 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26076145 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36746783 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10850479 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 927296 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1053023 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 507905 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35356 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62314637 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105308 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1053023 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27090322 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15013520 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18214120 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10165522 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4117218 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58954969 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7221 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 636497 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1465868 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39489312 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71817747 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71438623 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 379124 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34689683 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4799621 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1442009 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 210125 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11209509 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9215492 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6028586 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1140138 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 729797 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52283270 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1794569 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51124724 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87475 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5854476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3047065 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1215266 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 75653727 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.675773 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.327184 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77014869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109102 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559780 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26714732 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 37197398 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11068686 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 941364 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1092688 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 522796 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36882 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 63559406 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 110759 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1092688 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27743135 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15107351 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18539290 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10375436 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4156967 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 60135459 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7108 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 639244 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1468640 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 40265671 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 73230382 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72843642 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 386740 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35289688 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4975975 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1473731 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 214800 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11344202 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9431276 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6179329 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1162337 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 768163 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53333771 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1831002 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52106137 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 101747 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6058761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3179609 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1240264 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77014869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.676572 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.327910 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52928215 69.96% 69.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10364815 13.70% 83.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4648030 6.14% 89.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3048990 4.03% 93.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2439160 3.22% 97.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1210231 1.60% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 645067 0.85% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 315070 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54149 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53895136 69.98% 69.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10485242 13.61% 83.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4754218 6.17% 89.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3135006 4.07% 93.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2479570 3.22% 97.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1230098 1.60% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 664050 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 318021 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53528 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 75653727 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77014869 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82277 12.13% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 315255 46.46% 58.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 280962 41.41% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83201 11.94% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 325493 46.71% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 288201 41.36% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35245093 68.94% 68.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56186 0.11% 69.06% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15594 0.03% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.09% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9165347 17.93% 87.02% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5826893 11.40% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 809947 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35867732 68.84% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57468 0.11% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15763 0.03% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9368607 17.98% 86.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5962928 11.44% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 827971 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51124724 # Type of FU issued -system.cpu0.iq.rate 0.450136 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 678494 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 178124739 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59681238 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50082929 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 544404 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 263662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 256861 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51514533 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 284900 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 542155 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52106137 # Type of FU issued +system.cpu0.iq.rate 0.450361 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 696895 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013375 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 181470771 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60967498 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51029740 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 555013 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 268874 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 261978 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52508945 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 290302 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 547963 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1111126 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3856 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12844 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 447697 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1165767 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4234 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13137 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 465736 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 153340 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18478 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 155290 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1053023 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10729289 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 792549 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57283617 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 622169 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9215492 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6028586 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1581349 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 577410 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6280 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12844 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 162347 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 348099 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 510446 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50735914 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8864635 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 388809 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1092688 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10796951 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 798319 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58424017 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 633798 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9431276 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6179329 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1612922 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 582630 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5498 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13137 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 168729 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 358890 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 527619 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51705429 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9061014 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 400707 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3205778 # number of nop insts executed -system.cpu0.iew.exec_refs 14644864 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8078425 # Number of branches executed -system.cpu0.iew.exec_stores 5780229 # Number of stores executed -system.cpu0.iew.exec_rate 0.446713 # Inst execution rate -system.cpu0.iew.wb_sent 50428595 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50339790 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25084021 # num instructions producing a value -system.cpu0.iew.wb_consumers 33790368 # num instructions consuming a value +system.cpu0.iew.exec_nop 3259244 # number of nop insts executed +system.cpu0.iew.exec_refs 14976241 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8231181 # Number of branches executed +system.cpu0.iew.exec_stores 5915227 # Number of stores executed +system.cpu0.iew.exec_rate 0.446898 # Inst execution rate +system.cpu0.iew.wb_sent 51387761 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51291718 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25550537 # num instructions producing a value +system.cpu0.iew.wb_consumers 34415470 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.443225 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742342 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443322 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742414 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6311482 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 579303 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 475138 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74600704 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.681919 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.596319 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6546847 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 590738 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 492268 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75922181 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681996 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.596696 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55419889 74.29% 74.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8033545 10.77% 85.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4371447 5.86% 90.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2356278 3.16% 94.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1324268 1.78% 95.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 555518 0.74% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 469565 0.63% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 427219 0.57% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1642975 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56427011 74.32% 74.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8133810 10.71% 85.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4455745 5.87% 90.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2411043 3.18% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1335893 1.76% 95.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 570067 0.75% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 478554 0.63% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 445477 0.59% 97.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1664581 2.19% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74600704 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50871658 # Number of instructions committed -system.cpu0.commit.committedOps 50871658 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75922181 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51778647 # Number of instructions committed +system.cpu0.commit.committedOps 51778647 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13685255 # Number of memory references committed -system.cpu0.commit.loads 8104366 # Number of loads committed -system.cpu0.commit.membars 196950 # Number of memory barriers committed -system.cpu0.commit.branches 7686240 # Number of branches committed -system.cpu0.commit.fp_insts 254806 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47114322 # Number of committed integer instructions. -system.cpu0.commit.function_calls 650737 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1642975 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13979102 # Number of memory references committed +system.cpu0.commit.loads 8265509 # Number of loads committed +system.cpu0.commit.membars 200777 # Number of memory barriers committed +system.cpu0.commit.branches 7822311 # Number of branches committed +system.cpu0.commit.fp_insts 259967 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47959803 # Number of committed integer instructions. +system.cpu0.commit.function_calls 666551 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1664581 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129943858 # The number of ROB reads -system.cpu0.rob.rob_writes 115419344 # The number of ROB writes -system.cpu0.timesIdled 1091777 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 37922373 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693821721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47948786 # Number of Instructions Simulated -system.cpu0.committedOps 47948786 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47948786 # Number of Instructions Simulated -system.cpu0.cpi 2.368696 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.368696 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.422173 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.422173 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66777793 # number of integer regfile reads -system.cpu0.int_regfile_writes 36448823 # number of integer regfile writes -system.cpu0.fp_regfile_reads 126128 # number of floating regfile reads -system.cpu0.fp_regfile_writes 127569 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1693303 # number of misc regfile reads -system.cpu0.misc_regfile_writes 810480 # number of misc regfile writes +system.cpu0.rob.rob_reads 132380203 # The number of ROB reads +system.cpu0.rob.rob_writes 117743806 # The number of ROB writes +system.cpu0.timesIdled 1106178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38683703 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3692842270 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48811521 # Number of Instructions Simulated +system.cpu0.committedOps 48811521 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 48811521 # Number of Instructions Simulated +system.cpu0.cpi 2.370313 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.370313 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.421885 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.421885 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68020458 # number of integer regfile reads +system.cpu0.int_regfile_writes 37124303 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128594 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130201 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1727987 # number of misc regfile reads +system.cpu0.misc_regfile_writes 827975 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1103,49 +1106,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111431458 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2199741 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2199647 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13135 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13135 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 819443 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10566 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6236 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16802 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343057 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301508 # Transaction distribution +system.toL2Bus.throughput 111303171 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2194950 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2194857 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13046 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13046 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 821103 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9701 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5568 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15269 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343378 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301828 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1737096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3343563 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 452207 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 314296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5847162 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 55584064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 129094452 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 14469760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 11514982 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 210663258 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210652954 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1479360 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4959879460 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1783020 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3388598 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 397843 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 270349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5839810 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 57053376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 131002064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 12730112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 9815754 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 210601306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210591002 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1360704 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964254488 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3910967404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4017252621 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5778463419 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5927096055 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1017961113 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 540290711 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 895637092 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 468506529 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1437243 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54687 # Transaction distribution -system.iobus.trans_dist::WriteResp 54687 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1436442 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 54598 # Transaction distribution +system.iobus.trans_dist::WriteResp 54598 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1156,11 +1159,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40482 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1172,9 +1175,9 @@ system.iobus.pkt_count::system.tsunami.ethernet.pio 102 system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 124112 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123936 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1185,11 +1188,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 74458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 73754 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1201,11 +1204,11 @@ system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2736082 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2736082 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11417000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2735378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2735378 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11237000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1225,253 +1228,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378279654 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378252917 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27523000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27436000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43098256 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.replacements 867916 # number of replacements -system.cpu0.icache.tagsinuse 509.785268 # Cycle average of tags in use -system.cpu0.icache.total_refs 6758563 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 868427 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.782534 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25769681000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.785268 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995674 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995674 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6758564 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6758564 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6758564 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6758564 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6758564 # number of overall hits -system.cpu0.icache.overall_hits::total 6758564 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 912847 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 912847 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 912847 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 912847 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 912847 # number of overall misses -system.cpu0.icache.overall_misses::total 912847 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13149310993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13149310993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13149310993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13149310993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13149310993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13149310993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7671411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7671411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7671411 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7671411 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7671411 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7671411 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118993 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118993 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118993 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118993 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118993 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118993 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14404.726086 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14404.726086 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14404.726086 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14404.726086 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3418 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 152 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.486842 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 890887 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.759385 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6905559 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891396 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.746904 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.759385 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995624 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995624 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6905559 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6905559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6905559 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6905559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6905559 # number of overall hits +system.cpu0.icache.overall_hits::total 6905559 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 937559 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 937559 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 937559 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 937559 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 937559 # number of overall misses +system.cpu0.icache.overall_misses::total 937559 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13556216106 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13556216106 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13556216106 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13556216106 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13556216106 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13556216106 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7843118 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7843118 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7843118 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7843118 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7843118 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7843118 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119539 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119539 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119539 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119539 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119539 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119539 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14459.053890 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14459.053890 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14459.053890 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14459.053890 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6417 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1109 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.168182 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 554.500000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44252 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44252 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44252 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44252 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44252 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44252 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868595 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 868595 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 868595 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 868595 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 868595 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 868595 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814937089 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814937089 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814937089 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10814937089 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814937089 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10814937089 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113225 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113225 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113225 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12451.069934 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45998 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45998 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45998 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45998 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45998 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45998 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 891561 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 891561 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 891561 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 891561 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 891561 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 891561 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11118457121 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11118457121 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11118457121 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11118457121 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11118457121 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11118457121 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113674 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113674 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113674 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12470.775551 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1271376 # number of replacements -system.cpu0.dcache.tagsinuse 505.686526 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10390956 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1271888 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.169710 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 25830000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.686526 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987669 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987669 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6393137 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6393137 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3639350 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3639350 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 161427 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 161427 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185616 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 185616 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10032487 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10032487 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10032487 # number of overall hits -system.cpu0.dcache.overall_hits::total 10032487 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1573505 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1573505 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1738147 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1738147 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20045 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20045 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3020 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3020 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3311652 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3311652 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3311652 # number of overall misses -system.cpu0.dcache.overall_misses::total 3311652 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39654304500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39654304500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77521243901 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77521243901 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 292960500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 292960500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 22204000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 22204000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117175548401 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117175548401 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117175548401 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117175548401 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7966642 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7966642 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5377497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5377497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 181472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 188636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13344139 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13344139 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13344139 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13344139 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197512 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197512 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323226 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323226 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110458 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110458 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248173 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248173 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248173 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248173 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25201.257384 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25201.257384 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44599.935392 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44599.935392 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14615.140933 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14615.140933 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7352.317881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7352.317881 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35382.808460 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35382.808460 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2842539 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 840 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 51698 # number of cycles access was blocked +system.cpu0.dcache.tags.replacements 1288020 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.688069 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10644807 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1288532 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.261189 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.688069 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987672 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.987672 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6550900 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6550900 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3728429 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3728429 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165070 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 165070 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189835 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189835 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10279329 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10279329 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10279329 # number of overall hits +system.cpu0.dcache.overall_hits::total 10279329 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1597921 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1597921 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1777729 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1777729 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20672 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20672 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2669 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2669 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3375650 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3375650 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3375650 # number of overall misses +system.cpu0.dcache.overall_misses::total 3375650 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40268021859 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40268021859 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79880065793 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79880065793 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301767496 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 301767496 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20162915 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20162915 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 120148087652 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 120148087652 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 120148087652 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 120148087652 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8148821 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8148821 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5506158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5506158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185742 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 185742 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13654979 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13654979 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13654979 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13654979 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196092 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.196092 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322862 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.322862 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111294 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111294 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013865 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013865 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247210 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.247210 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247210 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.247210 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25200.258247 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25200.258247 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44933.769879 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44933.769879 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14597.885836 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14597.885836 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7554.482952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7554.482952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35592.578511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35592.578511 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2948269 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 52342 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 54.983539 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 120 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 56.327022 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 746874 # number of writebacks -system.cpu0.dcache.writebacks::total 746874 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 575080 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 575080 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465992 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1465992 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4461 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4461 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2041072 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2041072 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2041072 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2041072 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 998425 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 998425 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272155 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272155 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3020 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3020 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1270580 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1270580 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1270580 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1270580 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26454916051 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26454916051 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11388682739 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11388682739 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172348003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172348003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 16164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 16164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 37843598790 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 37843598790 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 37843598790 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 37843598790 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459347502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459347502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2156087498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2156087498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3615435000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3615435000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085876 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085876 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095216 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095216 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26496.648272 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26496.648272 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41846.310885 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41846.310885 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11059.291774 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11059.291774 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5352.317881 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5352.317881 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 760237 # number of writebacks +system.cpu0.dcache.writebacks::total 760237 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 590547 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 590547 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1499620 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1499620 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4585 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4585 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2090167 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2090167 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2090167 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2090167 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007374 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1007374 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 278109 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 278109 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2668 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2668 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1285483 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1285483 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1285483 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1285483 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26624787726 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26624787726 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11708735082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11708735082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178034254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178034254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14826085 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14826085 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38333522808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38333522808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38333522808 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38333522808 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465041000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465041000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2164117998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2164117998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3629158998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3629158998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123622 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123622 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050509 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050509 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013859 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013859 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094140 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094140 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26429.893690 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26429.893690 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42101.244771 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42101.244771 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11066.964257 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11066.964257 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5557.003373 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5557.003373 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1479,35 +1482,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2604526 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2153409 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 75247 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1513707 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 876072 # Number of BTB hits +system.cpu1.branchPred.lookups 2340238 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1946356 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 62804 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1358794 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 776922 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.875930 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 179167 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7740 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.177320 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 157214 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 6628 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1932131 # DTB read hits -system.cpu1.dtb.read_misses 10237 # DTB read misses -system.cpu1.dtb.read_acv 25 # DTB read access violations -system.cpu1.dtb.read_accesses 320506 # DTB read accesses -system.cpu1.dtb.write_hits 1251341 # DTB write hits -system.cpu1.dtb.write_misses 1962 # DTB write misses -system.cpu1.dtb.write_acv 65 # DTB write access violations -system.cpu1.dtb.write_accesses 130037 # DTB write accesses -system.cpu1.dtb.data_hits 3183472 # DTB hits -system.cpu1.dtb.data_misses 12199 # DTB misses -system.cpu1.dtb.data_acv 90 # DTB access violations -system.cpu1.dtb.data_accesses 450543 # DTB accesses -system.cpu1.itb.fetch_hits 430844 # ITB hits -system.cpu1.itb.fetch_misses 6753 # ITB misses -system.cpu1.itb.fetch_acv 212 # ITB acv -system.cpu1.itb.fetch_accesses 437597 # ITB accesses +system.cpu1.dtb.read_hits 1733483 # DTB read hits +system.cpu1.dtb.read_misses 9288 # DTB read misses +system.cpu1.dtb.read_acv 9 # DTB read access violations +system.cpu1.dtb.read_accesses 276268 # DTB read accesses +system.cpu1.dtb.write_hits 1103623 # DTB write hits +system.cpu1.dtb.write_misses 1818 # DTB write misses +system.cpu1.dtb.write_acv 38 # DTB write access violations +system.cpu1.dtb.write_accesses 104203 # DTB write accesses +system.cpu1.dtb.data_hits 2837106 # DTB hits +system.cpu1.dtb.data_misses 11106 # DTB misses +system.cpu1.dtb.data_acv 47 # DTB access violations +system.cpu1.dtb.data_accesses 380471 # DTB accesses +system.cpu1.itb.fetch_hits 375000 # ITB hits +system.cpu1.itb.fetch_misses 5508 # ITB misses +system.cpu1.itb.fetch_acv 148 # ITB acv +system.cpu1.itb.fetch_accesses 380508 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1520,508 +1523,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 15794943 # number of cpu cycles simulated +system.cpu1.numCycles 14113255 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6044274 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12313553 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2604526 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1055239 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2204838 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 395965 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6209579 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26246 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62195 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 53260 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1481011 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50405 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14852690 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.829045 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.204427 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5353605 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 10974333 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2340238 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 934136 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1960258 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 346091 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 5695969 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 25528 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 53832 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 54284 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1309338 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 41617 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 13363974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.821188 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.197770 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12647852 85.16% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 141564 0.95% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 235652 1.59% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 175889 1.18% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 303768 2.05% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 119285 0.80% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 129403 0.87% 92.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 209113 1.41% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 890164 5.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11403716 85.33% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 124023 0.93% 86.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 213549 1.60% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 153465 1.15% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 264643 1.98% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 105166 0.79% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 115273 0.86% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 186335 1.39% 94.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 797804 5.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14852690 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164896 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.779588 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5971093 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6462269 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2062064 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 112088 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 245175 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 113398 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7205 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12081319 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21458 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 245175 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6179272 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 425366 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5395094 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1962879 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 644902 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11197795 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 57093 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 157527 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7361429 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13363056 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13213666 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 149390 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6300177 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1061252 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 451071 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 42573 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1993362 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2041709 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1326014 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 180090 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 100258 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9822573 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 491625 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9565946 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29815 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1410113 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 705464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352077 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14852690 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644055 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.318534 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13363974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.165818 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.777590 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5293087 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 5922521 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1836128 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 97560 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 214677 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 97799 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5876 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10774764 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 17225 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 214677 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5481600 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 352411 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4990949 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1741665 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 582670 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 9967248 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 54670 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 132191 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 6553947 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 11886744 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 11748684 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 138060 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5636582 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 917365 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 415822 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 37623 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1815514 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1827244 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1170543 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 163690 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 89610 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8737156 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 452580 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8518295 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27160 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1245229 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 620627 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 325893 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13363974 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.637407 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.312561 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10648951 71.70% 71.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1930050 12.99% 84.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 818337 5.51% 90.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 551122 3.71% 93.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 476075 3.21% 97.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 213789 1.44% 98.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 136394 0.92% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 69529 0.47% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8443 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9608930 71.90% 71.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1736625 12.99% 84.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 727835 5.45% 90.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 487296 3.65% 93.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 421265 3.15% 97.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 191133 1.43% 98.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 120060 0.90% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 63613 0.48% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 7217 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14852690 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13363974 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3207 1.63% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 106178 53.97% 55.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 87357 44.40% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2685 1.53% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 94663 54.03% 55.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 77863 44.44% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5966011 62.37% 62.40% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16243 0.17% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10971 0.11% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2021702 21.13% 83.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1274955 13.33% 97.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 270775 2.83% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5299330 62.21% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14840 0.17% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10732 0.13% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1812344 21.28% 83.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1125275 13.21% 97.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 250497 2.94% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9565946 # Type of FU issued -system.cpu1.iq.rate 0.605633 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 196742 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020567 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 33995446 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11620704 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9288457 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 215693 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 105258 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 101999 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9646700 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 112462 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 92569 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8518295 # Type of FU issued +system.cpu1.iq.rate 0.603567 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 175211 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020569 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 30403276 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10338814 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8274405 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 199659 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 97460 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 94461 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8585899 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 104089 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 83773 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 282729 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1535 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1711 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 123624 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 247116 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1193 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1397 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 111584 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 323 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 14236 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 14213 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 245175 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 256542 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 43339 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10829040 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 147658 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2041709 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1326014 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 444647 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 36382 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1620 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1711 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 33953 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 99696 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 133649 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9473535 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1949759 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 92411 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 214677 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 210872 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 38123 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9643840 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 131515 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1827244 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1170543 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 410565 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 32525 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1557 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1397 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28168 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 87904 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 116072 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8443529 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1749257 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 74766 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 514842 # number of nop insts executed -system.cpu1.iew.exec_refs 3209162 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1413585 # Number of branches executed -system.cpu1.iew.exec_stores 1259403 # Number of stores executed -system.cpu1.iew.exec_rate 0.599783 # Inst execution rate -system.cpu1.iew.wb_sent 9417236 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9390456 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4401006 # num instructions producing a value -system.cpu1.iew.wb_consumers 6190652 # num instructions consuming a value +system.cpu1.iew.exec_nop 454104 # number of nop insts executed +system.cpu1.iew.exec_refs 2860324 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1252098 # Number of branches executed +system.cpu1.iew.exec_stores 1111067 # Number of stores executed +system.cpu1.iew.exec_rate 0.598269 # Inst execution rate +system.cpu1.iew.wb_sent 8394111 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8368866 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3943473 # num instructions producing a value +system.cpu1.iew.wb_consumers 5568899 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.594523 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710912 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.592979 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708124 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1449457 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 139548 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 125475 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14607515 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.636458 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.578813 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1277535 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126687 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 110026 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13149297 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.631052 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.572436 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11126487 76.17% 76.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1625013 11.12% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 604004 4.13% 91.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 371910 2.55% 93.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 263907 1.81% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 102565 0.70% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 109537 0.75% 97.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 110097 0.75% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 293995 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10035587 76.32% 76.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1461499 11.11% 87.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 536339 4.08% 91.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 329312 2.50% 94.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 237007 1.80% 95.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 91157 0.69% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 98866 0.75% 97.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 97470 0.74% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 262060 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14607515 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9297065 # Number of instructions committed -system.cpu1.commit.committedOps 9297065 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13149297 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8297892 # Number of instructions committed +system.cpu1.commit.committedOps 8297892 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2961370 # Number of memory references committed -system.cpu1.commit.loads 1758980 # Number of loads committed -system.cpu1.commit.membars 44792 # Number of memory barriers committed -system.cpu1.commit.branches 1328076 # Number of branches committed -system.cpu1.commit.fp_insts 100787 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8610735 # Number of committed integer instructions. -system.cpu1.commit.function_calls 147103 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 293995 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2639087 # Number of memory references committed +system.cpu1.commit.loads 1580128 # Number of loads committed +system.cpu1.commit.membars 40354 # Number of memory barriers committed +system.cpu1.commit.branches 1179945 # Number of branches committed +system.cpu1.commit.fp_insts 93281 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7680197 # Number of committed integer instructions. +system.cpu1.commit.function_calls 130349 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 262060 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 24970897 # The number of ROB reads -system.cpu1.rob.rob_writes 21736671 # The number of ROB writes -system.cpu1.timesIdled 134601 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 942253 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3790981004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8842996 # Number of Instructions Simulated -system.cpu1.committedOps 8842996 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8842996 # Number of Instructions Simulated -system.cpu1.cpi 1.786153 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.786153 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.559862 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.559862 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12205153 # number of integer regfile reads -system.cpu1.int_regfile_writes 6674473 # number of integer regfile writes -system.cpu1.fp_regfile_reads 55471 # number of floating regfile reads -system.cpu1.fp_regfile_writes 55305 # number of floating regfile writes -system.cpu1.misc_regfile_reads 527113 # number of misc regfile reads -system.cpu1.misc_regfile_writes 218222 # number of misc regfile writes -system.cpu1.icache.replacements 225540 # number of replacements -system.cpu1.icache.tagsinuse 470.721925 # Cycle average of tags in use -system.cpu1.icache.total_refs 1246547 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 226052 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.514426 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1877726350000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.721925 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919379 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919379 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1246547 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1246547 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1246547 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1246547 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1246547 # number of overall hits -system.cpu1.icache.overall_hits::total 1246547 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 234464 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 234464 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 234464 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 234464 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 234464 # number of overall misses -system.cpu1.icache.overall_misses::total 234464 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3166624000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3166624000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3166624000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3166624000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3166624000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3166624000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1481011 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1481011 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1481011 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1481011 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1481011 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1481011 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158313 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.158313 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158313 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.158313 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158313 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.158313 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.800464 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.800464 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13505.800464 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13505.800464 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked +system.cpu1.rob.rob_reads 22380631 # The number of ROB reads +system.cpu1.rob.rob_writes 19363835 # The number of ROB writes +system.cpu1.timesIdled 119058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 749281 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3793736462 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 7893138 # Number of Instructions Simulated +system.cpu1.committedOps 7893138 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 7893138 # Number of Instructions Simulated +system.cpu1.cpi 1.788041 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.788041 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.559271 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.559271 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 10874027 # number of integer regfile reads +system.cpu1.int_regfile_writes 5958512 # number of integer regfile writes +system.cpu1.fp_regfile_reads 51748 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51512 # number of floating regfile writes +system.cpu1.misc_regfile_reads 484557 # number of misc regfile reads +system.cpu1.misc_regfile_writes 198633 # number of misc regfile writes +system.cpu1.icache.tags.replacements 198364 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.505741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1103940 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 198874 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.550952 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1894556454000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.505741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918957 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.918957 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1103940 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1103940 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1103940 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1103940 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1103940 # number of overall hits +system.cpu1.icache.overall_hits::total 1103940 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 205398 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 205398 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 205398 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 205398 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 205398 # number of overall misses +system.cpu1.icache.overall_misses::total 205398 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2726676790 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2726676790 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2726676790 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2726676790 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2726676790 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2726676790 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1309338 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1309338 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1309338 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1309338 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1309338 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1309338 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.156872 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.156872 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.156872 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.156872 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.156872 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.156872 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13275.089290 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13275.089290 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13275.089290 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13275.089290 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.777778 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.166667 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8347 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8347 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8347 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8347 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8347 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8347 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 226117 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 226117 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 226117 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 226117 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 226117 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 226117 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2628094387 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2628094387 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2628094387 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2628094387 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2628094387 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2628094387 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152677 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.152677 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.152677 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11622.719154 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6463 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6463 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6463 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6463 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6463 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6463 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 198935 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 198935 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 198935 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 198935 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 198935 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 198935 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2267895657 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2267895657 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2267895657 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2267895657 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2267895657 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2267895657 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151936 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.151936 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.151936 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11400.184266 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 108851 # number of replacements -system.cpu1.dcache.tagsinuse 491.736427 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2599646 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 109251 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 23.795169 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 43858959000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.736427 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.960423 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.960423 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1587502 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1587502 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 943251 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 943251 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32579 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 32579 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 31559 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 31559 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2530753 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2530753 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2530753 # number of overall hits -system.cpu1.dcache.overall_hits::total 2530753 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 209244 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 209244 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 218379 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 218379 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5510 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5510 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3216 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3216 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 427623 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 427623 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 427623 # number of overall misses -system.cpu1.dcache.overall_misses::total 427623 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2938034500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2938034500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7305073698 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7305073698 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 55149000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 55149000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 23385500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 23385500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10243108198 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10243108198 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10243108198 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10243108198 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1796746 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1796746 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1161630 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1161630 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38089 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 38089 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 34775 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 34775 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2958376 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2958376 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2958376 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2958376 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.116457 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.116457 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187994 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187994 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.144661 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.144661 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092480 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092480 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.144547 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.144547 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.144547 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.144547 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14041.188756 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14041.188756 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33451.356119 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33451.356119 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10008.892922 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10008.892922 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7271.610697 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7271.610697 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23953.595101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23953.595101 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 227083 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 93782 # number of replacements +system.cpu1.dcache.tags.tagsinuse 490.645175 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2322631 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 94098 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.683107 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.645175 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958291 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.958291 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1425624 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1425624 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 844173 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 844173 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 28774 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 28774 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27671 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 27671 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2269797 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2269797 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2269797 # number of overall hits +system.cpu1.dcache.overall_hits::total 2269797 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 184725 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 184725 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178548 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178548 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4789 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4789 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2902 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2902 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 363273 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 363273 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 363273 # number of overall misses +system.cpu1.dcache.overall_misses::total 363273 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2584165220 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2584165220 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5809552721 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5809552721 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46614997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46614997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21574947 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 21574947 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8393717941 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8393717941 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8393717941 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8393717941 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1610349 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1610349 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1022721 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1022721 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33563 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 33563 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30573 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 30573 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2633070 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2633070 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2633070 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2633070 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114711 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114711 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174581 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.174581 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142687 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142687 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.137966 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.137966 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.137966 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.137966 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.255488 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.255488 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32537.764192 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32537.764192 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9733.764251 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9733.764251 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7434.509649 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7434.509649 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23105.812821 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23105.812821 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 188355 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 4054 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3483 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.014554 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 54.078381 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 72569 # number of writebacks -system.cpu1.dcache.writebacks::total 72569 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129770 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 129770 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 179212 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 179212 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 594 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 594 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 308982 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 308982 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 308982 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 308982 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79474 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 79474 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39167 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 39167 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4916 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4916 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3216 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3216 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 118641 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 118641 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 118641 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 118641 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 893939249 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 893939249 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081571527 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081571527 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37210004 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37210004 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16953500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16953500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1975510776 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1975510776 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1975510776 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1975510776 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23615501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23615501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 628297501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 628297501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 651913002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 651913002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044232 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044232 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.129066 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.129066 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092480 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092480 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040103 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040103 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11248.197511 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11248.197511 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27614.357163 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27614.357163 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7569.162734 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7569.162734 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5271.610697 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5271.610697 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 60866 # number of writebacks +system.cpu1.dcache.writebacks::total 60866 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 114750 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 114750 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 145883 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 145883 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 398 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 398 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 260633 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 260633 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 260633 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 260633 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69975 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 69975 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32665 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 32665 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4391 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4391 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 102640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 102640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 102640 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 102640 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 781048941 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 781048941 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 869596715 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 869596715 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32787753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32787753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15774053 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15774053 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1650645656 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1650645656 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1650645656 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1650645656 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18096000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18096000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600498502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 600498502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 618594502 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 618594502 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031939 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031939 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130829 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130829 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094855 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094855 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038981 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038981 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11161.828382 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11161.828382 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26621.665850 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26621.665850 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7467.035527 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7467.035527 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5439.328621 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5439.328621 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2030,170 +2033,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6605 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 182638 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64421 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.21% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 210 0.13% 41.93% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92368 58.07% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 159055 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63463 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.49% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 210 0.16% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63253 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128982 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863089530500 97.87% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64074500 0.00% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567937500 0.03% 97.90% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 100797000 0.01% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39879064000 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903701403500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.985129 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6628 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 186556 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65870 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.19% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 193 0.12% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94141 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162260 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64876 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.46% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 193 0.15% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64684 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131809 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863192383000 97.84% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64528500 0.00% 97.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571927000 0.03% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 92721000 0.00% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40351323000 2.12% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904272882500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984910 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684793 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810927 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.687097 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812332 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 302 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3478 2.07% 2.26% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 152288 90.83% 93.12% # number of callpals executed -system.cpu0.kern.callpal::rdps 6536 3.90% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4500 2.68% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.21% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167660 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7044 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches +system.cpu0.kern.callpal::wripir 275 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3568 2.09% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155408 90.82% 93.10% # number of callpals executed +system.cpu0.kern.callpal::rdps 6655 3.89% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4603 2.69% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 171120 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7202 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1285 -system.cpu0.kern.mode_good::user 1286 +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.182425 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.190225 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.308643 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901692288000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2009107500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.319725 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1902171924000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2100950500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3479 # number of times the context was actually changed +system.cpu0.kern.swap_context 3569 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 57331 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18009 36.73% 36.73% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.92% 40.65% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 302 0.62% 41.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28797 58.73% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49032 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17590 47.41% 47.41% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 5.19% 52.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 302 0.81% 53.41% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17288 46.59% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37104 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1873168497000 98.41% 98.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531845000 0.03% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 136792000 0.01% 98.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29552054000 1.55% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903389188000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976734 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2405 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 53020 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16452 36.11% 36.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 4.22% 40.33% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 275 0.60% 40.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26914 59.07% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45564 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16069 47.18% 47.18% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 5.65% 52.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 275 0.81% 53.63% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15794 46.37% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34061 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1873583378500 98.41% 98.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531505500 0.03% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 123925000 0.01% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29687237000 1.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903926046000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976720 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.600340 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.756730 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.586832 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.747542 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 210 0.41% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wripir 193 0.41% 0.41% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1165 2.30% 2.72% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.73% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.75% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43701 86.29% 89.04% # number of callpals executed -system.cpu1.kern.callpal::rdps 2223 4.39% 93.43% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.43% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.44% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.44% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.44% # number of callpals executed -system.cpu1.kern.callpal::rti 3104 6.13% 99.57% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.34% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1035 2.21% 2.63% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.63% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.65% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40418 86.22% 88.87% # number of callpals executed +system.cpu1.kern.callpal::rdps 2100 4.48% 93.35% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.35% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.36% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.36% # number of callpals executed +system.cpu1.kern.callpal::rti 2947 6.29% 99.65% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.26% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 50643 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1414 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2447 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 685 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 226 -system.cpu1.kern.mode_switch_good::kernel 0.484441 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 46877 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1217 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2392 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 567 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 200 +system.cpu1.kern.mode_switch_good::kernel 0.465900 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.092358 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.317130 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4654463000 0.24% 0.24% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 807268500 0.04% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1897916233000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1166 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.083612 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.285211 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3949860500 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 686482000 0.04% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1898967291500 99.76% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1036 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |