diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual')
5 files changed, 2292 insertions, 2044 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index c1955556a..ac0bee128 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -15,10 +15,12 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/work/gem5/dist/binaries/console +console=/arm/projectscratch/randd/systems/dist/binaries/console +default_p_state=UNDEFINED eventq_index=0 +exit_on_work_items=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -28,11 +30,17 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -pal=/work/gem5/dist/binaries/ts_osfpal -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh symbolfile= system_rev=1024 system_type=34 +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -45,8 +53,13 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -85,6 +98,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -121,6 +135,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -160,11 +178,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu0.dcache] type=Cache @@ -173,13 +198,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -198,8 +227,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -522,13 +556,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -547,8 +585,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -594,6 +637,7 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -630,6 +674,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -669,11 +717,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu1.dcache] type=Cache @@ -682,13 +737,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -707,8 +766,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1031,13 +1095,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -1056,8 +1124,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1107,7 +1180,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-latest.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -1130,7 +1203,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-bigswap2.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -1149,9 +1222,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1165,13 +1243,17 @@ addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1190,8 +1272,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1202,13 +1289,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1227,20 +1318,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1252,11 +1354,16 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1267,6 +1374,13 @@ update_data=false warn_access= pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -1301,6 +1415,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1312,7 +1427,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 @@ -1354,7 +1473,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-latest.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1369,9 +1488,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1399,11 +1524,16 @@ system=system type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 +default_p_state=UNDEFINED disk=system.simple_disk eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[24] @@ -1411,9 +1541,14 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8803072344064 pio_latency=100000 +power_model=Null system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -1494,6 +1629,7 @@ SubsystemVendorID=0 VendorID=4107 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED dma_data_free=false dma_desc_free=false dma_no_allocate=true @@ -1505,10 +1641,14 @@ eventq_index=0 hardware_address=00:90:00:00:00:01 host=system.tsunami.pchip intr_delay=10000000 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -1524,11 +1664,16 @@ pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8796093677568 pio_latency=100000 pio_size=393216 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1542,11 +1687,16 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848432 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1560,11 +1710,16 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848304 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1578,11 +1733,16 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848569 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1596,11 +1756,16 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848451 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1614,11 +1779,16 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848515 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1632,11 +1802,16 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848579 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1650,11 +1825,16 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848643 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1668,11 +1848,16 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848707 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1686,11 +1871,16 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848771 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1704,11 +1894,16 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848835 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1722,11 +1917,16 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848899 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1740,11 +1940,16 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615850617 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1758,11 +1963,16 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848891 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1776,11 +1986,16 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848816 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1794,11 +2009,16 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848696 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1812,11 +2032,16 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848936 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1830,11 +2055,16 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848680 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1848,11 +2078,16 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848944 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1866,10 +2101,15 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice clk_domain=system.clk_domain +default_p_state=UNDEFINED devicename=FrameBuffer eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848912 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1950,14 +2190,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.disk0 system.disk2 eventq_index=0 host=system.tsunami.pchip io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1965,10 +2210,15 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 frequency=976562500 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615847936 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1981,13 +2231,18 @@ clk_domain=system.clk_domain conf_base=8804649402368 conf_device_bits=8 conf_size=16777216 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=8796093022208 pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 platform=system.tsunami +power_model=Null system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1995,10 +2250,15 @@ pio=system.iobus.master[1] [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[23] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index 518507880..9acbae09f 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -1,5 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index f71ac7b91..b3e079503 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,14 +1,16 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 10:28:58 -gem5 started Dec 4 2015 10:42:11 -gem5 executing on e104799-lin, pid 22878 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Jul 19 2016 12:23:51 +gem5 started Jul 19 2016 12:24:23 +gem5 executing on e108600-lin, pid 39569 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 179187500 -Exiting @ tick 1922761887500 because m5_exit instruction encountered +info: Launching CPU 1 @ 127844500 +Exiting @ tick 1907672102500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 0eee642ef..1d7e55213 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.908652 # Number of seconds simulated -sim_ticks 1908652088000 # Number of ticks simulated -final_tick 1908652088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.907672 # Number of seconds simulated +sim_ticks 1907672102500 # Number of ticks simulated +final_tick 1907672102500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205918 # Simulator instruction rate (inst/s) -host_op_rate 205918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6997264233 # Simulator tick rate (ticks/s) -host_mem_usage 384940 # Number of bytes of host memory used -host_seconds 272.77 # Real time elapsed on the host -sim_insts 56168509 # Number of instructions simulated -sim_ops 56168509 # Number of ops (including micro ops) simulated +host_inst_rate 159928 # Simulator instruction rate (inst/s) +host_op_rate 159928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5430263290 # Simulator tick rate (ticks/s) +host_mem_usage 337712 # Number of bytes of host memory used +host_seconds 351.30 # Real time elapsed on the host +sim_insts 56183395 # Number of instructions simulated +sim_ops 56183395 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 873216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24648192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 103232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 582976 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 861632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24651584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 117952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 582656 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26208576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 873216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 103232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7849920 # Number of bytes written to this memory -system.physmem.bytes_written::total 7849920 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13644 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385128 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9109 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26214784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 861632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 117952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 979584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7845056 # Number of bytes written to this memory +system.physmem.bytes_written::total 7845056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1843 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9104 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 409509 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122655 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122655 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 457504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12913926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 305439 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 409606 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122579 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122579 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 451667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12922338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 61830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 305428 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13731458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457504 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 511590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4112808 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4112808 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4112808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12913926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 305439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13741766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 451667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 61830 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4112371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4112371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4112371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 451667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12922338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 61830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 305428 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17844266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 409509 # Number of read requests accepted -system.physmem.writeReqs 122655 # Number of write requests accepted -system.physmem.readBursts 409509 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122655 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26200320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue -system.physmem.bytesWritten 7848512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26208576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7849920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17854137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 409606 # Number of read requests accepted +system.physmem.writeReqs 122579 # Number of write requests accepted +system.physmem.readBursts 409606 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122579 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26206336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7843200 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26214784 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7845056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25687 # Per bank write bursts -system.physmem.perBankRdBursts::1 26129 # Per bank write bursts -system.physmem.perBankRdBursts::2 25602 # Per bank write bursts -system.physmem.perBankRdBursts::3 25363 # Per bank write bursts -system.physmem.perBankRdBursts::4 24824 # Per bank write bursts -system.physmem.perBankRdBursts::5 25086 # Per bank write bursts -system.physmem.perBankRdBursts::6 25117 # Per bank write bursts -system.physmem.perBankRdBursts::7 24738 # Per bank write bursts -system.physmem.perBankRdBursts::8 25651 # Per bank write bursts -system.physmem.perBankRdBursts::9 26257 # Per bank write bursts -system.physmem.perBankRdBursts::10 25842 # Per bank write bursts -system.physmem.perBankRdBursts::11 26258 # Per bank write bursts -system.physmem.perBankRdBursts::12 25994 # Per bank write bursts -system.physmem.perBankRdBursts::13 25940 # Per bank write bursts -system.physmem.perBankRdBursts::14 25679 # Per bank write bursts -system.physmem.perBankRdBursts::15 25213 # Per bank write bursts -system.physmem.perBankWrBursts::0 7897 # Per bank write bursts -system.physmem.perBankWrBursts::1 8119 # Per bank write bursts -system.physmem.perBankWrBursts::2 8345 # Per bank write bursts -system.physmem.perBankWrBursts::3 7678 # Per bank write bursts -system.physmem.perBankWrBursts::4 7188 # Per bank write bursts -system.physmem.perBankWrBursts::5 7302 # Per bank write bursts -system.physmem.perBankWrBursts::6 7389 # Per bank write bursts -system.physmem.perBankWrBursts::7 6798 # Per bank write bursts -system.physmem.perBankWrBursts::8 7376 # Per bank write bursts -system.physmem.perBankWrBursts::9 7907 # Per bank write bursts -system.physmem.perBankWrBursts::10 7738 # Per bank write bursts -system.physmem.perBankWrBursts::11 7709 # Per bank write bursts -system.physmem.perBankWrBursts::12 7797 # Per bank write bursts -system.physmem.perBankWrBursts::13 7971 # Per bank write bursts -system.physmem.perBankWrBursts::14 7878 # Per bank write bursts -system.physmem.perBankWrBursts::15 7541 # Per bank write bursts +system.physmem.perBankRdBursts::0 26087 # Per bank write bursts +system.physmem.perBankRdBursts::1 25986 # Per bank write bursts +system.physmem.perBankRdBursts::2 25681 # Per bank write bursts +system.physmem.perBankRdBursts::3 25351 # Per bank write bursts +system.physmem.perBankRdBursts::4 24681 # Per bank write bursts +system.physmem.perBankRdBursts::5 24934 # Per bank write bursts +system.physmem.perBankRdBursts::6 25045 # Per bank write bursts +system.physmem.perBankRdBursts::7 25140 # Per bank write bursts +system.physmem.perBankRdBursts::8 25540 # Per bank write bursts +system.physmem.perBankRdBursts::9 26037 # Per bank write bursts +system.physmem.perBankRdBursts::10 25956 # Per bank write bursts +system.physmem.perBankRdBursts::11 25606 # Per bank write bursts +system.physmem.perBankRdBursts::12 26142 # Per bank write bursts +system.physmem.perBankRdBursts::13 25795 # Per bank write bursts +system.physmem.perBankRdBursts::14 25668 # Per bank write bursts +system.physmem.perBankRdBursts::15 25825 # Per bank write bursts +system.physmem.perBankWrBursts::0 8182 # Per bank write bursts +system.physmem.perBankWrBursts::1 8217 # Per bank write bursts +system.physmem.perBankWrBursts::2 8055 # Per bank write bursts +system.physmem.perBankWrBursts::3 7694 # Per bank write bursts +system.physmem.perBankWrBursts::4 7332 # Per bank write bursts +system.physmem.perBankWrBursts::5 7389 # Per bank write bursts +system.physmem.perBankWrBursts::6 7497 # Per bank write bursts +system.physmem.perBankWrBursts::7 6907 # Per bank write bursts +system.physmem.perBankWrBursts::8 7336 # Per bank write bursts +system.physmem.perBankWrBursts::9 7821 # Per bank write bursts +system.physmem.perBankWrBursts::10 7658 # Per bank write bursts +system.physmem.perBankWrBursts::11 7295 # Per bank write bursts +system.physmem.perBankWrBursts::12 7753 # Per bank write bursts +system.physmem.perBankWrBursts::13 7589 # Per bank write bursts +system.physmem.perBankWrBursts::14 7825 # Per bank write bursts +system.physmem.perBankWrBursts::15 8000 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 13 # Number of times write queue was full causing retry -system.physmem.totGap 1908647739500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 1907667754500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 409509 # Read request sizes (log2) +system.physmem.readPktSize::6 409606 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122655 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24859 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122579 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24690 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 78 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see @@ -159,208 +159,193 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.314006 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.672506 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.720496 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14759 22.81% 22.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11414 17.64% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5700 8.81% 49.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2716 4.20% 53.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2485 3.84% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1481 2.29% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1583 2.45% 62.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1463 2.26% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23092 35.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64693 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5538 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.921271 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2818.439252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5535 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.308617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.463735 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.737705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14846 22.95% 22.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11278 17.43% 40.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5774 8.92% 49.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2666 4.12% 53.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2483 3.84% 57.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1468 2.27% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1658 2.56% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1459 2.26% 64.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23063 35.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64695 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5527 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.082685 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2821.240872 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5524 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5538 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5538 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.143915 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.892939 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.348287 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4779 86.29% 86.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 158 2.85% 89.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.29% 89.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 27 0.49% 89.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 200 3.61% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 23 0.42% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 15 0.27% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.13% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 3 0.05% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.11% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 11 0.20% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.13% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 10 0.18% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 30 0.54% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.04% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 13 0.23% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 169 3.05% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 7 0.13% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.04% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 12 0.22% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 9 0.16% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5538 # Writes before turning the bus around for reads -system.physmem.totQLat 3969590750 # Total ticks spent queuing -system.physmem.totMemAccLat 11645465750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2046900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9696.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5527 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5527 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.172969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.909622 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.446069 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4919 89.00% 89.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 36 0.65% 89.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 243 4.40% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 19 0.34% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 15 0.27% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 14 0.25% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 36 0.65% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 13 0.24% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 182 3.29% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.05% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.07% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.05% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 5 0.09% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.07% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 12 0.22% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5527 # Writes before turning the bus around for reads +system.physmem.totQLat 3957301251 # Total ticks spent queuing +system.physmem.totMemAccLat 11634938751 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2047370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9664.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28446.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28414.35 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.74 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.74 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing -system.physmem.readRowHits 368832 # Number of row buffer hits during reads -system.physmem.writeRowHits 98488 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.30 # Row buffer hit rate for writes -system.physmem.avgGap 3586578.08 # Average gap between requests +system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing +system.physmem.readRowHits 368811 # Number of row buffer hits during reads +system.physmem.writeRowHits 98518 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.37 # Row buffer hit rate for writes +system.physmem.avgGap 3584595.12 # Average gap between requests system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244233360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133262250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 393439680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57966073335 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1094343472500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1279324161285 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.276452 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1820370973000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63734060000 # Time in different power states +system.physmem_0.actEnergy 244392120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133348875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1582659000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 397049040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124599742800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57755737350 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1093939329000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278652258185 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.268952 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1819699135250 # Time in different power states +system.physmem_0.memoryStateTime::REF 63701300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24546489500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24270006000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244845720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133596375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1613305200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401222160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57268583145 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1094955297750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1279280671710 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.253671 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1821389841500 # Time in different power states -system.physmem_1.memoryStateTime::REF 63734060000 # Time in different power states +system.physmem_1.actEnergy 244702080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133518000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1611238200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397074960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124599742800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57480963435 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1094180367000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278647606475 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.266509 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1820097449251 # Time in different power states +system.physmem_1.memoryStateTime::REF 63701300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23527607250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23871705749 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 18555851 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15805635 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 543843 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 11677993 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5178603 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 18486901 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15748793 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 541835 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 11639433 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5170762 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.344974 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1050126 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 41449 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5562960 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 527221 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 5035739 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 249629 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.424518 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 1045004 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 41208 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5538250 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 525213 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 5013037 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 248456 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 10426157 # DTB read hits -system.cpu0.dtb.read_misses 39598 # DTB read misses -system.cpu0.dtb.read_acv 591 # DTB read access violations -system.cpu0.dtb.read_accesses 665311 # DTB read accesses -system.cpu0.dtb.write_hits 6323119 # DTB write hits -system.cpu0.dtb.write_misses 9829 # DTB write misses -system.cpu0.dtb.write_acv 421 # DTB write access violations -system.cpu0.dtb.write_accesses 221072 # DTB write accesses -system.cpu0.dtb.data_hits 16749276 # DTB hits -system.cpu0.dtb.data_misses 49427 # DTB misses -system.cpu0.dtb.data_acv 1012 # DTB access violations -system.cpu0.dtb.data_accesses 886383 # DTB accesses -system.cpu0.itb.fetch_hits 1503637 # ITB hits -system.cpu0.itb.fetch_misses 7915 # ITB misses -system.cpu0.itb.fetch_acv 722 # ITB acv -system.cpu0.itb.fetch_accesses 1511552 # ITB accesses +system.cpu0.dtb.read_hits 10388247 # DTB read hits +system.cpu0.dtb.read_misses 39745 # DTB read misses +system.cpu0.dtb.read_acv 614 # DTB read access violations +system.cpu0.dtb.read_accesses 666259 # DTB read accesses +system.cpu0.dtb.write_hits 6304219 # DTB write hits +system.cpu0.dtb.write_misses 9494 # DTB write misses +system.cpu0.dtb.write_acv 419 # DTB write access violations +system.cpu0.dtb.write_accesses 221498 # DTB write accesses +system.cpu0.dtb.data_hits 16692466 # DTB hits +system.cpu0.dtb.data_misses 49239 # DTB misses +system.cpu0.dtb.data_acv 1033 # DTB access violations +system.cpu0.dtb.data_accesses 887757 # DTB accesses +system.cpu0.itb.fetch_hits 1498511 # ITB hits +system.cpu0.itb.fetch_misses 7842 # ITB misses +system.cpu0.itb.fetch_acv 715 # ITB acv +system.cpu0.itb.fetch_accesses 1506353 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -373,605 +358,606 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12751 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 289891468.868256 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 443092480.248663 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 12731 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6366 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 290215354.618913 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 443182270.048279 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::underflows 4 0.06% 0.06% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6372 99.94% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6362 99.94% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 60304082496 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1848348005504 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 120614537 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6366 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 60161154996 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847510947504 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 120328672 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 28910287 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 80847463 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 18555851 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6755950 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 84571652 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1544806 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 27521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 158722 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 425179 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 9281945 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 366954 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 114866072 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.703841 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.035887 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 28758768 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 80605672 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 18486901 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6740979 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 84470777 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1538724 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 99 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 156668 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 425628 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 282 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 9251036 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 365043 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 114609928 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.703304 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.035053 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 99921621 86.99% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 978753 0.85% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2003703 1.74% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 871619 0.76% 90.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2763119 2.41% 92.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 643273 0.56% 93.31% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 756873 0.66% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 980520 0.85% 94.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5946591 5.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 99708886 87.00% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 974143 0.85% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1998972 1.74% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 868407 0.76% 90.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2758687 2.41% 92.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 641235 0.56% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 755467 0.66% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 978409 0.85% 94.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5925722 5.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 114866072 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.153844 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.670296 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 23249023 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 79273649 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9681952 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1921768 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 739679 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 692177 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 33362 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 69931495 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 102843 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 739679 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24188488 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 52133494 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18507080 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10598824 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8698505 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 67143844 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 198929 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2037542 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 235156 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4634826 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 45210033 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 80787031 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 80633489 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 143553 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36399823 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8810210 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1599007 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 262557 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 13124305 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10911287 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6742479 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1608349 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1040811 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 59252141 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2087306 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 57311786 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 84500 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10900957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4754694 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1456877 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 114866072 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.498944 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.243932 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 114609928 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.153637 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.669879 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23115734 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 79187494 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9649471 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1920435 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 736793 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 689182 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33223 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 69733339 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 101960 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 736793 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24053074 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 52045501 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18448869 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10567955 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8757734 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 66954427 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 200777 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2040075 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 234878 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4698433 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 45085797 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 80572701 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 80419250 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 143477 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36303569 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8782228 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1592248 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 261178 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 13101083 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10872978 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6724173 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1603556 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1060240 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 59089633 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2074933 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 57153011 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 84826 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10861661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4738821 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1447538 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 114609928 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.498674 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.243633 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 91593251 79.74% 79.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9917884 8.63% 88.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4171968 3.63% 92.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2987675 2.60% 94.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 3091850 2.69% 97.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1551239 1.35% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1031605 0.90% 99.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 391084 0.34% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 129516 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 91405720 79.75% 79.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9883367 8.62% 88.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4163005 3.63% 92.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2977529 2.60% 94.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 3083312 2.69% 97.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1549770 1.35% 98.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1029487 0.90% 99.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 389877 0.34% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 127861 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 114866072 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 114609928 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 177618 15.88% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 580154 51.88% 67.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 360585 32.24% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 177461 15.95% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 577417 51.89% 67.83% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 357940 32.17% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 38999657 68.05% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 59968 0.10% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28473 0.05% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 10921462 19.06% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6423481 11.21% 98.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 873773 1.52% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 38903396 68.07% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60002 0.10% 68.18% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28431 0.05% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 10881663 19.04% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6404122 11.21% 98.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 870425 1.52% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 57311786 # Type of FU issued -system.cpu0.iq.rate 0.475165 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1118357 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019514 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 230030260 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 71938879 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 55311420 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 662241 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 320414 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 300136 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 58069335 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 357492 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 651404 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 57153011 # Type of FU issued +system.cpu0.iq.rate 0.474974 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1112818 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019471 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 229452003 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 71724793 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 55161872 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 661591 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 320309 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 299753 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 57905331 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 357182 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 649944 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2319887 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3968 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19302 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 772094 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2311061 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3974 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19354 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 772397 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18487 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 403076 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18463 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 400325 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 739679 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 48919856 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 836899 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 65195890 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 175652 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10911287 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6742479 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1850250 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42611 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 592619 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19302 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 209624 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 584555 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 794179 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 56526207 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 10495265 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 785579 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 736793 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 48901711 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 778245 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 65010536 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 175759 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10872978 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6724173 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1839088 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 42617 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 533932 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19354 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 209386 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 582195 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 791581 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 56370431 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 10457447 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 782580 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3856443 # number of nop insts executed -system.cpu0.iew.exec_refs 16847340 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8962761 # Number of branches executed -system.cpu0.iew.exec_stores 6352075 # Number of stores executed -system.cpu0.iew.exec_rate 0.468652 # Inst execution rate -system.cpu0.iew.wb_sent 55828896 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 55611556 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 28259375 # num instructions producing a value -system.cpu0.iew.wb_consumers 39130384 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.461068 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.722185 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 11491140 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 630429 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 709660 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112872616 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.474349 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.409733 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3845970 # number of nop insts executed +system.cpu0.iew.exec_refs 16790279 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8937296 # Number of branches executed +system.cpu0.iew.exec_stores 6332832 # Number of stores executed +system.cpu0.iew.exec_rate 0.468470 # Inst execution rate +system.cpu0.iew.wb_sent 55678100 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 55461625 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 28192926 # num instructions producing a value +system.cpu0.iew.wb_consumers 39039520 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.460918 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.722164 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 11448425 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 627395 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 706831 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112623597 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.474128 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.409611 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 93942624 83.23% 83.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7580066 6.72% 89.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4021065 3.56% 93.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2150933 1.91% 95.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1669707 1.48% 96.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 619428 0.55% 97.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 456360 0.40% 97.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 507616 0.45% 98.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1924817 1.71% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 93749029 83.24% 83.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7554104 6.71% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4011836 3.56% 93.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2145505 1.91% 95.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1663134 1.48% 96.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 616876 0.55% 97.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 455080 0.40% 97.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 507934 0.45% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1920099 1.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112872616 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53540971 # Number of instructions committed -system.cpu0.commit.committedOps 53540971 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112623597 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 53398017 # Number of instructions committed +system.cpu0.commit.committedOps 53398017 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14561785 # Number of memory references committed -system.cpu0.commit.loads 8591400 # Number of loads committed -system.cpu0.commit.membars 215482 # Number of memory barriers committed -system.cpu0.commit.branches 8090306 # Number of branches committed -system.cpu0.commit.fp_insts 289534 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49542263 # Number of committed integer instructions. -system.cpu0.commit.function_calls 699437 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 3105795 5.80% 5.80% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 34689949 64.79% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 58544 0.11% 70.70% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28001 0.05% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8806882 16.45% 87.21% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5976371 11.16% 98.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 873773 1.63% 100.00% # Class of committed instruction +system.cpu0.commit.refs 14513693 # Number of memory references committed +system.cpu0.commit.loads 8561917 # Number of loads committed +system.cpu0.commit.membars 214579 # Number of memory barriers committed +system.cpu0.commit.branches 8068022 # Number of branches committed +system.cpu0.commit.fp_insts 288973 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49410509 # Number of committed integer instructions. +system.cpu0.commit.function_calls 696168 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 3098426 5.80% 5.80% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 34606705 64.81% 70.61% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 58588 0.11% 70.72% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.72% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 27960 0.05% 70.77% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.77% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.77% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.77% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.78% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8776496 16.44% 87.21% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5957761 11.16% 98.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 870425 1.63% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 53540971 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1924817 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 175788251 # The number of ROB reads -system.cpu0.rob.rob_writes 132059822 # The number of ROB writes -system.cpu0.timesIdled 545123 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5748465 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3696064399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50438489 # Number of Instructions Simulated -system.cpu0.committedOps 50438489 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.391319 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.391319 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.418179 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.418179 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 73773620 # number of integer regfile reads -system.cpu0.int_regfile_writes 40428970 # number of integer regfile writes -system.cpu0.fp_regfile_reads 142673 # number of floating regfile reads -system.cpu0.fp_regfile_writes 153221 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1866400 # number of misc regfile reads -system.cpu0.misc_regfile_writes 877434 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1337856 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.906059 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11855471 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1338256 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.858896 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 53398017 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1920099 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 175358628 # The number of ROB reads +system.cpu0.rob.rob_writes 131681344 # The number of ROB writes +system.cpu0.timesIdled 541437 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5718744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3694399415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 50302904 # Number of Instructions Simulated +system.cpu0.committedOps 50302904 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.392082 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.392082 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.418046 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.418046 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 73576817 # number of integer regfile reads +system.cpu0.int_regfile_writes 40321383 # number of integer regfile writes +system.cpu0.fp_regfile_reads 142542 # number of floating regfile reads +system.cpu0.fp_regfile_writes 152983 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1859375 # number of misc regfile reads +system.cpu0.misc_regfile_writes 873240 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1336574 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.845930 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11809421 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1336976 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.832934 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.906059 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988098 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988098 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62973100 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62973100 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 7528886 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7528886 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3919891 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3919891 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 201495 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 201495 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 204000 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 204000 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11448777 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11448777 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11448777 # number of overall hits -system.cpu0.dcache.overall_hits::total 11448777 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1699683 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1699683 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1831149 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1831149 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21973 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21973 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 873 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 873 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3530832 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3530832 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3530832 # number of overall misses -system.cpu0.dcache.overall_misses::total 3530832 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40671315500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40671315500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77312811875 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77312811875 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331728000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 331728000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6457500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 6457500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117984127375 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117984127375 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117984127375 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117984127375 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 9228569 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9228569 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5751040 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5751040 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223468 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 223468 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 204873 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 204873 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14979609 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14979609 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14979609 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14979609 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184176 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.184176 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318403 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.318403 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098327 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098327 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004261 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004261 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.235709 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.235709 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.235709 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.235709 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23928.765246 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23928.765246 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.928977 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42220.928977 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15097.073681 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15097.073681 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7396.907216 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7396.907216 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33415.389737 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33415.389737 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4312836 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 8080 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 119422 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 127 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.114250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 63.622047 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 792748 # number of writebacks -system.cpu0.dcache.writebacks::total 792748 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 643460 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 643460 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1557660 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1557660 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6525 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6525 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2201120 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2201120 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2201120 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2201120 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1056223 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1056223 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273489 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 273489 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15448 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15448 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 873 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 873 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1329712 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1329712 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1329712 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1329712 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7053 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7053 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9807 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9807 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16860 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16860 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30297527500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30297527500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12178891856 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12178891856 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 190480500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 190480500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5584500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5584500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42476419356 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 42476419356 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42476419356 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 42476419356 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1570178500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1570178500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1570178500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1570178500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047555 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047555 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069128 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.069128 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004261 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004261 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.088768 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.088768 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28684.782948 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28684.782948 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44531.560158 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44531.560158 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12330.431124 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.431124 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6396.907216 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6396.907216 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222625.620303 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222625.620303 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93130.397390 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93130.397390 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1021310 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.519684 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 8197716 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1021822 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.022646 # Average number of references to valid blocks. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.845930 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.987980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 62763513 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 62763513 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 7501117 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7501117 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3904271 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3904271 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 200075 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 200075 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 202804 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 202804 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11405388 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11405388 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11405388 # number of overall hits +system.cpu0.dcache.overall_hits::total 11405388 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1695209 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1695209 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1829361 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1829361 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22067 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22067 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 927 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 927 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3524570 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3524570 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3524570 # number of overall misses +system.cpu0.dcache.overall_misses::total 3524570 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40549578500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40549578500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77276130293 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77276130293 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333041000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 333041000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6753500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 6753500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117825708793 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117825708793 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117825708793 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117825708793 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9196326 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9196326 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5733632 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5733632 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 222142 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 222142 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 203731 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 203731 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14929958 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14929958 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14929958 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14929958 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184335 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.184335 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.319058 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.319058 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.099337 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.099337 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004550 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004550 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236074 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.236074 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236074 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.236074 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23920.105721 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23920.105721 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42242.143728 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42242.143728 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15092.264467 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15092.264467 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7285.329018 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7285.329018 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33429.810954 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33429.810954 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33429.810954 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33429.810954 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4313991 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 8795 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119168 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 132 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.200918 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 66.628788 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 791920 # number of writebacks +system.cpu0.dcache.writebacks::total 791920 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 639925 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 639925 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1556053 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1556053 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6507 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6507 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2195978 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2195978 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2195978 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2195978 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1055284 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1055284 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273308 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 273308 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15560 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15560 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 926 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 926 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1328592 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1328592 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1328592 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1328592 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7032 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7032 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9755 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9755 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16787 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16787 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30284931500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30284931500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12180596213 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12180596213 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 192236000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 192236000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5827500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5827500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42465527713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 42465527713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42465527713 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 42465527713 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566422000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566422000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566422000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566422000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114751 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114751 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047668 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047668 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.070045 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.070045 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004545 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004545 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088988 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.088988 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088988 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.088988 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28698.370770 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28698.370770 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44567.287503 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44567.287503 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12354.498715 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12354.498715 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6293.196544 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6293.196544 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31962.805521 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31962.805521 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31962.805521 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31962.805521 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222756.257110 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222756.257110 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93311.610175 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93311.610175 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1014611 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.545427 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 8173897 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1015123 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.052125 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 28452447500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.519684 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995156 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995156 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.545427 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995206 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995206 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 10303980 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 10303980 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 8197716 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 8197716 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 8197716 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 8197716 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 8197716 # number of overall hits -system.cpu0.icache.overall_hits::total 8197716 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1084226 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1084226 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1084226 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1084226 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1084226 # number of overall misses -system.cpu0.icache.overall_misses::total 1084226 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15369093993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 15369093993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 15369093993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 15369093993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 15369093993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 15369093993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 9281942 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 9281942 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 9281942 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 9281942 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 9281942 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 9281942 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116810 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116810 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116810 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116810 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116810 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116810 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.175649 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.175649 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14175.175649 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14175.175649 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5565 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 10266395 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 10266395 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 8173897 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 8173897 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 8173897 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 8173897 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 8173897 # number of overall hits +system.cpu0.icache.overall_hits::total 8173897 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1077136 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1077136 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1077136 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1077136 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1077136 # number of overall misses +system.cpu0.icache.overall_misses::total 1077136 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15255278493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 15255278493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 15255278493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 15255278493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 15255278493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 15255278493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 9251033 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 9251033 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 9251033 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 9251033 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 9251033 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 9251033 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116434 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116434 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116434 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116434 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116434 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116434 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14162.815553 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14162.815553 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14162.815553 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14162.815553 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14162.815553 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14162.815553 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5826 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 223 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 231 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.955157 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.220779 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1021310 # number of writebacks -system.cpu0.icache.writebacks::total 1021310 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 62188 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 62188 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 62188 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 62188 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 62188 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 62188 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1022038 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1022038 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1022038 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1022038 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1022038 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1022038 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13659780995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13659780995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13659780995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13659780995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13659780995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13659780995 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110110 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.110110 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.110110 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13365.237883 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency -system.cpu1.branchPred.lookups 2642221 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2286827 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 62241 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1292185 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 477042 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 1014611 # number of writebacks +system.cpu0.icache.writebacks::total 1014611 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 61774 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 61774 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 61774 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 61774 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 61774 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 61774 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1015362 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1015362 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1015362 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1015362 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1015362 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1015362 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13566878495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13566878495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13566878495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13566878495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13566878495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13566878495 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109757 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.109757 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.109757 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13361.617330 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13361.617330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13361.617330 # average overall mshr miss latency +system.cpu1.branchPred.lookups 2716012 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2349135 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 64284 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1339574 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 486642 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.917469 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 126491 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4205 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 709163 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 105030 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 604133 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 17634 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 36.328116 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 131116 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4300 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 740387 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 107863 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 632524 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 18463 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1454361 # DTB read hits -system.cpu1.dtb.read_misses 11674 # DTB read misses -system.cpu1.dtb.read_acv 55 # DTB read access violations -system.cpu1.dtb.read_accesses 336696 # DTB read accesses -system.cpu1.dtb.write_hits 804644 # DTB write hits -system.cpu1.dtb.write_misses 2787 # DTB write misses +system.cpu1.dtb.read_hits 1491854 # DTB read hits +system.cpu1.dtb.read_misses 11707 # DTB read misses +system.cpu1.dtb.read_acv 49 # DTB read access violations +system.cpu1.dtb.read_accesses 336889 # DTB read accesses +system.cpu1.dtb.write_hits 824931 # DTB write hits +system.cpu1.dtb.write_misses 2806 # DTB write misses system.cpu1.dtb.write_acv 46 # DTB write access violations -system.cpu1.dtb.write_accesses 125975 # DTB write accesses -system.cpu1.dtb.data_hits 2259005 # DTB hits -system.cpu1.dtb.data_misses 14461 # DTB misses -system.cpu1.dtb.data_acv 101 # DTB access violations -system.cpu1.dtb.data_accesses 462671 # DTB accesses -system.cpu1.itb.fetch_hits 472443 # ITB hits -system.cpu1.itb.fetch_misses 2661 # ITB misses -system.cpu1.itb.fetch_acv 95 # ITB acv -system.cpu1.itb.fetch_accesses 475104 # ITB accesses +system.cpu1.dtb.write_accesses 126281 # DTB write accesses +system.cpu1.dtb.data_hits 2316785 # DTB hits +system.cpu1.dtb.data_misses 14513 # DTB misses +system.cpu1.dtb.data_acv 95 # DTB access violations +system.cpu1.dtb.data_accesses 463170 # DTB accesses +system.cpu1.itb.fetch_hits 477856 # ITB hits +system.cpu1.itb.fetch_misses 2662 # ITB misses +system.cpu1.itb.fetch_acv 96 # ITB acv +system.cpu1.itb.fetch_accesses 480518 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -984,581 +970,580 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 4618 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2309 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 824384353.183196 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 333980461.680684 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2309 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 88500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975572500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2309 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 5148616500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1903503471500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 10299543 # number of cpu cycles simulated +system.cpu1.numPwrStateTransitions 4646 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2323 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 818936669.177787 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 339506423.560652 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2323 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 975573000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2323 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 5282220000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1902389882500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 10566764 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 3708105 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 10416725 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2642221 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 708563 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 5867887 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 223660 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 23709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 51632 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 40219 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1189367 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 46143 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9803421 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.062560 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.469546 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 3825216 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 10675597 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2716012 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 725621 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 5983543 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 229964 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 23815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 51735 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 41039 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1221851 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 48225 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 10040370 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.063267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.470833 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7976409 81.36% 81.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 98791 1.01% 82.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 205509 2.10% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 143569 1.46% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 244577 2.49% 88.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 96035 0.98% 89.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 110446 1.13% 90.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 69630 0.71% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 858455 8.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 8168289 81.35% 81.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 102687 1.02% 82.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 210133 2.09% 84.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 146343 1.46% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 249317 2.48% 88.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 97935 0.98% 89.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 113554 1.13% 90.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 71548 0.71% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 880564 8.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9803421 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.256538 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.011377 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3120035 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 5128574 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1274002 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 173173 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 107636 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 84669 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4317 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8395667 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13790 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 107636 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3236399 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 505262 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3781107 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1330090 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 842925 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7927045 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 866 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 80988 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18891 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 445625 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 5308652 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9558760 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9526496 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 27580 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4111841 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1196803 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 316905 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22710 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1429971 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1508631 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 873340 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 185286 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 107493 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6977977 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 344578 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6652421 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 19333 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1592530 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 796148 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 266679 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9803421 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.678582 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.403550 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 10040370 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.257033 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.010300 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3212898 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 5233388 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1306839 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 176592 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 110652 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 87490 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4477 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8611500 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 14236 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 110652 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3332108 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 534859 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3861101 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1363516 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 838132 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 8128723 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 840 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 81504 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 20811 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 431912 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 5442265 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9792683 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9760108 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 27875 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4220598 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1221659 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 323796 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 24055 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1462372 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1548375 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 895151 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 190303 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 111620 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 7151730 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 356002 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6823456 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 19520 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1627236 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 806919 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 274884 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 10040370 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.679602 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.404814 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 7053571 71.95% 71.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1194265 12.18% 84.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 509519 5.20% 89.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 375157 3.83% 93.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 322481 3.29% 96.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 169260 1.73% 98.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 99294 1.01% 99.19% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 57333 0.58% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 22541 0.23% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 7219551 71.91% 71.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1226248 12.21% 84.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 523144 5.21% 89.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 383300 3.82% 93.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 329501 3.28% 96.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 173963 1.73% 98.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 102712 1.02% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 58679 0.58% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 23272 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9803421 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 10040370 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24978 11.96% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 116023 55.55% 67.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 67859 32.49% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 25321 11.84% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 118979 55.64% 67.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 69548 32.52% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3973 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 4085085 61.41% 61.47% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10572 0.16% 61.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10292 0.15% 61.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1521104 22.87% 84.68% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 824727 12.40% 97.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 194682 2.93% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 4192346 61.44% 61.50% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10770 0.16% 61.66% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10332 0.15% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1560504 22.87% 84.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 845461 12.39% 97.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 198084 2.90% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6652421 # Type of FU issued -system.cpu1.iq.rate 0.645895 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 208860 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.031396 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 23247701 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8874149 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6353252 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 88754 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 44866 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 42405 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6811194 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 46114 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 75849 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6823456 # Type of FU issued +system.cpu1.iq.rate 0.645747 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 213848 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.031340 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 23830038 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 9093503 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6518367 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 90611 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 45521 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 43008 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6985974 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 47357 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 77493 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 328260 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 949 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4058 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 119869 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 335188 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 932 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4197 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 122462 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 415 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 72546 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 439 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 72925 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 107636 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 325014 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 147509 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7654698 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 36160 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1508631 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 873340 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 319432 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4857 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 141756 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4058 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 24786 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 89639 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 114425 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6540293 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1470121 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 112127 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 110652 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 347034 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 152695 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7850434 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 37055 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1548375 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 895151 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 329794 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4928 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 146829 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4197 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 25483 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 92224 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 117707 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6707770 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1507715 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 115685 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 332143 # number of nop insts executed -system.cpu1.iew.exec_refs 2281164 # number of memory reference insts executed -system.cpu1.iew.exec_branches 956130 # Number of branches executed -system.cpu1.iew.exec_stores 811043 # Number of stores executed -system.cpu1.iew.exec_rate 0.635008 # Inst execution rate -system.cpu1.iew.wb_sent 6430736 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6395657 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3121788 # num instructions producing a value -system.cpu1.iew.wb_consumers 4363189 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.620965 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.715483 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1558734 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 77899 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 97361 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9525282 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.626287 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.584809 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 342702 # number of nop insts executed +system.cpu1.iew.exec_refs 2339108 # number of memory reference insts executed +system.cpu1.iew.exec_branches 982956 # Number of branches executed +system.cpu1.iew.exec_stores 831393 # Number of stores executed +system.cpu1.iew.exec_rate 0.634799 # Inst execution rate +system.cpu1.iew.wb_sent 6597173 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6561375 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3197425 # num instructions producing a value +system.cpu1.iew.wb_consumers 4464974 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.620945 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.716113 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1594434 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 81118 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 100274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9755465 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.627758 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.585985 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 7314942 76.80% 76.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1051446 11.04% 87.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 355573 3.73% 91.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 228997 2.40% 93.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 163534 1.72% 95.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 72316 0.76% 96.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 75781 0.80% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 55973 0.59% 97.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 206720 2.17% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 7484983 76.73% 76.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1079374 11.06% 87.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 367183 3.76% 91.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 234920 2.41% 93.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 168491 1.73% 95.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 74517 0.76% 96.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 76064 0.78% 97.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 56824 0.58% 97.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 213109 2.18% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9525282 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5965556 # Number of instructions committed -system.cpu1.commit.committedOps 5965556 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 9755465 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 6124073 # Number of instructions committed +system.cpu1.commit.committedOps 6124073 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1933842 # Number of memory references committed -system.cpu1.commit.loads 1180371 # Number of loads committed -system.cpu1.commit.membars 21608 # Number of memory barriers committed -system.cpu1.commit.branches 842250 # Number of branches committed -system.cpu1.commit.fp_insts 40666 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5575941 # Number of committed integer instructions. -system.cpu1.commit.function_calls 91630 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 239508 4.01% 4.01% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 3553035 59.56% 63.57% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 10403 0.17% 63.75% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.75% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10285 0.17% 63.92% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.92% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.92% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.92% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.95% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1201979 20.15% 84.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 753678 12.63% 96.74% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 194682 3.26% 100.00% # Class of committed instruction +system.cpu1.commit.refs 1985876 # Number of memory references committed +system.cpu1.commit.loads 1213187 # Number of loads committed +system.cpu1.commit.membars 22586 # Number of memory barriers committed +system.cpu1.commit.branches 866488 # Number of branches committed +system.cpu1.commit.fp_insts 41227 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5722327 # Number of committed integer instructions. +system.cpu1.commit.function_calls 95129 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 247554 4.04% 4.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 3646853 59.55% 63.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 10597 0.17% 63.76% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.76% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10326 0.17% 63.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.97% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1235773 20.18% 84.14% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 772900 12.62% 96.77% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 198084 3.23% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 5965556 # Class of committed instruction -system.cpu1.commit.bw_lim_events 206720 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 16752551 # The number of ROB reads -system.cpu1.rob.rob_writes 15324043 # The number of ROB writes -system.cpu1.timesIdled 69166 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 496122 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3807004634 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5730020 # Number of Instructions Simulated -system.cpu1.committedOps 5730020 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.797471 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.797471 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556337 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556337 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8470716 # number of integer regfile reads -system.cpu1.int_regfile_writes 4619691 # number of integer regfile writes -system.cpu1.fp_regfile_reads 26922 # number of floating regfile reads -system.cpu1.fp_regfile_writes 25344 # number of floating regfile writes -system.cpu1.misc_regfile_reads 302216 # number of misc regfile reads -system.cpu1.misc_regfile_writes 137559 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 64410 # number of replacements -system.cpu1.dcache.tags.tagsinuse 463.614906 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1794834 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 64922 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.646006 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1880101020500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.614906 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905498 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.905498 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 6124073 # Class of committed instruction +system.cpu1.commit.bw_lim_events 213109 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 17170417 # The number of ROB reads +system.cpu1.rob.rob_writes 15719262 # The number of ROB writes +system.cpu1.timesIdled 71397 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 526394 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3804777442 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5880491 # Number of Instructions Simulated +system.cpu1.committedOps 5880491 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.796919 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.796919 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556508 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556508 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8685381 # number of integer regfile reads +system.cpu1.int_regfile_writes 4740732 # number of integer regfile writes +system.cpu1.fp_regfile_reads 27201 # number of floating regfile reads +system.cpu1.fp_regfile_writes 25643 # number of floating regfile writes +system.cpu1.misc_regfile_reads 310247 # number of misc regfile reads +system.cpu1.misc_regfile_writes 141917 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 65099 # number of replacements +system.cpu1.dcache.tags.tagsinuse 463.722972 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1848833 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 65611 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.178705 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1879972526500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.722972 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905709 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.905709 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 8336582 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 8336582 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1188882 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1188882 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 570377 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 570377 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16198 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16198 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15147 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15147 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1759259 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1759259 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1759259 # number of overall hits -system.cpu1.dcache.overall_hits::total 1759259 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 111545 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 111545 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 161954 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 161954 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1739 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1739 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 840 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 840 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 273499 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 273499 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 273499 # number of overall misses -system.cpu1.dcache.overall_misses::total 273499 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1447207500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1447207500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7450335261 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7450335261 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 18882500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 18882500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6469000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 6469000 # number of StoreCondReq miss cycles +system.cpu1.dcache.tags.tag_accesses 8556411 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 8556411 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1222356 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1222356 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 588321 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 588321 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 17437 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 17437 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 16296 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 16296 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1810677 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1810677 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1810677 # number of overall hits +system.cpu1.dcache.overall_hits::total 1810677 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 112363 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 112363 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 161965 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 161965 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1793 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1793 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 891 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 891 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 274328 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 274328 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 274328 # number of overall misses +system.cpu1.dcache.overall_misses::total 274328 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1482127500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1482127500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7331574147 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7331574147 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19537500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 19537500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6718500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6718500 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 34500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 34500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8897542761 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8897542761 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8897542761 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8897542761 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1300427 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1300427 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 732331 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 732331 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 17937 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 17937 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15987 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15987 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2032758 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2032758 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2032758 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2032758 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.085776 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.085776 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221149 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.221149 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.096950 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.096950 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.052543 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.052543 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134546 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134546 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134546 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134546 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12974.203236 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12974.203236 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46002.786353 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 46002.786353 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10858.251869 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10858.251869 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7701.190476 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7701.190476 # average StoreCondReq miss latency +system.cpu1.dcache.demand_miss_latency::cpu1.data 8813701647 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8813701647 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8813701647 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8813701647 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1334719 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1334719 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 750286 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 750286 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 19230 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 19230 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 17187 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 17187 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2085005 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2085005 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2085005 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2085005 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.084185 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.084185 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.215871 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.215871 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093240 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093240 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.051842 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.051842 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131572 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.131572 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131572 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.131572 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13190.529801 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13190.529801 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 45266.410317 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 45266.410317 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10896.542108 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10896.542108 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7540.404040 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7540.404040 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32532.267983 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32532.267983 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32532.267983 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32532.267983 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 463151 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 490 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15628 # number of cycles access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32128.334137 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 32128.334137 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32128.334137 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 32128.334137 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 454264 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 482 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 15527 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.635974 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 49 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 38002 # number of writebacks -system.cpu1.dcache.writebacks::total 38002 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 65961 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 65961 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137427 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 137427 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 372 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 372 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 203388 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 203388 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 203388 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 203388 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 45584 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 45584 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24527 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 24527 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1367 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1367 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 840 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 840 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 70111 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 70111 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 70111 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 70111 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 146 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 146 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2584 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2584 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 2730 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 2730 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 575200000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 575200000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1170679567 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1170679567 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13141000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13141000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5630000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5630000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.256392 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 48.200000 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 38456 # number of writebacks +system.cpu1.dcache.writebacks::total 38456 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66033 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 66033 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137281 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 137281 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 379 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 379 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 203314 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 203314 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 203314 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 203314 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 46330 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 46330 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24684 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 24684 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1414 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1414 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 891 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 891 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 71014 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 71014 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 71014 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 71014 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2639 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2639 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 2801 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 2801 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 590183000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 590183000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1153615997 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1153615997 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13566500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13566500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5828500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5828500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 33500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 33500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1745879567 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1745879567 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1745879567 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1745879567 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29635500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29635500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 29635500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 29635500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035053 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035053 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033492 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033492 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076211 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076211 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.052543 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.052543 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034491 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034491 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.462618 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12618.462618 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47730.238798 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47730.238798 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9613.021214 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9613.021214 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6702.380952 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6702.380952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1743798997 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1743798997 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1743798997 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1743798997 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32350500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32350500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32350500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32350500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034711 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034711 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032899 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032899 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073531 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073531 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.051842 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.051842 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034059 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034059 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034059 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034059 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12738.679042 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12738.679042 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46735.375020 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46735.375020 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9594.413013 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9594.413013 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6541.526375 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6541.526375 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202982.876712 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202982.876712 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10855.494505 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10855.494505 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 125381 # number of replacements -system.cpu1.icache.tags.tagsinuse 466.454678 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1056750 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 125892 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.394100 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880706304500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.454678 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911044 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.911044 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1315314 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1315314 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1056751 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1056751 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1056751 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1056751 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1056751 # number of overall hits -system.cpu1.icache.overall_hits::total 1056751 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 132616 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 132616 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 132616 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 132616 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 132616 # number of overall misses -system.cpu1.icache.overall_misses::total 132616 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1887030000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1887030000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1887030000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1887030000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1887030000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1887030000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1189367 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1189367 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1189367 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1189367 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1189367 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1189367 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111501 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.111501 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111501 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.111501 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111501 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.111501 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14229.278518 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14229.278518 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14229.278518 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14229.278518 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24555.707283 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24555.707283 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24555.707283 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24555.707283 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199694.444444 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 199694.444444 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11549.625134 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11549.625134 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 129926 # number of replacements +system.cpu1.icache.tags.tagsinuse 466.448190 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1084325 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 130435 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.313144 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880575078500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.448190 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911032 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.911032 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 419 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1352346 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1352346 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1084325 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1084325 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1084325 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1084325 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1084325 # number of overall hits +system.cpu1.icache.overall_hits::total 1084325 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 137526 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 137526 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 137526 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 137526 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 137526 # number of overall misses +system.cpu1.icache.overall_misses::total 137526 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1969078999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1969078999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1969078999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1969078999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1969078999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1969078999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1221851 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1221851 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1221851 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1221851 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1221851 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1221851 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112555 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112555 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112555 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14317.867160 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14317.867160 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14317.867160 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14317.867160 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14317.867160 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14317.867160 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.193548 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.400000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 125381 # number of writebacks -system.cpu1.icache.writebacks::total 125381 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6669 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6669 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6669 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6669 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6669 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6669 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 125947 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 125947 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 125947 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 125947 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 125947 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 125947 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1682313500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1682313500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1682313500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1682313500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1682313500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1682313500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105894 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.105894 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.105894 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.312997 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 129926 # number of writebacks +system.cpu1.icache.writebacks::total 129926 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7031 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7031 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7031 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7031 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7031 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7031 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 130495 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 130495 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 130495 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 130495 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 130495 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 130495 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1753458499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1753458499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1753458499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1753458499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1753458499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1753458499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106801 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.106801 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.106801 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13436.978421 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13436.978421 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13436.978421 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1571,101 +1556,101 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7381 # Transaction distribution -system.iobus.trans_dist::ReadResp 7381 # Transaction distribution -system.iobus.trans_dist::WriteReq 53943 # Transaction distribution -system.iobus.trans_dist::WriteResp 53943 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10586 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 7367 # Transaction distribution +system.iobus.trans_dist::ReadResp 7367 # Transaction distribution +system.iobus.trans_dist::WriteReq 53946 # Transaction distribution +system.iobus.trans_dist::WriteResp 53946 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122648 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42344 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122626 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 68539 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661680 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661680 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2730219 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 10864500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68530 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2730138 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 10859000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 814501 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 821000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 178000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14057500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14076000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6034500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6060001 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216209541 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216164058 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26789000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26782000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41964000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41702 # number of replacements -system.iocache.tags.tagsinuse 0.516326 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 41693 # number of replacements +system.iocache.tags.tagsinuse 0.508375 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41718 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712300449000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.516326 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.032270 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.032270 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712300354000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.508375 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031773 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031773 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375606 # Number of tag accesses -system.iocache.tags.data_accesses 375606 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 182 # number of ReadReq misses -system.iocache.ReadReq_misses::total 182 # number of ReadReq misses +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41734 # number of demand (read+write) misses -system.iocache.demand_misses::total 41734 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41734 # number of overall misses -system.iocache.overall_misses::total 41734 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22913883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22913883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4860118658 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4860118658 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4883032541 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4883032541 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4883032541 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4883032541 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 182 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 182 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21862383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21862383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858655675 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858655675 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4880518058 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4880518058 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4880518058 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4880518058 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41734 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41734 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41734 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41734 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1674,38 +1659,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125900.456044 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125900.456044 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116964.734742 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116964.734742 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 117003.703000 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 117003.703000 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 117003.703000 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 117003.703000 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126372.156069 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126372.156069 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116929.526256 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116929.526256 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116968.677244 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116968.677244 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116968.677244 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116968.677244 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 37 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 182 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41734 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41734 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41734 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41734 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13813883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13813883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2780093407 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2780093407 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2793907290 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2793907290 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2793907290 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2793907290 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13212383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13212383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778666661 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2778666661 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2791879044 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2791879044 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2791879044 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2791879044 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1714,464 +1699,463 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75900.456044 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75900.456044 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66906.368093 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66906.368093 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66945.590885 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66945.590885 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 344399 # number of replacements -system.l2c.tags.tagsinuse 65257.528904 # Cycle average of tags in use -system.l2c.tags.total_refs 4049043 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409397 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.890261 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76372.156069 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76372.156069 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.031695 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.031695 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66911.421067 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66911.421067 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66911.421067 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66911.421067 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 344445 # number of replacements +system.l2c.tags.tagsinuse 65257.633522 # Cycle average of tags in use +system.l2c.tags.total_refs 4040340 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 409472 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.867195 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 7589084000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53234.554738 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5306.808814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6471.614757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 207.979433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 36.571163 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.812295 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.098749 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003174 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995751 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64998 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3509 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3235 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6125 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51897 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991791 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38854214 # Number of tag accesses -system.l2c.tags.data_accesses 38854214 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 830750 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 830750 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 873391 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 873391 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 189 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 76 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 265 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 96 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 120 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 167999 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 13850 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 181849 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 1008159 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 124281 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1132440 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 779840 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 40945 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 820785 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 1008159 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 947839 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124281 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 54795 # number of demand (read+write) hits -system.l2c.demand_hits::total 2135074 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 1008159 # number of overall hits -system.l2c.overall_hits::cpu0.data 947839 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124281 # number of overall hits -system.l2c.overall_hits::cpu1.data 54795 # number of overall hits -system.l2c.overall_hits::total 2135074 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2489 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 605 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3094 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 70 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 171 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 111855 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8432 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120287 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13646 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1630 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15276 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 273692 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 770 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 274462 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 13646 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 385547 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1630 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9202 # number of demand (read+write) misses -system.l2c.demand_misses::total 410025 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13646 # number of overall misses -system.l2c.overall_misses::cpu0.data 385547 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1630 # number of overall misses -system.l2c.overall_misses::cpu1.data 9202 # number of overall misses -system.l2c.overall_misses::total 410025 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 1409000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1507500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2916500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 533500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 89500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 623000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9988107000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 962206500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10950313500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1153739000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 140335000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1294074000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 20210786000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 69824500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 20280610500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1153739000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 30198893000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 140335000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1032031000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 32524998000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1153739000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 30198893000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 140335000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1032031000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 32524998000 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 830750 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 830750 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 873391 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 873391 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2678 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 681 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3359 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 166 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 125 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 291 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 279854 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 22282 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 1021805 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 125911 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1147716 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1053532 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 41715 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1095247 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 1021805 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1333386 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 125911 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 63997 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2545099 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 1021805 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1333386 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 125911 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 63997 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2545099 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.929425 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.888399 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.921107 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.421687 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.808000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.587629 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.399691 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.378422 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.398122 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.013355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.012946 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013310 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.259785 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.018459 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.250594 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013355 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.289149 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.012946 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.143788 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.161104 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013355 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.289149 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.012946 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.143788 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.161104 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 566.090800 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2491.735537 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 942.630899 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7621.428571 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 886.138614 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3643.274854 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89295.132091 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 114113.674099 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 91034.887394 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84547.779569 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 86095.092025 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 84712.882954 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73845.000950 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90681.168831 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 73892.234626 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84547.779569 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 78327.397179 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 86095.092025 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 112152.901543 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 79324.426559 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84547.779569 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 78327.397179 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 86095.092025 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 112152.901543 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 79324.426559 # average overall miss latency +system.l2c.tags.occ_blocks::writebacks 53236.660660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5305.017555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6468.149046 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 210.708528 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 37.097733 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.812327 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.098696 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003215 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000566 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995752 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65027 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3644 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2937 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5880 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52328 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.992233 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 38778519 # Number of tag accesses +system.l2c.tags.data_accesses 38778519 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 830376 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 830376 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 866904 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 866904 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 177 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 78 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 255 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 93 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 119 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 167638 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 13954 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 181592 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 1001682 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 128599 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1130281 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 778846 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 41539 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 820385 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 1001682 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 946484 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 128599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 55493 # number of demand (read+write) hits +system.l2c.demand_hits::total 2132258 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 1001682 # number of overall hits +system.l2c.overall_hits::cpu0.data 946484 # number of overall hits +system.l2c.overall_hits::cpu1.inst 128599 # number of overall hits +system.l2c.overall_hits::cpu1.data 55493 # number of overall hits +system.l2c.overall_hits::total 2132258 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2505 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 627 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3132 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 74 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 102 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 176 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 111923 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8380 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120303 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 13465 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1860 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15325 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 273663 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 829 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 274492 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 13465 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 385586 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1860 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9209 # number of demand (read+write) misses +system.l2c.demand_misses::total 410120 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13465 # number of overall misses +system.l2c.overall_misses::cpu0.data 385586 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1860 # number of overall misses +system.l2c.overall_misses::cpu1.data 9209 # number of overall misses +system.l2c.overall_misses::total 410120 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 1461500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1509000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 2970500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 588500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 59000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 647500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9993512000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 942928000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10936440000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1136019500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 157980000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1293999500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 20211623000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 77550000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 20289173000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1136019500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 30205135000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 157980000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1020478000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 32519612500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1136019500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 30205135000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 157980000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1020478000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 32519612500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 830376 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 830376 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 866904 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 866904 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2682 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 705 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3387 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 167 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 128 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 295 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 279561 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 22334 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 301895 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 1015147 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 130459 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1145606 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1052509 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 42368 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1094877 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 1015147 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1332070 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 130459 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 64702 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2542378 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 1015147 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1332070 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 130459 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 64702 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2542378 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934004 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.889362 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.924712 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.443114 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.796875 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.596610 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.400353 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.375213 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.398493 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.013264 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.014257 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013377 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.260010 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.019567 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.250706 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013264 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.289464 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014257 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.142329 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.161314 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013264 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.289464 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014257 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.142329 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.161314 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 583.433134 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2406.698565 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 948.435504 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7952.702703 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 578.431373 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3678.977273 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89289.172020 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112521.241050 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90907.458667 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84368.325288 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84935.483871 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 84437.161501 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73855.884793 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93546.441496 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 73915.352724 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 84368.325288 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 78335.663121 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84935.483871 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 110813.117602 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 79292.920365 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 84368.325288 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 78335.663121 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84935.483871 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 110813.117602 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 79292.920365 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 81135 # number of writebacks -system.l2c.writebacks::total 81135 # number of writebacks -system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.writebacks::writebacks 81059 # number of writebacks +system.l2c.writebacks::total 81059 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2489 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 605 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3094 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 70 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 101 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 171 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 111855 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8432 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 120287 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13645 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1613 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 15258 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 273692 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 770 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 274462 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13645 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 385547 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1613 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9202 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 410007 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13645 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 385547 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1613 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9202 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 410007 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7053 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 146 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9807 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2584 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 12391 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16860 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2730 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 19590 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 49921000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12220000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 62141000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1392500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1996500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 3389000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8869557000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 877886500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9747443500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1017206501 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 122964001 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1140170502 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17480141501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 62124500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 17542266001 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1017206501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 26349698501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 122964001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 940011000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 28429880003 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1017206501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 26349698501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 122964001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 940011000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 28429880003 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1482000500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27810500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1509811000 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1482000500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 27810500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1509811000 # number of overall MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2505 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 627 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3132 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 74 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 102 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 176 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 111923 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8380 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 120303 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13465 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1843 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 15308 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 273663 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 829 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 274492 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13465 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 385586 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1843 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9209 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 410103 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13465 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 385586 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1843 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9209 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 410103 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7032 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7194 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9755 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2639 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 12394 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16787 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2801 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 19588 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 50228500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12653000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 62881500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1467500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2009000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 3476500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8874280004 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 859128000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9733408004 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1001369001 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 138309001 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1139678002 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17481138002 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 69259501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 17550397503 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1001369001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 26355418006 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 138309001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 928387501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 28423483509 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1001369001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 26355418006 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 138309001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 928387501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28423483509 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478504000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 30323500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1508827500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1478504000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 30323500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1508827500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.929425 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.888399 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.921107 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.421687 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.587629 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.399691 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.378422 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.398122 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013294 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.259785 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.018459 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250594 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.289149 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.143788 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.161097 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.289149 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.143788 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.161097 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20056.649257 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20198.347107 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20084.356820 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19892.857143 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19767.326733 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19818.713450 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79295.132091 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104113.674099 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 81034.887394 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74726.078254 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63867.930013 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80681.168831 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63915.099362 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210123.422657 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190482.876712 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209725.100708 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87900.385528 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10186.996337 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 77070.495151 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 843888 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 393117 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 439 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934004 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.889362 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.924712 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.443114 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.796875 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.596610 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.400353 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.375213 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.398493 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014127 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013362 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260010 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019567 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250706 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.289464 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014127 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.142329 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.161307 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.289464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014127 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.142329 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.161307 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20051.297405 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20180.223285 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20077.107280 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19831.081081 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19696.078431 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19752.840909 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79289.154186 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 102521.241050 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80907.442075 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74368.288229 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75045.578405 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74449.830285 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63878.339425 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83545.839566 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63937.737723 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74368.288229 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68351.594731 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75045.578405 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 100813.063416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69308.157973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74368.288229 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68351.594731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75045.578405 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 100813.063416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69308.157973 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210253.697383 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187182.098765 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209734.153461 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 88074.343242 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10825.955016 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77028.154993 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 844318 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 393480 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 297053 # Transaction distribution -system.membus.trans_dist::WriteReq 12391 # Transaction distribution -system.membus.trans_dist::WriteResp 12391 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122655 # Transaction distribution -system.membus.trans_dist::CleanEvict 262560 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5361 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1592 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 7194 # Transaction distribution +system.membus.trans_dist::ReadResp 297120 # Transaction distribution +system.membus.trans_dist::WriteReq 12394 # Transaction distribution +system.membus.trans_dist::WriteResp 12394 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122579 # Transaction distribution +system.membus.trans_dist::CleanEvict 262673 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5556 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1697 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 120253 # Transaction distribution -system.membus.trans_dist::ReadExResp 120107 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289902 # Transaction distribution -system.membus.trans_dist::BadAddressError 48 # Transaction distribution +system.membus.trans_dist::ReadExReq 120271 # Transaction distribution +system.membus.trans_dist::ReadExResp 120125 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289973 # Transaction distribution +system.membus.trans_dist::BadAddressError 47 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39180 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1169885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 96 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1209161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83451 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83451 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1292612 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68539 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31400256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31468795 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1170427 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1209697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1293130 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68530 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31401600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31470130 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34127035 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 4109 # Total snoops (count) -system.membus.snoop_fanout::samples 478250 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001409 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037514 # Request fanout histogram +system.membus.pkt_size::total 34128370 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 4361 # Total snoops (count) +system.membus.snoopTraffic 28480 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 478637 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001444 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037968 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 477576 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 674 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 477946 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 691 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 478250 # Request fanout histogram -system.membus.reqLayer0.occupancy 34894499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 478637 # Request fanout histogram +system.membus.reqLayer0.occupancy 34935499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1351079796 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1350989532 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 59500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2171993250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2172548749 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 976613 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 925113 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5115302 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2557070 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 337938 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1067 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5110475 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2554732 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 342217 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1055 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 987 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2263337 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12391 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12391 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 911885 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1146691 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 834780 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5446 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1712 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 7158 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 7194 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2261145 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12394 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12394 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 911435 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1144537 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 834683 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5633 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1816 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 7449 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 303166 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 303166 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1147985 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1108204 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 48 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 217 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3065153 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4053991 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 377239 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 207014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7703397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 130759360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 136128589 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16082688 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6548014 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 289518651 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 362547 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2930720 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.118515 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.323634 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 302973 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302973 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1145857 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1108145 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3045120 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4050284 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 390880 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 209583 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7695867 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 129904512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 135990364 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16664640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6622614 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 289182130 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 363206 # Total snoops (count) +system.toL2Bus.snoopTraffic 6121792 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2928698 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.120181 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.325532 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2583760 88.16% 88.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 346605 11.83% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 335 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2577056 87.99% 87.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 351320 12.00% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 312 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 10 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2930720 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4551122919 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2928698 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4546181919 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 306385 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 291385 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1534824957 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1524803969 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2028150819 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2026499354 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 190444943 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 197300876 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 107558787 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 108970290 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2203,185 +2187,185 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 198541 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71138 40.62% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.08% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1928 1.10% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 20 0.01% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101928 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175147 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69801 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1928 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 197565 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 70781 40.59% 40.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.66% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.10% 41.77% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 20 0.01% 41.78% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 101534 58.22% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174393 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69444 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.37% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 20 0.01% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69782 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141664 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864307233500 97.69% 97.69% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 66845500 0.00% 97.70% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 580922500 0.03% 97.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 11315500 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 43373119000 2.27% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1908339436000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981206 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 69424 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 140946 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863377945500 97.69% 97.69% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 65817500 0.00% 97.70% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 580544500 0.03% 97.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 11361000 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 43328343000 2.27% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907364011500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981111 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684621 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808829 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.70% 3.70% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.33% 12.04% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.85% 13.89% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.81% 28.70% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.46% 29.17% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.70% 32.87% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.63% 37.50% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.78% 40.28% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.46% 40.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.39% 42.13% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.78% 44.91% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.93% 45.83% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.28% 61.11% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.39% 62.50% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.63% 67.13% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.63% 71.76% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.46% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.78% 75.00% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.65% 85.65% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.39% 87.04% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.78% 89.81% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.46% 90.28% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.39% 91.67% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.17% 95.83% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.93% 96.76% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.93% 97.69% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.46% 98.15% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 216 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.683751 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808209 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.76% 3.76% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.45% 12.21% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.88% 14.08% # number of syscalls executed +system.cpu0.kern.syscall::6 32 15.02% 29.11% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 29.58% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.76% 33.33% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.69% 38.03% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.82% 40.85% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.47% 41.31% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.41% 42.72% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.82% 45.54% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.94% 46.48% # number of syscalls executed +system.cpu0.kern.syscall::45 33 15.49% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.41% 63.38% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.69% 68.08% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.69% 72.77% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 73.24% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.82% 76.06% # number of syscalls executed +system.cpu0.kern.syscall::71 21 9.86% 85.92% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.41% 87.32% # number of syscalls executed +system.cpu0.kern.syscall::74 5 2.35% 89.67% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 90.14% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.41% 91.55% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.23% 95.77% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.94% 96.71% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.94% 97.65% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.47% 98.12% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.94% 99.06% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.94% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 213 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 116 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 120 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3824 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3815 2.08% 2.15% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168401 91.54% 93.72% # number of callpals executed -system.cpu0.kern.callpal::rdps 6369 3.46% 97.18% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::rti 4665 2.54% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::swpipl 167656 91.61% 93.80% # number of callpals executed +system.cpu0.kern.callpal::rdps 6177 3.38% 97.17% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::rti 4658 2.55% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183960 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7174 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches +system.cpu0.kern.callpal::total 183007 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7158 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1253 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1257 -system.cpu0.kern.mode_good::user 1257 +system.cpu0.kern.mode_good::kernel 1253 +system.cpu0.kern.mode_good::user 1253 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175216 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175049 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298185 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1906404052500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1926707500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.297943 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1905453819000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1901068000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3825 # number of times the context was actually changed +system.cpu0.kern.swap_context 3816 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2309 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39314 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10555 33.51% 33.51% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1926 6.11% 39.62% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 116 0.37% 39.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18905 60.01% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 31502 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10515 45.81% 45.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1926 8.39% 54.19% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 116 0.51% 54.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10399 45.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22956 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1877342030500 98.36% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 564972500 0.03% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 56160500 0.00% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30688096500 1.61% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1908651260000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.996210 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2323 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 40320 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10930 33.84% 33.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 5.96% 39.80% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 120 0.37% 40.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 19320 59.82% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 32295 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10890 45.94% 45.94% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 8.12% 54.06% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 120 0.51% 54.57% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10770 45.43% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 23705 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1876314481500 98.36% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 564739500 0.03% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 58247500 0.00% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 30733817000 1.61% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907671285500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.996340 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.550066 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.728716 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 12 10.91% 10.91% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.09% 20.00% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.91% 20.91% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.36% 27.27% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.73% 30.00% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.73% 32.73% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.55% 37.27% # number of syscalls executed -system.cpu1.kern.syscall::45 21 19.09% 56.36% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.73% 59.09% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.91% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::71 31 28.18% 88.18% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.09% 97.27% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.73% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 110 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.557453 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.734015 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 12 10.62% 10.62% # number of syscalls executed +system.cpu1.kern.syscall::6 10 8.85% 19.47% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.88% 20.35% # number of syscalls executed +system.cpu1.kern.syscall::17 7 6.19% 26.55% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.65% 29.20% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.65% 31.86% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.42% 36.28% # number of syscalls executed +system.cpu1.kern.syscall::45 21 18.58% 54.87% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.65% 57.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.88% 58.41% # number of syscalls executed +system.cpu1.kern.syscall::71 33 29.20% 87.61% # number of syscalls executed +system.cpu1.kern.syscall::74 11 9.73% 97.35% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.65% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 113 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal::wripir 20 0.06% 0.06% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu1.kern.callpal::swpctx 440 1.35% 1.42% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.43% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.45% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26890 82.68% 84.13% # number of callpals executed -system.cpu1.kern.callpal::rdps 2393 7.36% 91.49% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.50% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.51% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.52% # number of callpals executed -system.cpu1.kern.callpal::rti 2569 7.90% 99.42% # number of callpals executed -system.cpu1.kern.callpal::callsys 144 0.44% 99.86% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.14% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 449 1.34% 1.41% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.42% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.44% # number of callpals executed +system.cpu1.kern.callpal::swpipl 27672 82.56% 84.00% # number of callpals executed +system.cpu1.kern.callpal::rdps 2585 7.71% 91.71% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.71% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 91.73% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.74% # number of callpals executed +system.cpu1.kern.callpal::rti 2577 7.69% 99.42% # number of callpals executed +system.cpu1.kern.callpal::callsys 148 0.44% 99.87% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.13% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32523 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 900 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2082 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 529 -system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 41 -system.cpu1.kern.mode_switch_good::kernel 0.587778 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 33518 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 911 # number of protection mode switches +system.cpu1.kern.mode_switch::user 493 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2088 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 538 +system.cpu1.kern.mode_good::user 493 +system.cpu1.kern.mode_good::idle 45 +system.cpu1.kern.mode_switch_good::kernel 0.590560 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.019693 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.304899 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2122812500 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 785064000 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1905743375500 99.85% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 441 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.021552 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.308133 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2257888000 0.12% 0.12% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 790670500 0.04% 0.16% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1904622719000 99.84% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 450 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index 195c1d872..7e0283697 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 |