diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3819 |
1 files changed, 1907 insertions, 1912 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 2b53a578a..683e407e9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,138 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906207 # Number of seconds simulated -sim_ticks 1906207240000 # Number of ticks simulated -final_tick 1906207240000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903124 # Number of seconds simulated +sim_ticks 1903123778500 # Number of ticks simulated +final_tick 1903123778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147655 # Simulator instruction rate (inst/s) -host_op_rate 147655 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5021061637 # Simulator tick rate (ticks/s) -host_mem_usage 308576 # Number of bytes of host memory used -host_seconds 379.64 # Real time elapsed on the host -sim_insts 56056069 # Number of instructions simulated -sim_ops 56056069 # Number of ops (including micro ops) simulated +host_inst_rate 103415 # Simulator instruction rate (inst/s) +host_op_rate 103415 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3505224116 # Simulator tick rate (ticks/s) +host_mem_usage 322696 # Number of bytes of host memory used +host_seconds 542.94 # Real time elapsed on the host +sim_insts 56148221 # Number of instructions simulated +sim_ops 56148221 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 903488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24906304 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 74560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 378304 # Number of bytes read from this memory -system.physmem.bytes_read::total 28912320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 903488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 74560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7848000 # Number of bytes written to this memory -system.physmem.bytes_written::total 7848000 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389161 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5911 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451755 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122625 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122625 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 473972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13065895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1390019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 39114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 198459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15167459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 473972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 39114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4117076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4117076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4117076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 473972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13065895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1390019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 39114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 198459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19284535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451755 # Number of read requests accepted -system.physmem.writeReqs 122625 # Number of write requests accepted -system.physmem.readBursts 451755 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122625 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28904128 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7846080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28912320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7848000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 744192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24296448 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 238144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1067328 # Number of bytes read from this memory +system.physmem.bytes_read::total 26347072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 744192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 238144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 982336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5275328 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7934656 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379632 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16677 # Number of read requests responded to by this memory +system.physmem.num_reads::total 411673 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82427 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123979 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 391037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12766615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 125133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 560830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13844119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 391037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 125133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2771931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1397349 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4169280 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2771931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 391037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12766615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1397853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 125133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 560830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18013399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411673 # Number of read requests accepted +system.physmem.writeReqs 123979 # Number of write requests accepted +system.physmem.readBursts 411673 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123979 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26335040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue +system.physmem.bytesWritten 7932928 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26347072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7934656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3217 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28097 # Per bank write bursts -system.physmem.perBankRdBursts::1 28602 # Per bank write bursts -system.physmem.perBankRdBursts::2 29043 # Per bank write bursts -system.physmem.perBankRdBursts::3 27571 # Per bank write bursts -system.physmem.perBankRdBursts::4 27384 # Per bank write bursts -system.physmem.perBankRdBursts::5 27564 # Per bank write bursts -system.physmem.perBankRdBursts::6 27744 # Per bank write bursts -system.physmem.perBankRdBursts::7 27694 # Per bank write bursts -system.physmem.perBankRdBursts::8 27865 # Per bank write bursts -system.physmem.perBankRdBursts::9 28720 # Per bank write bursts -system.physmem.perBankRdBursts::10 28531 # Per bank write bursts -system.physmem.perBankRdBursts::11 28618 # Per bank write bursts -system.physmem.perBankRdBursts::12 28938 # Per bank write bursts -system.physmem.perBankRdBursts::13 28977 # Per bank write bursts -system.physmem.perBankRdBursts::14 28277 # Per bank write bursts -system.physmem.perBankRdBursts::15 28002 # Per bank write bursts -system.physmem.perBankWrBursts::0 7839 # Per bank write bursts -system.physmem.perBankWrBursts::1 8045 # Per bank write bursts -system.physmem.perBankWrBursts::2 8418 # Per bank write bursts -system.physmem.perBankWrBursts::3 7040 # Per bank write bursts -system.physmem.perBankWrBursts::4 6886 # Per bank write bursts -system.physmem.perBankWrBursts::5 7040 # Per bank write bursts -system.physmem.perBankWrBursts::6 7326 # Per bank write bursts -system.physmem.perBankWrBursts::7 7097 # Per bank write bursts -system.physmem.perBankWrBursts::8 7158 # Per bank write bursts -system.physmem.perBankWrBursts::9 7908 # Per bank write bursts -system.physmem.perBankWrBursts::10 7739 # Per bank write bursts -system.physmem.perBankWrBursts::11 7821 # Per bank write bursts -system.physmem.perBankWrBursts::12 8331 # Per bank write bursts -system.physmem.perBankWrBursts::13 8401 # Per bank write bursts -system.physmem.perBankWrBursts::14 7959 # Per bank write bursts -system.physmem.perBankWrBursts::15 7587 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3444 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25632 # Per bank write bursts +system.physmem.perBankRdBursts::1 25720 # Per bank write bursts +system.physmem.perBankRdBursts::2 26346 # Per bank write bursts +system.physmem.perBankRdBursts::3 25660 # Per bank write bursts +system.physmem.perBankRdBursts::4 25672 # Per bank write bursts +system.physmem.perBankRdBursts::5 25150 # Per bank write bursts +system.physmem.perBankRdBursts::6 25568 # Per bank write bursts +system.physmem.perBankRdBursts::7 25491 # Per bank write bursts +system.physmem.perBankRdBursts::8 25973 # Per bank write bursts +system.physmem.perBankRdBursts::9 26167 # Per bank write bursts +system.physmem.perBankRdBursts::10 25812 # Per bank write bursts +system.physmem.perBankRdBursts::11 25687 # Per bank write bursts +system.physmem.perBankRdBursts::12 26023 # Per bank write bursts +system.physmem.perBankRdBursts::13 25844 # Per bank write bursts +system.physmem.perBankRdBursts::14 25108 # Per bank write bursts +system.physmem.perBankRdBursts::15 25632 # Per bank write bursts +system.physmem.perBankWrBursts::0 8431 # Per bank write bursts +system.physmem.perBankWrBursts::1 7989 # Per bank write bursts +system.physmem.perBankWrBursts::2 8275 # Per bank write bursts +system.physmem.perBankWrBursts::3 7382 # Per bank write bursts +system.physmem.perBankWrBursts::4 7684 # Per bank write bursts +system.physmem.perBankWrBursts::5 7400 # Per bank write bursts +system.physmem.perBankWrBursts::6 7193 # Per bank write bursts +system.physmem.perBankWrBursts::7 7021 # Per bank write bursts +system.physmem.perBankWrBursts::8 7374 # Per bank write bursts +system.physmem.perBankWrBursts::9 7755 # Per bank write bursts +system.physmem.perBankWrBursts::10 7777 # Per bank write bursts +system.physmem.perBankWrBursts::11 7454 # Per bank write bursts +system.physmem.perBankWrBursts::12 8052 # Per bank write bursts +system.physmem.perBankWrBursts::13 8097 # Per bank write bursts +system.physmem.perBankWrBursts::14 7762 # Per bank write bursts +system.physmem.perBankWrBursts::15 8306 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1906202745000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 1903119235000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 451755 # Read request sizes (log2) +system.physmem.readPktSize::6 411673 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122625 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 319401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 41325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123979 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -158,359 +161,357 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 549.396161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 336.305192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 420.466175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14808 22.14% 22.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11177 16.71% 38.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5157 7.71% 46.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2881 4.31% 50.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2294 3.43% 54.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1713 2.56% 56.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1492 2.23% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1822 2.72% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25548 38.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66892 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7192 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 62.794355 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2475.959084 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 7189 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7192 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7192 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.046023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.810949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.823344 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5742 79.84% 79.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 42 0.58% 80.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 691 9.61% 90.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 254 3.53% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 102 1.42% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 28 0.39% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 28 0.39% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 90 1.25% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.14% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 32 0.44% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 22 0.31% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 14 0.19% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 15 0.21% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.10% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 9 0.13% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 23 0.32% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.15% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.03% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 4 0.06% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.01% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 8 0.11% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 4 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 13 0.18% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 13 0.18% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7192 # Writes before turning the bus around for reads -system.physmem.totQLat 9007685000 # Total ticks spent queuing -system.physmem.totMemAccLat 17475691250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2258135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19944.97 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 64910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 527.930488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.008348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.202697 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14944 23.02% 23.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11454 17.65% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5213 8.03% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2920 4.50% 53.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2279 3.51% 56.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1787 2.75% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1551 2.39% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1716 2.64% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23046 35.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64910 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5635 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.021650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2812.727565 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5632 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5635 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5635 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.996806 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.958563 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.289473 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4843 85.94% 85.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 143 2.54% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10 0.18% 88.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 227 4.03% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 45 0.80% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 4 0.07% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 10 0.18% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.18% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 34 0.60% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.11% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.16% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 41 0.73% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 13 0.23% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.04% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 176 3.12% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.09% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.05% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.18% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.11% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5635 # Writes before turning the bus around for reads +system.physmem.totQLat 3887945250 # Total ticks spent queuing +system.physmem.totMemAccLat 11603289000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2057425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9448.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38694.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28198.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing -system.physmem.readRowHits 408104 # Number of row buffer hits during reads -system.physmem.writeRowHits 99226 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes -system.physmem.avgGap 3318713.65 # Average gap between requests -system.physmem.pageHitRate 88.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1805036475500 # Time in different power states -system.physmem.memoryStateTime::REF 63652420000 # Time in different power states +system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 371100 # Number of row buffer hits during reads +system.physmem.writeRowHits 99427 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.20 # Row buffer hit rate for writes +system.physmem.avgGap 3552902.32 # Average gap between requests +system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1802319562500 # Time in different power states +system.physmem.memoryStateTime::REF 63549460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37517744500 # Time in different power states +system.physmem.memoryStateTime::ACT 37254262500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19340215 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296416 # Transaction distribution -system.membus.trans_dist::ReadResp 296338 # Transaction distribution -system.membus.trans_dist::WriteReq 12317 # Transaction distribution -system.membus.trans_dist::WriteResp 12317 # Transaction distribution -system.membus.trans_dist::Writeback 122625 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1033 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3220 # Transaction distribution -system.membus.trans_dist::ReadExReq 163308 # Transaction distribution -system.membus.trans_dist::ReadExResp 163210 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39026 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 910934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 950116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1074769 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 67930 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31453376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31521306 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36828250 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36828250 # Total data (bytes) -system.membus.snoop_data_through_bus 38208 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 36079499 # Layer occupancy (ticks) +system.membus.throughput 18054612 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296849 # Transaction distribution +system.membus.trans_dist::ReadResp 296569 # Transaction distribution +system.membus.trans_dist::WriteReq 12351 # Transaction distribution +system.membus.trans_dist::WriteResp 12351 # Transaction distribution +system.membus.trans_dist::Writeback 82427 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5284 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1479 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3444 # Transaction distribution +system.membus.trans_dist::ReadExReq 122594 # Transaction distribution +system.membus.trans_dist::ReadExResp 122459 # Transaction distribution +system.membus.trans_dist::BadAddressError 280 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 916085 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 955737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1039031 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68194 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31621440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31689634 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34349922 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34349922 # Total data (bytes) +system.membus.snoop_data_through_bus 10240 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 35504996 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1585687750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1560042750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 374000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3823460772 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3834491323 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376710991 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43141738 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 344852 # number of replacements -system.l2c.tags.tagsinuse 65305.335131 # Cycle average of tags in use -system.l2c.tags.total_refs 2605080 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409986 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.354071 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7095487750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53708.677879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5228.517850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6139.451939 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 202.418952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 26.268512 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.819529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093681 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000401 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996480 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65134 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2578 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5246 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6338 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50733 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993866 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27313168 # Number of tag accesses -system.l2c.tags.data_accesses 27313168 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 979450 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 788527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 94097 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 31413 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1893487 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 833565 # number of Writeback hits -system.l2c.Writeback_hits::total 833565 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 47 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 175693 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7721 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183414 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 979450 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 964220 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 94097 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 39134 # number of demand (read+write) hits -system.l2c.demand_hits::total 2076901 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 979450 # number of overall hits -system.l2c.overall_hits::cpu0.data 964220 # number of overall hits -system.l2c.overall_hits::cpu1.inst 94097 # number of overall hits -system.l2c.overall_hits::cpu1.data 39134 # number of overall hits -system.l2c.overall_hits::total 2076901 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14127 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273418 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1173 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 340 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289058 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 511 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2953 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 76 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 110 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 116199 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5616 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121815 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14127 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389617 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1173 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 5956 # number of demand (read+write) misses -system.l2c.demand_misses::total 410873 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14127 # number of overall misses -system.l2c.overall_misses::cpu0.data 389617 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1173 # number of overall misses -system.l2c.overall_misses::cpu1.data 5956 # number of overall misses -system.l2c.overall_misses::total 410873 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1071252992 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17895085485 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 90289500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 26594999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19083222976 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1079964 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 402483 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1482447 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 116495 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 68997 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 185492 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9654052371 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 606648221 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10260700592 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1071252992 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 27549137856 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 90289500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 633243220 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29343923568 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1071252992 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 27549137856 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 90289500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 633243220 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29343923568 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 993577 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1061945 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 95270 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 31753 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2182545 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 833565 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 833565 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2617 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 557 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3174 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 61 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 96 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 157 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 291892 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13337 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305229 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 993577 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1353837 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 95270 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 45090 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2487774 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 993577 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1353837 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 95270 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 45090 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2487774 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.257469 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.012312 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.010708 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.132441 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933130 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.917415 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930372 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.557377 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.791667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.700637 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.398089 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.421084 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.399094 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014218 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.287787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.012312 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.132091 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165157 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014218 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.287787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.012312 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.132091 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165157 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75830.182771 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65449.551547 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76973.145780 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78220.585294 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 66018.663991 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 442.245700 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 787.637965 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 502.013884 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3426.323529 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 907.855263 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1686.290909 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83082.060698 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108021.406873 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84231.831811 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 75830.182771 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70708.254147 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76973.145780 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 106320.218267 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71418.476191 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 75830.182771 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70708.254147 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76973.145780 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 106320.218267 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71418.476191 # average overall miss latency +system.l2c.tags.replacements 345839 # number of replacements +system.l2c.tags.tagsinuse 65302.356632 # Cycle average of tags in use +system.l2c.tags.total_refs 2646364 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411006 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.438748 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7093732750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53566.898021 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4193.415796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5564.276304 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1386.450480 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 591.316031 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.817366 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063986 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.084904 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021156 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009023 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996435 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 2289 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6029 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6100 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 50524 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27707761 # Number of tag accesses +system.l2c.tags.data_accesses 27707761 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 751132 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 546267 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 350558 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 278844 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1926801 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 841911 # number of Writeback hits +system.l2c.Writeback_hits::total 841911 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 128 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 75 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 203 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 37 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 140399 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 48308 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 188707 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 751132 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 686666 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 350558 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 327152 # number of demand (read+write) hits +system.l2c.demand_hits::total 2115508 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 751132 # number of overall hits +system.l2c.overall_hits::cpu0.data 686666 # number of overall hits +system.l2c.overall_hits::cpu1.inst 350558 # number of overall hits +system.l2c.overall_hits::cpu1.data 327152 # number of overall hits +system.l2c.overall_hits::total 2115508 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11641 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272205 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3725 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1926 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289497 # 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average overall miss latency -system.iocache.blocked_cycles::no_mshrs 366756 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122082.188571 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122082.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122082.188571 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28394 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.916673 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 180 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41732 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41732 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41732 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41732 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12701883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12701883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10283217961 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10283217961 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10295919844 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10295919844 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10295919844 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10295919844 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12263383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12263383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2507056568 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2507056568 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12263383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12263383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12263383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12263383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -757,35 +750,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 13535285 # Number of BP lookups -system.cpu0.branchPred.condPredicted 11399113 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 368683 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9302001 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5741441 # Number of BTB hits +system.cpu0.branchPred.lookups 13702956 # Number of BP lookups +system.cpu0.branchPred.condPredicted 11991857 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 276088 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8588922 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4683455 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 61.722644 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 871515 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32576 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.529020 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 677984 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 15448 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9655924 # DTB read hits -system.cpu0.dtb.read_misses 34371 # DTB read misses -system.cpu0.dtb.read_acv 569 # DTB read access violations -system.cpu0.dtb.read_accesses 673777 # DTB read accesses -system.cpu0.dtb.write_hits 6329246 # DTB write hits -system.cpu0.dtb.write_misses 8477 # DTB write misses -system.cpu0.dtb.write_acv 351 # DTB write access violations -system.cpu0.dtb.write_accesses 236111 # DTB write accesses -system.cpu0.dtb.data_hits 15985170 # DTB hits -system.cpu0.dtb.data_misses 42848 # DTB misses -system.cpu0.dtb.data_acv 920 # DTB access violations -system.cpu0.dtb.data_accesses 909888 # DTB accesses -system.cpu0.itb.fetch_hits 1092484 # ITB hits -system.cpu0.itb.fetch_misses 31809 # ITB misses -system.cpu0.itb.fetch_acv 996 # ITB acv -system.cpu0.itb.fetch_accesses 1124293 # ITB accesses +system.cpu0.dtb.read_hits 7950804 # DTB read hits +system.cpu0.dtb.read_misses 30543 # DTB read misses +system.cpu0.dtb.read_acv 546 # DTB read access violations +system.cpu0.dtb.read_accesses 683229 # DTB read accesses +system.cpu0.dtb.write_hits 5159026 # DTB write hits +system.cpu0.dtb.write_misses 6845 # DTB write misses +system.cpu0.dtb.write_acv 353 # DTB write access violations +system.cpu0.dtb.write_accesses 234573 # DTB write accesses +system.cpu0.dtb.data_hits 13109830 # DTB hits +system.cpu0.dtb.data_misses 37388 # DTB misses +system.cpu0.dtb.data_acv 899 # DTB access violations +system.cpu0.dtb.data_accesses 917802 # DTB accesses +system.cpu0.itb.fetch_hits 1312718 # ITB hits +system.cpu0.itb.fetch_misses 29261 # ITB misses +system.cpu0.itb.fetch_acv 629 # ITB acv +system.cpu0.itb.fetch_accesses 1341979 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -798,304 +791,304 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 120980731 # number of cpu cycles simulated +system.cpu0.numCycles 99665250 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 27854466 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69491073 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13535285 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6612956 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12980522 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1985487 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37586938 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31052 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 209286 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 361146 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8301805 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 269407 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 80329317 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.865077 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.209142 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 22511576 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60582407 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13702956 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5361439 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 70984108 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 933480 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 621 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 27412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1463366 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 292819 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7109889 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 200075 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 95746858 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.632735 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.928110 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67348795 83.84% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 826622 1.03% 84.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1640547 2.04% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 764329 0.95% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2736993 3.41% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 565546 0.70% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 615994 0.77% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1025224 1.28% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4805267 5.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 84335489 88.08% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 757900 0.79% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1598110 1.67% 90.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 658612 0.69% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2290747 2.39% 93.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 510807 0.53% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 540667 0.56% 94.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 744782 0.78% 95.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4309744 4.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 80329317 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.111880 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.574398 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 28693302 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 37589637 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12241193 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 539176 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1266008 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 554913 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 40031 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68046301 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 123637 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1266008 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 29596220 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 13874520 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19704370 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11366279 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4521918 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64294985 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 8881 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 963704 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 49626 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1581472 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 42969329 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 77993479 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77835647 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 147432 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36982529 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5986792 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1597094 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 233553 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9775023 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10212119 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6719453 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1264075 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 886942 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56810323 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2002217 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 55156303 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 107150 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7195907 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4115621 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1359252 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 80329317 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.686627 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.367653 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 95746858 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.137490 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.607859 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18154184 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 68366814 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7221268 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1568077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 436514 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 432928 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 30567 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53177978 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 98719 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 436514 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18925396 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 44877173 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16564638 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 7942906 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7000229 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 51314401 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 200370 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1702156 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 121650 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3596195 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 34369689 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 62476617 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 62360377 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 107565 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30276917 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4092764 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1298231 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 191875 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11393500 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8037568 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5366781 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1135735 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 800748 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 45795204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1644687 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 45103865 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 41971 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5328763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2477826 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1134880 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 95746858 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.471074 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.201865 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56644741 70.52% 70.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10637349 13.24% 83.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4503428 5.61% 89.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3111745 3.87% 93.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2708967 3.37% 96.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1473067 1.83% 98.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 832512 1.04% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 359476 0.45% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 58032 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 76985468 80.41% 80.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8252195 8.62% 89.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3430688 3.58% 92.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2350675 2.46% 95.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2374207 2.48% 97.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1175968 1.23% 98.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 779493 0.81% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 300669 0.31% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 97495 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 80329317 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 95746858 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 91428 11.87% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 367704 47.76% 59.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 310812 40.37% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 143906 17.61% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 398143 48.73% 66.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 274956 33.65% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3793 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37662855 68.28% 68.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60369 0.11% 68.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.40% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 16864 0.03% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 10116560 18.34% 86.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6398898 11.60% 98.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 895081 1.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30829458 68.35% 68.36% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46395 0.10% 68.46% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 26948 0.06% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8252345 18.30% 86.82% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5217820 11.57% 98.39% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 725236 1.61% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 55156303 # Type of FU issued -system.cpu0.iq.rate 0.455910 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 769944 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013959 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 190884663 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65713674 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53746277 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 634353 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 307759 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 299045 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55590646 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 331808 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 587688 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 45103865 # Type of FU issued +system.cpu0.iq.rate 0.452554 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 817005 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018114 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 186342910 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 52562719 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43916640 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 470653 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 221373 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 216432 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 45663938 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 253152 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 522094 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1466473 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4362 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13302 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 593267 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 946690 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4799 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15752 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 387148 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18777 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 290466 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13610 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 357638 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1266008 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10034082 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1132931 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 62323042 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 565721 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10212119 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6719453 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1762676 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 460962 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 503945 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13302 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186944 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 388547 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 575491 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54610252 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9715916 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 546050 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 436514 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 41413967 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1424350 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50298451 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 103444 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8037568 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5366781 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1456887 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 31578 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1238658 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15752 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 134081 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 309122 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 443203 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 44677716 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8001376 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 426148 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3510502 # number of nop insts executed -system.cpu0.iew.exec_refs 16068148 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8653897 # Number of branches executed -system.cpu0.iew.exec_stores 6352232 # Number of stores executed -system.cpu0.iew.exec_rate 0.451396 # Inst execution rate -system.cpu0.iew.wb_sent 54145867 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 54045322 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 27468175 # num instructions producing a value -system.cpu0.iew.wb_consumers 37895992 # num instructions consuming a value +system.cpu0.iew.exec_nop 2858560 # number of nop insts executed +system.cpu0.iew.exec_refs 13178604 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7039370 # Number of branches executed +system.cpu0.iew.exec_stores 5177228 # Number of stores executed +system.cpu0.iew.exec_rate 0.448278 # Inst execution rate +system.cpu0.iew.wb_sent 44227196 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44133072 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22691402 # num instructions producing a value +system.cpu0.iew.wb_consumers 31140086 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.446727 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.724831 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.442813 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.728688 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7798809 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 642965 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 531823 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 79063309 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.688507 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.631609 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5846321 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 509807 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 407712 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 94708833 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.468364 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.405169 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 59272342 74.97% 74.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8075780 10.21% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4311536 5.45% 90.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2381088 3.01% 93.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1583020 2.00% 95.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 598155 0.76% 96.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 490827 0.62% 97.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 478799 0.61% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1871762 2.37% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 79035549 83.45% 83.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6314508 6.67% 90.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3292930 3.48% 93.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1802282 1.90% 95.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1366338 1.44% 96.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 489382 0.52% 97.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 366889 0.39% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 390234 0.41% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1650721 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 79063309 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 54435622 # Number of instructions committed -system.cpu0.commit.committedOps 54435622 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 94708833 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 44358216 # Number of instructions committed +system.cpu0.commit.committedOps 44358216 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14871832 # Number of memory references committed -system.cpu0.commit.loads 8745646 # Number of loads committed -system.cpu0.commit.membars 219982 # Number of memory barriers committed -system.cpu0.commit.branches 8204799 # Number of branches committed -system.cpu0.commit.fp_insts 296843 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 50375539 # Number of committed integer instructions. -system.cpu0.commit.function_calls 712916 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 3148922 5.78% 5.78% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 35215746 64.69% 70.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 59292 0.11% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 16864 0.03% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8965628 16.47% 87.09% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 6132206 11.27% 98.36% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 895081 1.64% 100.00% # Class of committed instruction +system.cpu0.commit.refs 12070511 # Number of memory references committed +system.cpu0.commit.loads 7090878 # Number of loads committed +system.cpu0.commit.membars 170277 # Number of memory barriers committed +system.cpu0.commit.branches 6663650 # Number of branches committed +system.cpu0.commit.fp_insts 213529 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 41141903 # Number of committed integer instructions. +system.cpu0.commit.function_calls 549728 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2498518 5.63% 5.63% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 28814427 64.96% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 45393 0.10% 70.69% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 26477 0.06% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7261155 16.37% 87.13% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 4985127 11.24% 98.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 725236 1.63% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 54435622 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1871762 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 44358216 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1650721 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 139225703 # The number of ROB reads -system.cpu0.rob.rob_writes 125735253 # The number of ROB writes -system.cpu0.timesIdled 1168278 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 40651414 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3691427340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 51290467 # Number of Instructions Simulated -system.cpu0.committedOps 51290467 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.358737 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.358737 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.423956 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.423956 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71570668 # number of integer regfile reads -system.cpu0.int_regfile_writes 39014056 # number of integer regfile writes -system.cpu0.fp_regfile_reads 147010 # number of floating regfile reads -system.cpu0.fp_regfile_writes 148900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1947197 # number of misc regfile reads -system.cpu0.misc_regfile_writes 897129 # number of misc regfile writes +system.cpu0.rob.rob_reads 143064224 # The number of ROB reads +system.cpu0.rob.rob_writes 101447849 # The number of ROB writes +system.cpu0.timesIdled 414726 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3918392 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3706577488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41863465 # Number of Instructions Simulated +system.cpu0.committedOps 41863465 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.380721 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.380721 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.420041 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.420041 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 58777310 # number of integer regfile reads +system.cpu0.int_regfile_writes 31962259 # number of integer regfile writes +system.cpu0.fp_regfile_reads 106639 # number of floating regfile reads +system.cpu0.fp_regfile_writes 106808 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1588469 # number of misc regfile reads +system.cpu0.misc_regfile_writes 729535 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1127,49 +1120,50 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111935595 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2200566 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2200471 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12317 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12317 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 833565 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4571 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1080 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 347592 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 306043 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1987262 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3563495 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 190571 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 127415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5868743 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63588928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 138451052 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 6097280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4501998 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 212639258 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 212628634 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 743808 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5019455896 # Layer occupancy (ticks) +system.toL2Bus.throughput 115690704 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2250904 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2250609 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 841911 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5326 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6878 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 312265 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 312265 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 280 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1525692 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2740000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 708608 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1000724 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5975024 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48817472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 104660497 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22674112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39558737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 215710818 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 215700578 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4473152 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5085967365 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 720000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4476579522 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3437989936 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 6206391842 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4906988127 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 429200431 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 227242208 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1431950 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 53869 # Transaction distribution -system.iobus.trans_dist::WriteResp 53869 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10422 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer2.occupancy 1597018302 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1654443775 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1434388 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 53903 # Transaction distribution +system.iobus.trans_dist::WriteResp 53903 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1180,12 +1174,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122490 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41688 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39092 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122546 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1196,14 +1190,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 67930 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729594 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729594 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9777000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729818 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729818 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9847000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1223,267 +1217,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380161835 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374411689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26709000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26741000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43245009 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42019262 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 993039 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.694749 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7257459 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 993551 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.304566 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26718502250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.694749 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995498 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995498 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9295490 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9295490 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7257459 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7257459 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7257459 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7257459 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7257459 # number of overall hits -system.cpu0.icache.overall_hits::total 7257459 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1044346 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1044346 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1044346 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1044346 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1044346 # number of overall misses -system.cpu0.icache.overall_misses::total 1044346 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14667970749 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14667970749 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14667970749 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14667970749 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14667970749 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14667970749 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8301805 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8301805 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8301805 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8301805 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8301805 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8301805 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125797 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125797 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125797 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125797 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125797 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125797 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14045.125609 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14045.125609 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4303 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 762211 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.848890 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6309809 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 762721 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.272762 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485928250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.848890 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993845 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7872808 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7872808 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6309809 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6309809 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6309809 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6309809 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6309809 # number of overall hits +system.cpu0.icache.overall_hits::total 6309809 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 800080 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 800080 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 800080 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 800080 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 800080 # number of overall misses +system.cpu0.icache.overall_misses::total 800080 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11341096711 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11341096711 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11341096711 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11341096711 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11341096711 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11341096711 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7109889 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7109889 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7109889 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7109889 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7109889 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7109889 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112531 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.112531 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112531 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.112531 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112531 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.112531 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14174.953393 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14174.953393 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3387 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.642857 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.907407 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50661 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50661 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 50661 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50661 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 50661 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50661 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 993685 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 993685 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 993685 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 993685 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 993685 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 993685 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12074149969 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12074149969 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12074149969 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12074149969 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12074149969 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12074149969 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119695 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.119695 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.119695 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37161 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 37161 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37161 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 37161 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37161 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 37161 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 762919 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 762919 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 762919 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 762919 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 762919 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 762919 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9350852559 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9350852559 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9350852559 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9350852559 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9350852559 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9350852559 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.107304 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.107304 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.107304 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1357625 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.932074 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11305784 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1358137 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.324480 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25366000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.932074 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990102 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.990102 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1069035 # number of replacements +system.cpu0.dcache.tags.tagsinuse 482.779727 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9141371 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1069547 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.546956 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.779727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942929 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.942929 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 61088591 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 61088591 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6897589 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6897589 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4012977 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4012977 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181053 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 181053 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208423 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208423 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10910566 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10910566 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10910566 # number of overall hits -system.cpu0.dcache.overall_hits::total 10910566 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1718976 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1718976 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1889613 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1889613 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22934 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22934 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 507 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3608589 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3608589 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3608589 # number of overall misses -system.cpu0.dcache.overall_misses::total 3608589 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42674970043 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42674970043 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 81294445080 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 81294445080 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 374188245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 374188245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3007034 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3007034 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 123969415123 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 123969415123 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8616565 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8616565 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5902590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5902590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203987 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203987 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 208930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14519155 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14519155 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14519155 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14519155 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199497 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199497 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320133 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.320133 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112429 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112429 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002427 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002427 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248540 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248540 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248540 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248540 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5931.033531 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5931.033531 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3433420 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 538 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 116463 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.480779 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 76.857143 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 49546788 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 49546788 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5665393 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5665393 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3152024 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3152024 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147109 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147109 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 170256 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 170256 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8817417 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8817417 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8817417 # number of overall hits +system.cpu0.dcache.overall_hits::total 8817417 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1322171 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1322171 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1644281 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1644281 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16610 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16610 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2966452 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2966452 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2966452 # number of overall misses +system.cpu0.dcache.overall_misses::total 2966452 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36169344894 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36169344894 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74324803897 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 74324803897 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 267182493 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 267182493 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4788059 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4788059 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 110494148791 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 110494148791 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6987564 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6987564 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4796305 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4796305 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163719 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 163719 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 171022 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 171022 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11783869 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11783869 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11783869 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11783869 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.189218 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.189218 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342822 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.342822 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004479 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004479 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251738 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.251738 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251738 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.251738 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27356.026485 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6250.729765 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6250.729765 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3702426 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3454 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 160595 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 88 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.054429 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 39.250000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 808609 # number of writebacks -system.cpu0.dcache.writebacks::total 808609 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 667238 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 667238 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1594728 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1594728 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2261966 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2261966 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2261966 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2261966 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1051738 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1051738 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 294885 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 294885 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17172 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17172 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 507 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1346623 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1346623 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1346623 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1346623 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27880739944 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27880739944 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12002536573 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12002536573 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 202887753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 202887753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1992966 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1992966 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39883276517 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 39883276517 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39883276517 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 39883276517 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1460997001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1460997001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2069284998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2069284998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3530281999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3530281999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122060 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122060 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049959 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049959 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084182 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084182 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002427 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002427 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092748 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092748 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3930.899408 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3930.899408 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 568073 # number of writebacks +system.cpu0.dcache.writebacks::total 568073 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 499697 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 499697 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1402831 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1402831 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1902528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1902528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1902528 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1902528 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 822474 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 822474 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 241450 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 241450 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12284 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12284 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1063924 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1063924 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1063924 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1063924 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24909734008 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24909734008 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10782476086 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10782476086 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 145144507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145144507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3254941 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3254941 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35692210094 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35692210094 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35692210094 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35692210094 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 992378000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 992378000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1672126998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1672126998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2664504998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2664504998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117705 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117705 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075031 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075031 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004479 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004479 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.090286 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.090286 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4249.270235 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4249.270235 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1491,35 +1485,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 1483279 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1227619 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 44770 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 650934 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 463612 # Number of BTB hits +system.cpu1.branchPred.lookups 5770916 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5004196 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 122577 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3556553 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1526133 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.222582 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 99211 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4550 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 42.910453 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 301064 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7748 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1187167 # DTB read hits -system.cpu1.dtb.read_misses 8989 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 276351 # DTB read accesses -system.cpu1.dtb.write_hits 628916 # DTB write hits -system.cpu1.dtb.write_misses 1890 # DTB write misses -system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 104365 # DTB write accesses -system.cpu1.dtb.data_hits 1816083 # DTB hits -system.cpu1.dtb.data_misses 10879 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 380716 # DTB accesses -system.cpu1.itb.fetch_hits 316911 # ITB hits -system.cpu1.itb.fetch_misses 5517 # ITB misses -system.cpu1.itb.fetch_acv 125 # ITB acv -system.cpu1.itb.fetch_accesses 322428 # ITB accesses +system.cpu1.dtb.read_hits 3015540 # DTB read hits +system.cpu1.dtb.read_misses 12269 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 293761 # DTB read accesses +system.cpu1.dtb.write_hits 1836726 # DTB write hits +system.cpu1.dtb.write_misses 2353 # DTB write misses +system.cpu1.dtb.write_acv 39 # DTB write access violations +system.cpu1.dtb.write_accesses 109652 # DTB write accesses +system.cpu1.dtb.data_hits 4852266 # DTB hits +system.cpu1.dtb.data_misses 14622 # DTB misses +system.cpu1.dtb.data_acv 44 # DTB access violations +system.cpu1.dtb.data_accesses 403413 # DTB accesses +system.cpu1.itb.fetch_hits 632341 # ITB hits +system.cpu1.itb.fetch_misses 5352 # ITB misses +system.cpu1.itb.fetch_acv 51 # ITB acv +system.cpu1.itb.fetch_accesses 637693 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1532,553 +1526,554 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 8637240 # number of cpu cycles simulated +system.cpu1.numCycles 26335588 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 2818807 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 7093634 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1483279 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 562823 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1271731 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 278690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3719491 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 23500 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 54196 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48363 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 894062 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 29430 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 8117811 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.873836 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.252237 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9800268 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 22981944 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 5770916 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1827197 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14019681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 419510 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 307 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 23776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 208449 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 196331 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2522136 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 89875 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 24458620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.939626 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.331670 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 6846080 84.33% 84.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 64163 0.79% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 148479 1.83% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 110798 1.36% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 183312 2.26% 90.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 76211 0.94% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 83539 1.03% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 57250 0.71% 93.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 547979 6.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20375648 83.31% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 230665 0.94% 84.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 464859 1.90% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 295118 1.21% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 600413 2.45% 89.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 204861 0.84% 90.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 257669 1.05% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 270860 1.11% 92.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1758527 7.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 8117811 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.171731 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.821285 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 2872853 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 3821739 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1206360 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 38891 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 177967 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 63499 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 3800 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 6911640 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 11536 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 177967 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 2981399 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 177384 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3223332 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1138018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 419709 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 6319378 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 203 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45248 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 5428 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 135690 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 4267087 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 7667393 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 7641550 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 21648 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3453234 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 813853 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 270338 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 17002 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1051064 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1262745 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 687524 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 118324 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 74010 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 5585108 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 271421 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 5341703 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20645 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1049804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 612834 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 207573 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 8117811 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.658023 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.347544 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 24458620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.219130 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.872657 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8213195 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 12716086 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2925937 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 406668 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 196733 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 189397 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 13167 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 19294426 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 40930 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 196733 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8443455 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3954170 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 7253500 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3074788 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1535972 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 18421784 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 5378 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 385976 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 36959 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 551165 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 12165906 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 21959681 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21890085 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 63650 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 10221482 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1944424 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 582778 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 59316 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3316426 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3128488 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1940399 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 395849 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 259099 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 16224994 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 722304 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 15758531 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 26415 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2553169 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1203962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 524576 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 24458620 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644294 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.366216 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 5813637 71.62% 71.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1034901 12.75% 84.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 447279 5.51% 89.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 322285 3.97% 93.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 244246 3.01% 96.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 126246 1.56% 98.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 72876 0.90% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 50809 0.63% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 5532 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 17964380 73.45% 73.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2773024 11.34% 84.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1191873 4.87% 89.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 895755 3.66% 93.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 840464 3.44% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 400907 1.64% 98.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 238226 0.97% 99.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 113179 0.46% 99.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 40812 0.17% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 8117811 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 24458620 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 4295 3.26% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 76591 58.14% 61.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 50850 38.60% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 56470 15.54% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 184321 50.72% 66.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 122598 33.74% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.07% 0.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3268625 61.19% 61.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 9680 0.18% 61.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8881 0.17% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1232456 23.07% 84.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 646098 12.10% 96.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 170686 3.20% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 10371294 65.81% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 24284 0.15% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11773 0.07% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3139820 19.92% 86.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1865147 11.84% 97.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 340936 2.16% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 5341703 # Type of FU issued -system.cpu1.iq.rate 0.618450 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 131736 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 18885884 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 6873502 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 5132762 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 67714 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 33978 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 32480 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 5434957 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 34964 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 63957 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 15758531 # Type of FU issued +system.cpu1.iq.rate 0.598374 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 363389 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023060 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 56111313 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 19387392 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 15262127 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 254173 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 119441 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 117263 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 15982004 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 136398 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 157695 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 266370 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 353 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1238 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 98626 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 453605 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1302 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 6552 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 197079 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 72939 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5589 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 74646 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 177967 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 80772 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 78093 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 6077668 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 83087 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1262745 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 687524 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 253926 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4593 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 73335 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1238 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 19913 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 60148 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 80061 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 5287979 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1198929 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 53724 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 196733 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 3102898 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 407577 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 17959821 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 47400 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3128488 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1940399 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 647154 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 24325 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 312873 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 6552 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 58721 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 143362 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 202083 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 15559963 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3035862 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 198568 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 221139 # number of nop insts executed -system.cpu1.iew.exec_refs 1832774 # number of memory reference insts executed -system.cpu1.iew.exec_branches 762873 # Number of branches executed -system.cpu1.iew.exec_stores 633845 # Number of stores executed -system.cpu1.iew.exec_rate 0.612230 # Inst execution rate -system.cpu1.iew.wb_sent 5189273 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 5165242 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2532511 # num instructions producing a value -system.cpu1.iew.wb_consumers 3587094 # num instructions consuming a value +system.cpu1.iew.exec_nop 1012523 # number of nop insts executed +system.cpu1.iew.exec_refs 4881099 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2446532 # Number of branches executed +system.cpu1.iew.exec_stores 1845237 # Number of stores executed +system.cpu1.iew.exec_rate 0.590834 # Inst execution rate +system.cpu1.iew.wb_sent 15420680 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 15379390 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7566791 # num instructions producing a value +system.cpu1.iew.wb_consumers 10761562 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.598020 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.706006 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.583977 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.703131 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1065222 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 63848 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 75650 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 7939844 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.623951 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.560784 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2776166 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 197728 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 185190 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 23976589 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.630910 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.597118 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6043541 76.12% 76.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 925286 11.65% 87.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 320402 4.04% 91.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 190890 2.40% 94.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 129096 1.63% 95.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 57238 0.72% 96.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 65164 0.82% 97.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 44060 0.55% 97.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 164167 2.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 18550941 77.37% 77.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2272481 9.48% 86.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1151381 4.80% 91.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 578443 2.41% 94.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 385291 1.61% 95.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 189866 0.79% 96.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 157998 0.66% 97.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 143488 0.60% 97.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 546700 2.28% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 7939844 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 4954074 # Number of instructions committed -system.cpu1.commit.committedOps 4954074 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 23976589 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 15127070 # Number of instructions committed +system.cpu1.commit.committedOps 15127070 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1585273 # Number of memory references committed -system.cpu1.commit.loads 996375 # Number of loads committed -system.cpu1.commit.membars 16576 # Number of memory barriers committed -system.cpu1.commit.branches 700739 # Number of branches committed -system.cpu1.commit.fp_insts 31280 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 4632533 # Number of committed integer instructions. -system.cpu1.commit.function_calls 77324 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 191990 3.88% 3.88% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 2969211 59.93% 63.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 9565 0.19% 64.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.00% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8881 0.18% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.04% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1012951 20.45% 84.66% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 589031 11.89% 96.55% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 170686 3.45% 100.00% # Class of committed instruction +system.cpu1.commit.refs 4418203 # Number of memory references committed +system.cpu1.commit.loads 2674883 # Number of loads committed +system.cpu1.commit.membars 66521 # Number of memory barriers committed +system.cpu1.commit.branches 2263870 # Number of branches committed +system.cpu1.commit.fp_insts 115331 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 13957396 # Number of committed integer instructions. +system.cpu1.commit.function_calls 240978 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 845832 5.59% 5.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 9417463 62.26% 67.85% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 23911 0.16% 68.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.01% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 11769 0.08% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2741404 18.12% 86.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1743996 11.53% 97.75% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 340936 2.25% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 4954074 # Class of committed instruction -system.cpu1.commit.bw_lim_events 164167 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 15127070 # Class of committed instruction +system.cpu1.commit.bw_lim_events 546700 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 13715407 # The number of ROB reads -system.cpu1.rob.rob_writes 12215098 # The number of ROB writes -system.cpu1.timesIdled 57372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 519429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3803095502 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 4765602 # Number of Instructions Simulated -system.cpu1.committedOps 4765602 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.812413 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.812413 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551751 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551751 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 6848640 # number of integer regfile reads -system.cpu1.int_regfile_writes 3746417 # number of integer regfile writes -system.cpu1.fp_regfile_reads 21244 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19994 # number of floating regfile writes -system.cpu1.misc_regfile_reads 693471 # number of misc regfile reads -system.cpu1.misc_regfile_writes 115172 # number of misc regfile writes -system.cpu1.icache.tags.replacements 94727 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.369242 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 794363 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 95239 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.340732 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880860642000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.369242 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885487 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.885487 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 41251186 # The number of ROB reads +system.cpu1.rob.rob_writes 36287802 # The number of ROB writes +system.cpu1.timesIdled 194891 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1876968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3779240330 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 14284756 # Number of Instructions Simulated +system.cpu1.committedOps 14284756 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.843615 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.843615 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.542413 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.542413 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20099122 # number of integer regfile reads +system.cpu1.int_regfile_writes 11015819 # number of integer regfile writes +system.cpu1.fp_regfile_reads 63024 # number of floating regfile reads +system.cpu1.fp_regfile_writes 62672 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1065455 # number of misc regfile reads +system.cpu1.misc_regfile_writes 283847 # number of misc regfile writes +system.cpu1.icache.tags.replacements 353746 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.553851 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 2153244 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 354258 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.078180 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 47615844250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.553851 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985457 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.985457 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 989361 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 989361 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 794363 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 794363 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 794363 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 794363 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 794363 # number of overall hits -system.cpu1.icache.overall_hits::total 794363 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 99697 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 99697 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 99697 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 99697 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 99697 # number of overall misses -system.cpu1.icache.overall_misses::total 99697 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1381976879 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1381976879 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1381976879 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1381976879 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1381976879 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1381976879 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 894060 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 894060 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 894060 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 894060 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 894060 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 894060 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111510 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.111510 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111510 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.111510 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111510 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.111510 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13861.769953 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13861.769953 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13861.769953 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13861.769953 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2876460 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2876460 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 2153244 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2153244 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2153244 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2153244 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2153244 # number of overall hits +system.cpu1.icache.overall_hits::total 2153244 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 368891 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 368891 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 368891 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 368891 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 368891 # number of overall misses +system.cpu1.icache.overall_misses::total 368891 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5137931940 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5137931940 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5137931940 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5137931940 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5137931940 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5137931940 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2522135 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2522135 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2522135 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2522135 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2522135 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2522135 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146261 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.146261 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146261 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.146261 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146261 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.146261 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13928.049044 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13928.049044 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13928.049044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13928.049044 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1327 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.217391 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 24.127273 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 4396 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 4396 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 4396 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 4396 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 4396 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 4396 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 95301 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 95301 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 95301 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 95301 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 95301 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 95301 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1139734069 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1139734069 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1139734069 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1139734069 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1139734069 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1139734069 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106594 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.106594 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.106594 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14566 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 14566 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 14566 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 14566 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 14566 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 14566 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 354325 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 354325 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 354325 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 354325 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 354325 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 354325 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4259071697 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4259071697 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4259071697 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4259071697 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4259071697 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4259071697 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140486 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.140486 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.140486 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 45361 # number of replacements -system.cpu1.dcache.tags.tagsinuse 428.999436 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1451630 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 45680 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 31.778240 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1880566804000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.999436 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837890 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.837890 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 6609919 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 6609919 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 960992 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 960992 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 477143 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 477143 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 12504 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 12504 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 10799 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 10799 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1438135 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1438135 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1438135 # number of overall hits -system.cpu1.dcache.overall_hits::total 1438135 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 81302 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 81302 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 95545 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 95545 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1156 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1156 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 573 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 573 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 176847 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 176847 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 176847 # number of overall misses -system.cpu1.dcache.overall_misses::total 176847 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1110177095 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1110177095 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5046033431 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5046033431 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13905498 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 13905498 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4132075 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4132075 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6156210526 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6156210526 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6156210526 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6156210526 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1042294 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1042294 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 572688 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 572688 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 13660 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 13660 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11372 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 11372 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1614982 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1614982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1614982 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1614982 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078003 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.078003 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166836 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.166836 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084627 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084627 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050387 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050387 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.109504 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.109504 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.109504 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.109504 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7211.300175 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7211.300175 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 236601 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6165 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 38.378102 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360788 # number of replacements +system.cpu1.dcache.tags.tagsinuse 496.086183 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3613456 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 361109 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 10.006552 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 40126349500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.086183 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968918 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.968918 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18510307 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18510307 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2220866 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2220866 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1307515 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1307515 # 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number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8897 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 903784 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 903784 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 903784 # number of overall misses +system.cpu1.dcache.overall_misses::total 903784 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8191623763 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8191623763 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 14087810149 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 14087810149 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 135761491 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 135761491 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5726098 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5726098 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 22279433912 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 22279433912 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 22279433912 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 22279433912 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2745761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2745761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1686404 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1686404 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54261 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 54261 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 49669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4432165 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4432165 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4432165 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4432165 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.191166 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.191166 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224673 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.224673 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.163967 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.163967 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015825 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015825 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.203915 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.203915 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.203915 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.203915 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7285.111959 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7285.111959 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 560522 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 381 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 27149 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.646138 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 20.052632 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 24956 # number of writebacks -system.cpu1.dcache.writebacks::total 24956 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 46173 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 46173 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 80581 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 80581 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 235 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 235 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 126754 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 126754 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 126754 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 126754 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35129 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35129 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 14964 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 14964 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 921 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 921 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 573 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 573 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 50093 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 50093 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 50093 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 50093 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 398615352 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 398615352 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 730663501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 730663501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8358752 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8358752 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2984925 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2984925 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1129278853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1129278853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1129278853 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1129278853 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 533147000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 533147000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555544000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555544000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033704 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033704 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026129 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067423 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067423 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050387 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050387 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031018 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031018 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9075.735071 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9075.735071 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5209.293194 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5209.293194 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 273838 # number of writebacks +system.cpu1.dcache.writebacks::total 273838 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229504 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 229504 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 313811 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 313811 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1705 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1705 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 543315 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 543315 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 543315 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 543315 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 295391 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 295391 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65078 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65078 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7192 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7192 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 360469 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 360469 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 360469 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 360469 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3818838154 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3818838154 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2138006676 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2138006676 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81043507 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81043507 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4153902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4153902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5956844830 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5956844830 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5956844830 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5956844830 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 490391500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 490391500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 941927000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 941927000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1432318500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1432318500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038590 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038590 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132545 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.132545 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015825 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015825 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.081330 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.081330 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5284.862595 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5284.862595 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2087,161 +2082,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6410 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202830 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72673 40.72% 40.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.08% 41.87% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 103726 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178462 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71304 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.38% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.33% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71298 49.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144665 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863558813000 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63845500 0.00% 97.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565237000 0.03% 97.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 3385500 0.00% 97.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42015112000 2.20% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906206393000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981162 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4820 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 161850 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55184 39.67% 39.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 39.77% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.38% 41.15% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.16% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81844 58.84% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139099 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 54289 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.74% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54273 49.06% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 110633 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865924468000 98.05% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 60967000 0.00% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 531593000 0.03% 98.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8367000 0.00% 98.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36597541500 1.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903122936500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983782 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.687369 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810621 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.663127 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.795354 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed +system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 95 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3930 2.10% 2.15% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171605 91.48% 93.66% # number of callpals executed -system.cpu0.kern.callpal::rdps 6547 3.49% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rti 4793 2.56% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 187581 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7378 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::wripir 105 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2905 1.98% 2.05% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132721 90.43% 92.52% # number of callpals executed +system.cpu0.kern.callpal::rdps 6135 4.18% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rti 4306 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 146768 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6331 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1341 +system.cpu0.kern.mode_good::user 1342 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.185552 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.211815 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313100 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904135221500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2071163500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.349668 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901148119000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1974809500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3931 # number of times the context was actually changed +system.cpu0.kern.swap_context 2906 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2254 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 34590 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8916 31.91% 31.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 6.89% 38.80% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 95 0.34% 39.14% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17006 60.86% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 27942 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8908 45.12% 45.12% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 9.75% 54.88% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 95 0.48% 55.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8813 44.64% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 19741 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876395415500 98.45% 98.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531818000 0.03% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 44293500 0.00% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28895956000 1.52% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1905867483000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999103 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3853 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 75635 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26441 39.26% 39.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 2.85% 42.12% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 105 0.16% 42.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 38878 57.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 67346 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25959 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 3.57% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.20% 51.98% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25854 48.02% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53840 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1868834322000 98.22% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532397000 0.03% 98.24% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 48831000 0.00% 98.25% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33374320500 1.75% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1902789870500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981771 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.518229 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.706499 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.665003 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.799454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed +system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed +system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 298 1.04% 1.07% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.08% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.11% # number of callpals executed -system.cpu1.kern.callpal::swpipl 23527 82.20% 83.30% # number of callpals executed -system.cpu1.kern.callpal::rdps 2214 7.74% 91.04% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.04% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 91.05% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.06% # number of callpals executed -system.cpu1.kern.callpal::rti 2394 8.36% 99.43% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.42% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1334 1.92% 1.95% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 1.95% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.96% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62422 89.83% 91.80% # number of callpals executed +system.cpu1.kern.callpal::rdps 2621 3.77% 95.57% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.57% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.57% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.58% # number of callpals executed +system.cpu1.kern.callpal::rti 2896 4.17% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 28623 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 659 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2036 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 386 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 19 -system.cpu1.kern.mode_switch_good::kernel 0.585736 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 69486 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1712 # number of protection mode switches +system.cpu1.kern.mode_switch::user 395 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2056 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 462 +system.cpu1.kern.mode_good::user 395 +system.cpu1.kern.mode_good::idle 67 +system.cpu1.kern.mode_switch_good::kernel 0.269860 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.009332 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.252123 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1444110500 0.08% 0.08% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 692193000 0.04% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1903401131500 99.89% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 299 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.032588 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.221955 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 38841912000 2.04% 2.04% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 712477500 0.04% 2.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862932175500 97.92% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1335 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |