diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1992 |
1 files changed, 998 insertions, 994 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 44e9b2e2b..aba3b9944 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859049 # Number of seconds simulated -sim_ticks 1859049148500 # Number of ticks simulated -final_tick 1859049148500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859045 # Number of seconds simulated +sim_ticks 1859045389000 # Number of ticks simulated +final_tick 1859045389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168870 # Simulator instruction rate (inst/s) -host_op_rate 168870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5931192571 # Simulator tick rate (ticks/s) -host_mem_usage 320216 # Number of bytes of host memory used -host_seconds 313.44 # Real time elapsed on the host -sim_insts 52930035 # Number of instructions simulated -sim_ops 52930035 # Number of ops (including micro ops) simulated +host_inst_rate 155751 # Simulator instruction rate (inst/s) +host_op_rate 155751 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5470499619 # Simulator tick rate (ticks/s) +host_mem_usage 374716 # Number of bytes of host memory used +host_seconds 339.83 # Real time elapsed on the host +sim_insts 52929026 # Number of instructions simulated +sim_ops 52929026 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 968128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24876416 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388684 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25845504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15127 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388694 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13380914 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117450 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117450 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13381285 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13901679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13380914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13902567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043366 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043366 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13381285 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17944726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403811 # Number of read requests accepted -system.physmem.writeReqs 158993 # Number of write requests accepted -system.physmem.readBursts 403811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158993 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25836928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 10037376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10175552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2130 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write +system.physmem.bw_total::total 17945933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403836 # Number of read requests accepted +system.physmem.writeReqs 159002 # Number of write requests accepted +system.physmem.readBursts 403836 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159002 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25838848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 10042304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25845504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10176128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2068 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 208 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25744 # Per bank write bursts -system.physmem.perBankRdBursts::1 25560 # Per bank write bursts -system.physmem.perBankRdBursts::2 25512 # Per bank write bursts -system.physmem.perBankRdBursts::3 25342 # Per bank write bursts -system.physmem.perBankRdBursts::4 25388 # Per bank write bursts -system.physmem.perBankRdBursts::5 24802 # Per bank write bursts -system.physmem.perBankRdBursts::6 25022 # Per bank write bursts -system.physmem.perBankRdBursts::7 25128 # Per bank write bursts -system.physmem.perBankRdBursts::8 24929 # Per bank write bursts -system.physmem.perBankRdBursts::9 25033 # Per bank write bursts -system.physmem.perBankRdBursts::10 25435 # Per bank write bursts -system.physmem.perBankRdBursts::11 24778 # Per bank write bursts -system.physmem.perBankRdBursts::12 24542 # Per bank write bursts -system.physmem.perBankRdBursts::13 25239 # Per bank write bursts -system.physmem.perBankRdBursts::14 25649 # Per bank write bursts -system.physmem.perBankRdBursts::15 25599 # Per bank write bursts -system.physmem.perBankWrBursts::0 10531 # Per bank write bursts -system.physmem.perBankWrBursts::1 10049 # Per bank write bursts -system.physmem.perBankWrBursts::2 10576 # Per bank write bursts -system.physmem.perBankWrBursts::3 9740 # Per bank write bursts -system.physmem.perBankWrBursts::4 9614 # Per bank write bursts -system.physmem.perBankWrBursts::5 9115 # Per bank write bursts -system.physmem.perBankWrBursts::6 9087 # Per bank write bursts -system.physmem.perBankWrBursts::7 8933 # Per bank write bursts -system.physmem.perBankWrBursts::8 9694 # Per bank write bursts -system.physmem.perBankWrBursts::9 8895 # Per bank write bursts -system.physmem.perBankWrBursts::10 9699 # Per bank write bursts -system.physmem.perBankWrBursts::11 9449 # Per bank write bursts -system.physmem.perBankWrBursts::12 10004 # Per bank write bursts +system.physmem.perBankRdBursts::1 25557 # Per bank write bursts +system.physmem.perBankRdBursts::2 25510 # Per bank write bursts +system.physmem.perBankRdBursts::3 25348 # Per bank write bursts +system.physmem.perBankRdBursts::4 25387 # Per bank write bursts +system.physmem.perBankRdBursts::5 24799 # Per bank write bursts +system.physmem.perBankRdBursts::6 25027 # Per bank write bursts +system.physmem.perBankRdBursts::7 25129 # Per bank write bursts +system.physmem.perBankRdBursts::8 24928 # Per bank write bursts +system.physmem.perBankRdBursts::9 25032 # Per bank write bursts +system.physmem.perBankRdBursts::10 25436 # Per bank write bursts +system.physmem.perBankRdBursts::11 24784 # Per bank write bursts +system.physmem.perBankRdBursts::12 24551 # Per bank write bursts +system.physmem.perBankRdBursts::13 25235 # Per bank write bursts +system.physmem.perBankRdBursts::14 25659 # Per bank write bursts +system.physmem.perBankRdBursts::15 25606 # Per bank write bursts +system.physmem.perBankWrBursts::0 10485 # Per bank write bursts +system.physmem.perBankWrBursts::1 10108 # Per bank write bursts +system.physmem.perBankWrBursts::2 10574 # Per bank write bursts +system.physmem.perBankWrBursts::3 9632 # Per bank write bursts +system.physmem.perBankWrBursts::4 9668 # Per bank write bursts +system.physmem.perBankWrBursts::5 9137 # Per bank write bursts +system.physmem.perBankWrBursts::6 9064 # Per bank write bursts +system.physmem.perBankWrBursts::7 8900 # Per bank write bursts +system.physmem.perBankWrBursts::8 9821 # Per bank write bursts +system.physmem.perBankWrBursts::9 8750 # Per bank write bursts +system.physmem.perBankWrBursts::10 9677 # Per bank write bursts +system.physmem.perBankWrBursts::11 9460 # Per bank write bursts +system.physmem.perBankWrBursts::12 10019 # Per bank write bursts system.physmem.perBankWrBursts::13 10709 # Per bank write bursts -system.physmem.perBankWrBursts::14 10413 # Per bank write bursts -system.physmem.perBankWrBursts::15 10326 # Per bank write bursts +system.physmem.perBankWrBursts::14 10502 # Per bank write bursts +system.physmem.perBankWrBursts::15 10405 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 1859043836000 # Total gap between requests +system.physmem.totGap 1859040142000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403811 # Read request sizes (log2) +system.physmem.readPktSize::6 403836 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 158993 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314947 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159002 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314988 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -148,120 +148,119 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 562.390130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 348.747922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.715872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13502 21.17% 21.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10319 16.18% 37.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4795 7.52% 44.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2857 4.48% 49.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2332 3.66% 53.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1655 2.59% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1501 2.35% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1587 2.49% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25241 39.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63789 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5661 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.309309 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2806.420357 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5658 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63696 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 563.318764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 349.809758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.596932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13378 21.00% 21.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10306 16.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4860 7.63% 44.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2855 4.48% 49.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2272 3.57% 52.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1671 2.62% 55.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1518 2.38% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1616 2.54% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25220 39.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63696 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.190619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2803.945627 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5668 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5661 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5661 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.704293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.909682 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.456612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4621 81.63% 81.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 191 3.37% 85.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 281 4.96% 89.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 54 0.95% 90.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 96 1.70% 92.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 48 0.85% 93.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.30% 93.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 14 0.25% 94.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.34% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 15 0.26% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 5 0.09% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 19 0.34% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 42 0.74% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 21 0.37% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 11 0.19% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 96 1.70% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 35 0.62% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 14 0.25% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 13 0.23% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.18% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 6 0.11% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5661 # Writes before turning the bus around for reads -system.physmem.totQLat 3666880250 # Total ticks spent queuing -system.physmem.totMemAccLat 11236292750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9083.14 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5671 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5671 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.669018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.928355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.069194 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4623 81.52% 81.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 171 3.02% 84.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 302 5.33% 89.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 63 1.11% 90.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 97 1.71% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 43 0.76% 93.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 19 0.34% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 6 0.11% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 22 0.39% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.30% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 6 0.11% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 18 0.32% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 43 0.76% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 8 0.14% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 17 0.30% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 89 1.57% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 36 0.63% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 17 0.30% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 22 0.39% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 13 0.23% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 5 0.09% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5671 # Writes before turning the bus around for reads +system.physmem.totQLat 3621320000 # Total ticks spent queuing +system.physmem.totMemAccLat 11191295000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8969.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27833.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27719.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s @@ -270,67 +269,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing -system.physmem.readRowHits 364667 # Number of row buffer hits during reads -system.physmem.writeRowHits 132080 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.20 # Row buffer hit rate for writes -system.physmem.avgGap 3303181.63 # Average gap between requests -system.physmem.pageHitRate 88.62 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1760890123500 # Time in different power states -system.physmem.memoryStateTime::REF 62077600000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 36077600250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 239795640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 242449200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 130840875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132288750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1579484400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1569391200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 503139600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 513144720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 55719498420 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 55486362150 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1066550433000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1066754938500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1246146977535 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1246122360120 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.315549 # Core power per rank (mW) -system.physmem.averagePower::1 670.302307 # Core power per rank (mW) -system.cpu.branchPred.lookups 17761302 # Number of BP lookups -system.cpu.branchPred.condPredicted 15456576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379954 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12009119 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5937139 # Number of BTB hits +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.54 # Average write queue length when enqueuing +system.physmem.readRowHits 364717 # Number of row buffer hits during reads +system.physmem.writeRowHits 132230 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes +system.physmem.avgGap 3302975.53 # Average gap between requests +system.physmem.pageHitRate 88.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239009400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130411875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579507800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 502640640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 55671864660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1066592208750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1246139428725 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.311493 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1774205493250 # Time in different power states +system.physmem_0.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22762216750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 242532360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 132334125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1569601800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 514142640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 55569327930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1066682161500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1246133885955 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.308507 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1774360012750 # Time in different power states +system.physmem_1.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22607711000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 17755011 # Number of BP lookups +system.cpu.branchPred.condPredicted 15447257 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 380557 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11928628 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5915753 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.438589 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 914399 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21305 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 49.592904 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 917507 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21428 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10308188 # DTB read hits -system.cpu.dtb.read_misses 41379 # DTB read misses -system.cpu.dtb.read_acv 521 # DTB read access violations -system.cpu.dtb.read_accesses 967155 # DTB read accesses -system.cpu.dtb.write_hits 6646702 # DTB write hits -system.cpu.dtb.write_misses 9325 # DTB write misses -system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 342603 # DTB write accesses -system.cpu.dtb.data_hits 16954890 # DTB hits -system.cpu.dtb.data_misses 50704 # DTB misses -system.cpu.dtb.data_acv 931 # DTB access violations -system.cpu.dtb.data_accesses 1309758 # DTB accesses -system.cpu.itb.fetch_hits 1770443 # ITB hits -system.cpu.itb.fetch_misses 36092 # ITB misses -system.cpu.itb.fetch_acv 664 # ITB acv -system.cpu.itb.fetch_accesses 1806535 # ITB accesses +system.cpu.dtb.read_hits 10297861 # DTB read hits +system.cpu.dtb.read_misses 41459 # DTB read misses +system.cpu.dtb.read_acv 502 # DTB read access violations +system.cpu.dtb.read_accesses 968382 # DTB read accesses +system.cpu.dtb.write_hits 6648165 # DTB write hits +system.cpu.dtb.write_misses 9537 # DTB write misses +system.cpu.dtb.write_acv 407 # DTB write access violations +system.cpu.dtb.write_accesses 342637 # DTB write accesses +system.cpu.dtb.data_hits 16946026 # DTB hits +system.cpu.dtb.data_misses 50996 # DTB misses +system.cpu.dtb.data_acv 909 # DTB access violations +system.cpu.dtb.data_accesses 1311019 # DTB accesses +system.cpu.itb.fetch_hits 1769037 # ITB hits +system.cpu.itb.fetch_misses 35976 # ITB misses +system.cpu.itb.fetch_acv 675 # ITB acv +system.cpu.itb.fetch_accesses 1805013 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -343,256 +347,256 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118298016 # number of cpu cycles simulated +system.cpu.numCycles 118253854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29541198 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78055768 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17761302 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6851538 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80476428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1253224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1384 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1737629 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 451562 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9019799 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273133 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 29528041 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78024704 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17755011 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6833260 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80443267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1255548 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1917 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1737879 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 457742 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9020958 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 272859 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112863592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.691594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.010851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 112824612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.691557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.011053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98289284 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 935566 0.83% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1976201 1.75% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 911928 0.81% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2795335 2.48% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 642698 0.57% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 727750 0.64% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007954 0.89% 95.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5576876 4.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98261708 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 933543 0.83% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1973411 1.75% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 908515 0.81% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2794922 2.48% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 638903 0.57% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 728605 0.65% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007079 0.89% 95.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5577926 4.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112863592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150140 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.659823 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24058379 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76821722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9496623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1902660 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 584207 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 588094 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68303161 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 133250 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 584207 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24982800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47259981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20734687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10387203 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8914712 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65869472 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 202922 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2041149 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 141248 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4766165 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43946104 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79818079 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79637315 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168311 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38139253 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5806843 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1691151 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241440 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13536828 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10424364 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6928356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1483959 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1059889 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58630025 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2138995 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57603342 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50950 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7503583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3485287 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1477804 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112863592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.510380 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.252962 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 112824612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150143 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.659807 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24062318 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76790103 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9490656 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1896068 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 585466 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586954 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42767 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68209057 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130935 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 585466 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24987088 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 47248716 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20734654 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10372019 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8896667 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65782894 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 200446 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2040001 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 143212 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4746299 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43863584 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79748694 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79567373 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168869 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38138490 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5725086 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1691130 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13583154 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10423192 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6953251 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1496634 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1073096 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58558441 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2136854 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57535876 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 59225 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7428094 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503981 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1475675 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 112824612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.509959 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.252016 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89383207 79.20% 79.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10013548 8.87% 88.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4301377 3.81% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2962557 2.62% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3086274 2.73% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1586017 1.41% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1012124 0.90% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 396460 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 122028 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89346173 79.19% 79.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10029271 8.89% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4305402 3.82% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2956038 2.62% 94.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3073019 2.72% 97.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1592834 1.41% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1003723 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 396113 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 122039 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112863592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 112824612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 213045 18.77% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547519 48.24% 67.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 374446 32.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206156 18.23% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547934 48.46% 66.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 376604 33.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39102059 67.88% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61815 0.11% 68.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38377 0.07% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10718615 18.61% 86.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722522 11.67% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949032 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39037949 67.85% 67.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61847 0.11% 67.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38375 0.07% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10709010 18.61% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6728743 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949030 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57603342 # Type of FU issued -system.cpu.iq.rate 0.486934 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1135010 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019704 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228544022 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67957775 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55921178 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712213 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 334464 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328973 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58348779 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382287 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 639736 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57535876 # Type of FU issued +system.cpu.iq.rate 0.486545 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1130694 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019652 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228371695 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67806986 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55854530 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 714587 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336328 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329574 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58275622 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 383662 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 641458 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1339690 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4038 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 554552 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1338736 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3932 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20392 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 579549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18285 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 544771 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18260 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537508 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 584207 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44318330 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 613096 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64473181 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145267 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10424364 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6928356 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890724 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42751 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 366947 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 190952 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410451 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 601403 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57018878 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10377294 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 584463 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 585466 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44292826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 620223 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64391845 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145304 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10423192 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6953251 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1888969 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42563 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 374293 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20392 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 192990 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410068 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 603058 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56949005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10367007 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586870 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3704161 # number of nop insts executed -system.cpu.iew.exec_refs 17048455 # number of memory reference insts executed -system.cpu.iew.exec_branches 8982580 # Number of branches executed -system.cpu.iew.exec_stores 6671161 # Number of stores executed -system.cpu.iew.exec_rate 0.481994 # Inst execution rate -system.cpu.iew.wb_sent 56384919 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56250151 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28947314 # num instructions producing a value -system.cpu.iew.wb_consumers 40326252 # num instructions consuming a value +system.cpu.iew.exec_nop 3696550 # number of nop insts executed +system.cpu.iew.exec_refs 17039818 # number of memory reference insts executed +system.cpu.iew.exec_branches 8972525 # Number of branches executed +system.cpu.iew.exec_stores 6672811 # Number of stores executed +system.cpu.iew.exec_rate 0.481583 # Inst execution rate +system.cpu.iew.wb_sent 56323297 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56184104 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28889312 # num instructions producing a value +system.cpu.iew.wb_consumers 40263081 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475495 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717828 # average fanout of values written-back +system.cpu.iew.wb_rate 0.475114 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717514 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8239076 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661191 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 548552 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111427799 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503633 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.455266 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8158001 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661179 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 549251 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111396128 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.503767 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.456242 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91796177 82.38% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7808087 7.01% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4129534 3.71% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2155296 1.93% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1855711 1.67% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615462 0.55% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 470761 0.42% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 513166 0.46% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2083605 1.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91779533 82.39% 82.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7802293 7.00% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4122327 3.70% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2151634 1.93% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1854051 1.66% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 612708 0.55% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 470628 0.42% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 511278 0.46% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2091676 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111427799 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56118765 # Number of instructions committed -system.cpu.commit.committedOps 56118765 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111396128 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56117715 # Number of instructions committed +system.cpu.commit.committedOps 56117715 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15458478 # Number of memory references committed -system.cpu.commit.loads 9084674 # Number of loads committed -system.cpu.commit.membars 226351 # Number of memory barriers committed -system.cpu.commit.branches 8434924 # Number of branches committed -system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51970227 # Number of committed integer instructions. -system.cpu.commit.function_calls 739937 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3196003 5.70% 5.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36180557 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60666 0.11% 70.27% # Class of committed instruction +system.cpu.commit.refs 15458158 # Number of memory references committed +system.cpu.commit.loads 9084456 # Number of loads committed +system.cpu.commit.membars 226347 # Number of memory barriers committed +system.cpu.commit.branches 8434758 # Number of branches committed +system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.int_insts 51969244 # Number of committed integer instructions. +system.cpu.commit.function_calls 739915 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3195962 5.70% 5.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36179881 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60661 0.11% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction @@ -618,192 +622,192 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9311025 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6379757 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949032 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9310803 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6379655 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949030 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56118765 # Class of committed instruction -system.cpu.commit.bw_lim_events 2083605 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56117715 # Class of committed instruction +system.cpu.commit.bw_lim_events 2091676 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173452486 # The number of ROB reads -system.cpu.rob.rob_writes 130147702 # The number of ROB writes -system.cpu.timesIdled 575947 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5434424 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599800282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52930035 # Number of Instructions Simulated -system.cpu.committedOps 52930035 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.234988 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.234988 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447430 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447430 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74659793 # number of integer regfile reads -system.cpu.int_regfile_writes 40587610 # number of integer regfile writes -system.cpu.fp_regfile_reads 166949 # number of floating regfile reads -system.cpu.fp_regfile_writes 167607 # number of floating regfile writes -system.cpu.misc_regfile_reads 2029497 # number of misc regfile reads -system.cpu.misc_regfile_writes 939434 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1404580 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994645 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11874772 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1405092 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.451242 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 173330307 # The number of ROB reads +system.cpu.rob.rob_writes 129976168 # The number of ROB writes +system.cpu.timesIdled 574999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5429242 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599836925 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52929026 # Number of Instructions Simulated +system.cpu.committedOps 52929026 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.234197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.234197 # CPI: Total CPI of All Threads +system.cpu.ipc 0.447588 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.447588 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74582639 # number of integer regfile reads +system.cpu.int_regfile_writes 40531859 # number of integer regfile writes +system.cpu.fp_regfile_reads 167323 # number of floating regfile reads +system.cpu.fp_regfile_writes 167888 # number of floating regfile writes +system.cpu.misc_regfile_reads 2030592 # number of misc regfile reads +system.cpu.misc_regfile_writes 939419 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1404198 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994647 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11876238 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404710 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.454584 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994645 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994647 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63937777 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63937777 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7284414 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7284414 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4188003 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4188003 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186359 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186359 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215726 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215726 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11472417 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11472417 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11472417 # number of overall hits -system.cpu.dcache.overall_hits::total 11472417 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1780024 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1780024 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1955346 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1955346 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23271 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23271 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 63918355 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63918355 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7286393 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7286393 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4187319 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4187319 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186500 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186500 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215720 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215720 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11473712 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11473712 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11473712 # number of overall hits +system.cpu.dcache.overall_hits::total 11473712 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1773211 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1773211 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1955934 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1955934 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23306 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23306 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3735370 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3735370 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3735370 # number of overall misses -system.cpu.dcache.overall_misses::total 3735370 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39520730746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39520730746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 78084026192 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 78084026192 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364876749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 364876749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 441006 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 441006 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117604756938 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117604756938 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117604756938 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117604756938 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9064438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9064438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6143349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6143349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209630 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209630 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15207787 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15207787 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15207787 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15207787 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196374 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.196374 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111010 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3729145 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3729145 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3729145 # number of overall misses +system.cpu.dcache.overall_misses::total 3729145 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39410540501 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39410540501 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77932908678 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77932908678 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 363692999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 363692999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 466008 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 466008 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117343449179 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117343449179 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117343449179 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117343449179 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9059604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9059604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6143253 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6143253 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209806 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209806 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215748 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215748 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15202857 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15202857 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15202857 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15202857 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195727 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.195727 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318387 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318387 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111084 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111084 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245622 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245622 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245622 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245622 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22202.358365 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22202.358365 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39933.610825 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39933.610825 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15679.461519 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15679.461519 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15750.214286 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15750.214286 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31484.098480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31484.098480 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3992388 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1705 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 180260 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.147942 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.041667 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.245292 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245292 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245292 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245292 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31466.582602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31466.582602 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3975824 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1887 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 179816 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.110513 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82.043478 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842675 # number of writebacks -system.cpu.dcache.writebacks::total 842675 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683874 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 683874 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664228 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664228 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5276 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5276 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2348102 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2348102 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2348102 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2348102 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096150 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1096150 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291118 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291118 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17995 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17995 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 842396 # number of writebacks +system.cpu.dcache.writebacks::total 842396 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 677447 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 677447 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664842 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664842 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5278 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5278 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2342289 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2342289 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2342289 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2342289 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095764 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1095764 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291092 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291092 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18028 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18028 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1387268 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1387268 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1387268 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1387268 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27519652282 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27519652282 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11779193020 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11779193020 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204738251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204738251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 384994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 384994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39298845302 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39298845302 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39298845302 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39298845302 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423580000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423580000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999637498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999637498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423217498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423217498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085842 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085842 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27504145773 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27504145773 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11747551273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11747551273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205106501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205106501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 409992 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 409992 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39251697046 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39251697046 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39251697046 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39251697046 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423712500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423712500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999632498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999632498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423344998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423344998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047384 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047384 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085927 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25105.735786 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25105.735786 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40461.919290 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40461.919290 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.507697 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.507697 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13749.785714 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13749.785714 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091223 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091223 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25100.428352 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25100.428352 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40356.833142 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40356.833142 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.107888 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.107888 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14642.571429 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14642.571429 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -811,213 +815,213 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1035530 # number of replacements -system.cpu.icache.tags.tagsinuse 509.402349 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7932375 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1036038 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.656452 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.402349 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1034381 # number of replacements +system.cpu.icache.tags.tagsinuse 509.395054 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7933874 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1034889 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.666401 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26421984250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.395054 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994912 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10056088 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10056088 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7932376 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7932376 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7932376 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7932376 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7932376 # number of overall hits -system.cpu.icache.overall_hits::total 7932376 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1087421 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1087421 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1087421 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1087421 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1087421 # number of overall misses -system.cpu.icache.overall_misses::total 1087421 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15131971529 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15131971529 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15131971529 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15131971529 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15131971529 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15131971529 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9019797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9019797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9019797 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9019797 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9019797 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9019797 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13915.467449 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13915.467449 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13915.467449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13915.467449 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5307 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10056110 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10056110 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7933875 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7933875 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7933875 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7933875 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7933875 # number of overall hits +system.cpu.icache.overall_hits::total 7933875 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1087081 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1087081 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1087081 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1087081 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1087081 # number of overall misses +system.cpu.icache.overall_misses::total 1087081 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15110067823 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15110067823 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15110067823 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15110067823 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15110067823 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15110067823 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9020956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9020956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9020956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9020956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9020956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9020956 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120506 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120506 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120506 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120506 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120506 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120506 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13899.670607 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13899.670607 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13899.670607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13899.670607 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3991 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.808743 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51130 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 51130 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 51130 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 51130 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 51130 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 51130 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1036291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1036291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1036291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1036291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1036291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1036291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12436978135 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12436978135 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12436978135 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12436978135 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12436978135 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12436978135 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114891 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114891 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114891 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12001.434090 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12001.434090 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12001.434090 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12001.434090 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12001.434090 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12001.434090 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51927 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 51927 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 51927 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 51927 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 51927 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 51927 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035154 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1035154 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1035154 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1035154 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1035154 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1035154 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12419429847 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12419429847 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12419429847 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12419429847 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12419429847 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12419429847 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114750 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114750 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114750 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11997.663968 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11997.663968 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338304 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65336.722890 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2576408 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403470 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.385625 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 338332 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65337.269998 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2574624 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403501 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.380713 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53740.358806 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.050861 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.313222 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.820013 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081498 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095449 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 494 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3329 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55432 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26978409 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26978409 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1021005 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 829436 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1850441 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 842675 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 842675 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 32 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186561 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186561 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1021005 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1015997 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037002 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1021005 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1015997 # number of overall hits -system.cpu.l2cache.overall_hits::total 2037002 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15114 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273817 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288931 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 47 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 47 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115372 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115372 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389189 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404303 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389189 # number of overall misses -system.cpu.l2cache.overall_misses::total 404303 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1159992750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17995310250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19155303000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 355494 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 355494 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92496 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92496 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9679121611 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9679121611 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1159992750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27674431861 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28834424611 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1159992750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27674431861 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28834424611 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1036119 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1103253 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2139372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 842675 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 842675 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.tags.occ_blocks::writebacks 53714.137748 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5350.111230 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6273.021020 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.819613 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081636 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996968 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 498 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3501 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26963891 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26963891 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1019836 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 829079 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1848915 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 842396 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 842396 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 20 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186519 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186519 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1019836 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1015598 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2035434 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1019836 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1015598 # number of overall hits +system.cpu.l2cache.overall_hits::total 2035434 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15129 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288952 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 57 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 57 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 8 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115376 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15129 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389199 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404328 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15129 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389199 # number of overall misses +system.cpu.l2cache.overall_misses::total 404328 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1155504000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17984856500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19140360500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331495 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 331495 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92996 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92996 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647937355 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9647937355 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1155504000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27632793855 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28788297855 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1155504000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27632793855 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28788297855 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1034965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1102902 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2137867 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 842396 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 842396 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 88 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301933 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301933 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1036119 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1405186 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2441305 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1036119 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1405186 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2441305 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014587 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248191 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.135054 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.594937 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.594937 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382111 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382111 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014587 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276966 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165609 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014587 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276966 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165609 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76749.553394 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65720.208205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66297.153992 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7563.702128 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7563.702128 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 15416 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 15416 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83894.893137 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83894.893137 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76749.553394 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71107.949765 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71318.849009 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76749.553394 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71107.949765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71318.849009 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301895 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301895 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1034965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1404797 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2439762 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1034965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1404797 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2439762 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014618 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248275 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.135159 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.647727 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.647727 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382173 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014618 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277050 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.165724 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014618 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277050 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.165724 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76376.759865 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65680.591112 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66240.623010 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5815.701754 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5815.701754 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11624.500000 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11624.500000 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83621.700830 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83621.700830 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71200.356777 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71200.356777 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1026,80 +1030,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks -system.cpu.l2cache.writebacks::total 75929 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks +system.cpu.l2cache.writebacks::total 75938 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273817 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288930 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 47 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 47 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115372 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115372 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389189 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404302 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389189 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404302 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 969372000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14584664250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15554036250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 622542 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 622542 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 60006 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8273073889 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8273073889 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 969372000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22857738139 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23827110139 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 969372000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22857738139 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23827110139 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333490000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333490000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884459000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884459000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217949000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217949000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135054 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.594937 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.594937 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276966 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165609 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276966 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165609 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64141.599947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53264.275958 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53833.233828 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13245.574468 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13245.574468 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15128 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288951 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 57 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 57 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15128 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389199 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404327 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15128 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389199 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404327 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964671250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14573298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15537969750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 720554 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 720554 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80008 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80008 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8241634145 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8241634145 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 964671250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22814932645 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23779603895 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 964671250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22814932645 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23779603895 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333622500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333622500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884454000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884454000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218076500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218076500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.647727 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.647727 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382173 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382173 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165724 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165724 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63767.269302 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53221.601180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53773.718554 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 12641.298246 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 12641.298246 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71707.813759 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71707.813759 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71432.829575 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71432.829575 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1107,43 +1111,43 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2146647 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2146537 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2145159 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2145056 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 842675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 842396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 88 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 93 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2072410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686471 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5758881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66311616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143911276 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210222892 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42053 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3325984 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111300 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 86 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2070119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3685432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5755551 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66237760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143868972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210106732 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42071 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3324189 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012552 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111331 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3284259 98.75% 98.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3282463 98.74% 98.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 1.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3325984 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2497867498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3324189 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2496690997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1558461609 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1556745400 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189866891 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2189304171 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1216,23 +1220,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406221775 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406216778 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010536 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42011283 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260575 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.260535 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709355371000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260575 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078786 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078786 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1709356303000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260535 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078783 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078783 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1248,8 +1252,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13648838856 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13648838856 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13645647112 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13645647112 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles @@ -1272,17 +1276,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328476.098768 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328476.098768 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206574 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206436 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23538 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23523 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.776192 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.775921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1298,8 +1302,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11488062928 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11488062928 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11484876678 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11484876678 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles @@ -1314,60 +1318,60 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276474.367732 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276474.367732 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296033 # Transaction distribution -system.membus.trans_dist::ReadResp 295940 # Transaction distribution +system.membus.trans_dist::ReadReq 296054 # Transaction distribution +system.membus.trans_dist::ReadResp 295968 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117441 # Transaction distribution +system.membus.trans_dist::Writeback 117450 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 186 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 192 # Transaction distribution -system.membus.trans_dist::ReadExReq 115233 # Transaction distribution -system.membus.trans_dist::ReadExResp 115233 # Transaction distribution -system.membus.trans_dist::BadAddressError 93 # Transaction distribution +system.membus.trans_dist::UpgradeReq 203 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.membus.trans_dist::UpgradeResp 211 # Transaction distribution +system.membus.trans_dist::ReadExReq 115230 # Transaction distribution +system.membus.trans_dist::ReadExResp 115230 # Transaction distribution +system.membus.trans_dist::BadAddressError 86 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 186 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917499 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042303 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30748716 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36063596 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36065772 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 563522 # Request fanout histogram +system.membus.snoop_fanout::samples 563568 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 563522 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 563568 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 563522 # Request fanout histogram -system.membus.reqLayer0.occupancy 31470000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 563568 # Request fanout histogram +system.membus.reqLayer0.occupancy 31570500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1857946999 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1858044250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 115000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 107000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3754266813 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3754720043 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43145464 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43142717 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1401,28 +1405,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211002 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105561 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105562 57.93% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817339213500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61863500 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 521835500 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41125418500 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859048331000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817332157500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 61952500 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 528077500 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41122369500 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859044557000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694338 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815440 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815429 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1458,10 +1462,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175118 91.22% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175118 91.23% 93.44% # number of callpals executed system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1470,20 +1474,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191963 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.callpal::total 191962 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::user 1743 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1743 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326499 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326953 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394468 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29096339500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2660038000 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827291945500 98.29% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394840 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29081819500 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2655993500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827306736000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |