diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3 | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3')
3 files changed, 351 insertions, 405 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index c884dc482..ecd4c00a8 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -11,14 +11,14 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -152,20 +152,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -451,20 +444,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -499,7 +485,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -519,7 +505,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -548,20 +534,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -580,20 +559,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -647,7 +619,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 0ab209212..c3587ff5d 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,14 +1,11 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 3 2012 13:46:22 -gem5 started Feb 3 2012 13:46:34 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:47:47 +gem5 executing on zizzer +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1859850554500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 44b3ca581..3b4a45a9b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.859851 # Nu sim_ticks 1859850554500 # Number of ticks simulated final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100457 # Simulator instruction rate (inst/s) -host_tick_rate 3519496587 # Simulator tick rate (ticks/s) -host_mem_usage 323652 # Number of bytes of host memory used -host_seconds 528.44 # Real time elapsed on the host +host_inst_rate 188989 # Simulator instruction rate (inst/s) +host_op_rate 188989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6621174751 # Simulator tick rate (ticks/s) +host_mem_usage 292896 # Number of bytes of host memory used +host_seconds 280.89 # Real time elapsed on the host sim_insts 53085804 # Number of instructions simulated +sim_ops 53085804 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29820864 # Number of bytes read from this memory system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory system.physmem.bytes_written 10193536 # Number of bytes written to this memory @@ -25,83 +27,89 @@ system.l2c.total_refs 2406767 # To system.l2c.sampled_refs 424249 # Sample count of references to valid blocks. system.l2c.avg_refs 5.673006 # Average number of references to valid blocks. system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12305.465353 # Average occupied blocks per context -system.l2c.occ_blocks::1 22620.354669 # Average occupied blocks per context -system.l2c.occ_percent::0 0.187767 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.345159 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1800764 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.532926 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 988583 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 812181 # number of ReadReq hits system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits -system.l2c.Writeback_hits::0 835189 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 835189 # number of Writeback hits system.l2c.Writeback_hits::total 835189 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183241 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 183241 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits -system.l2c.demand_hits::0 1984005 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 988583 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 995422 # number of demand (read+write) hits system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits -system.l2c.overall_hits::0 1984005 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::cpu.inst 988583 # number of overall hits +system.l2c.overall_hits::cpu.data 995422 # number of overall hits system.l2c.overall_hits::total 1984005 # number of overall hits -system.l2c.ReadReq_misses::0 308137 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 16626 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 291511 # number of ReadReq misses system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 35 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116889 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 116889 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses -system.l2c.demand_misses::0 425026 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 16626 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 408400 # number of demand (read+write) misses system.l2c.demand_misses::total 425026 # number of demand (read+write) misses -system.l2c.overall_misses::0 425026 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::cpu.inst 16626 # number of overall misses +system.l2c.overall_misses::cpu.data 408400 # number of overall misses system.l2c.overall_misses::total 425026 # number of overall misses -system.l2c.ReadReq_miss_latency 16037812500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 424500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6132457500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22170270000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22170270000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2108901 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.inst 869674000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 15168138500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 16037812500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 424500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 424500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6132457500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6132457500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 869674000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 21300596000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22170270000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 869674000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 21300596000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22170270000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1005209 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1103692 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835189 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835189 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 51 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 51 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300130 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 300130 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2409031 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1005209 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1403822 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2409031 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1005209 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1403822 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146113 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.686275 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389461 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176430 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176430 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52047.668732 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 12128.571429 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52463.940148 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52162.150080 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52162.150080 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.264124 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.686275 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.389461 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.290920 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.290920 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -110,48 +118,59 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117762 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308137 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116889 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 425026 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 425026 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12334071500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1460000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4711233500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17045305000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17045305000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 809589500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1114928998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1924518498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146113 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.686275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389461 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176430 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176430 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40027.882078 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41714.285714 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40305.191250 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 117762 # number of writebacks +system.l2c.writebacks::total 117762 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 16626 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 291511 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 308137 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 116889 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116889 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16626 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 408400 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 425026 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16626 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 408400 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 425026 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 666148500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 11667923000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 12334071500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1460000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1460000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4711233500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4711233500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 666148500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 16379156500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17045305000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 666148500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 16379156500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17045305000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809589500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 809589500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114928998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1114928998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924518498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1924518498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264124 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.686275 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389461 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.276011 # Cycle average of tags in use @@ -159,58 +178,41 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.276011 # Average occupied blocks per context -system.iocache.occ_percent::1 0.079751 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.occ_blocks::tsunami.ide 1.276011 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079751 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079751 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5721891806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741829804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741829804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5721891806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5721891806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5741829804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5741829804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5741829804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5741829804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137704.365759 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137611.259533 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137611.259533 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked @@ -219,38 +221,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41512 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561041984 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571983982 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571983982 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85700.856373 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561041984 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3561041984 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3571983982 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3571983982 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3571983982 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3571983982 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -518,6 +514,7 @@ system.cpu.iew.wb_rate 0.487979 # in system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56280196 # The number of committed instructions system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted @@ -538,7 +535,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle -system.cpu.commit.count 56280196 # Number of instructions committed +system.cpu.commit.committedInsts 56280196 # Number of instructions committed +system.cpu.commit.committedOps 56280196 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 15504446 # Number of memory references committed system.cpu.commit.loads 9112319 # Number of loads committed @@ -555,6 +553,7 @@ system.cpu.timesIdled 1255783 # Nu system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 53085804 # Number of Instructions Simulated +system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads @@ -603,51 +602,39 @@ system.cpu.icache.total_refs 7985769 # To system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.963959 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.996023 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 7985770 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 509.963959 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996023 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996023 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7985770 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits -system.cpu.icache.demand_hits::0 7985770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 7985770 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 7985770 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 7985770 # number of overall hits system.cpu.icache.overall_hits::total 7985770 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1065446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 1065446 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1065446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 1065446 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1065446 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 1065446 # number of overall misses system.cpu.icache.overall_misses::total 1065446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15927822494 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15927822494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15927822494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9051216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15927822494 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15927822494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15927822494 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15927822494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15927822494 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15927822494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9051216 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9051216 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 9051216 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9051216 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9051216 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.117713 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.117713 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.117713 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14949.441355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14949.441355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14949.441355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117713 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.117713 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.117713 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked @@ -656,33 +643,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 234 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 60134 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 60134 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 60134 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12047333996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12047333996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12047333996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111069 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.111069 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.111069 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 234 # number of writebacks +system.cpu.icache.writebacks::total 234 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60134 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60134 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60134 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60134 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60134 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60134 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1005312 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1005312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1005312 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1005312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1005312 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1005312 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12047333996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12047333996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12047333996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12047333996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12047333996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12047333996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1403406 # number of replacements system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use @@ -690,84 +676,69 @@ system.cpu.dcache.total_refs 12086534 # To system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.996008 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7453772 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.996008 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7453772 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4220462 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4220462 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192050 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 192050 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220033 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 220033 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11674234 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 11674234 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11674234 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 11674234 # number of overall hits system.cpu.dcache.overall_hits::total 11674234 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1809182 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1809182 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1936475 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1936475 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 22599 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22599 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3745657 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 3745657 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3745657 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 3745657 # number of overall misses system.cpu.dcache.overall_misses::total 3745657 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38930236000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57815325976 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 338636000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 96745561976 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 96745561976 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9262954 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38930236000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38930236000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57815325976 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57815325976 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 338636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 28500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 28500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 96745561976 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 96745561976 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 96745561976 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 96745561976 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9262954 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6156937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156937 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 214649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214649 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220035 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 220035 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15419891 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 15419891 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15419891 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15419891 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.195314 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105284 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.242911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.242911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25828.729640 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25828.729640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195314 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314519 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.105284 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.242911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.242911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14250 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked @@ -776,57 +747,63 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 721461 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1637588 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5103 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2359049 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2359049 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298887 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17496 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386608 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386608 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24804888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8509686826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206420500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33314575326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33314575326 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904009500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234178998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2138188498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117427 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048545 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081510 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089923 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089923 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks +system.cpu.dcache.writebacks::total 834955 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed |