diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3 | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1682 |
1 files changed, 926 insertions, 756 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 76f868d7e..135d2aacf 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.855236 # Number of seconds simulated -sim_ticks 1855236450500 # Number of ticks simulated -final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854370 # Number of seconds simulated +sim_ticks 1854370484500 # Number of ticks simulated +final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182093 # Simulator instruction rate (inst/s) -host_op_rate 182093 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6374280472 # Simulator tick rate (ticks/s) -host_mem_usage 298212 # Number of bytes of host memory used -host_seconds 291.05 # Real time elapsed on the host -sim_insts 52998368 # Number of instructions simulated -sim_ops 52998368 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory -system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 94446 # Simulator instruction rate (inst/s) +host_op_rate 94446 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3304859837 # Simulator tick rate (ticks/s) +host_mem_usage 326668 # Number of bytes of host memory used +host_seconds 561.10 # Real time elapsed on the host +sim_insts 52993965 # Number of instructions simulated +sim_ops 52993965 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7507712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7507712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388692 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445277 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117308 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117308 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 522597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13414950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15367872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 522597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 522597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 522597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13414950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19416530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445277 # Total number of read requests seen +system.physmem.writeReqs 117308 # Total number of write requests seen +system.physmem.cpureqs 564090 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28497728 # Total number of bytes read from memory +system.physmem.bytesWritten 7507712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28497728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7507712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27911 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28123 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27918 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27747 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27734 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7583 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7380 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7215 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6854 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7671 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7427 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7174 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854365055000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 445277 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 118080 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 175 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 331917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 3912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 6175508423 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13385774423 # Sum of mem lat for all requests +system.physmem.totBusLat 1780884000 # Total cycles spent in databus access +system.physmem.totBankLat 5429382000 # Total cycles spent in bank access +system.physmem.avgQLat 13870.66 # Average queueing delay per request +system.physmem.avgBankLat 12194.80 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30065.46 # Average memory access latency +system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgWrQLen 10.01 # Average write queue length over time +system.physmem.readRowHits 425232 # Number of row buffer hits during reads +system.physmem.writeRowHits 76485 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.20 # Row buffer hit rate for writes +system.physmem.avgGap 3296150.90 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255779 # Cycle average of tags in use +system.iocache.tagsinuse 1.265505 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704471567000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265505 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079094 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079094 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -55,14 +213,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20930998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20930998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9501230806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9501230806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9522161804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9522161804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9522161804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9522161804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -79,19 +237,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120988.427746 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120988.427746 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228658.808385 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228658.808385 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228212.385956 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228212.385956 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 190847 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22837 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.356921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11934000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11934000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338470481 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7338470481 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7350404481 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7350404481 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7350404481 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7350404481 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68982.658960 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68982.658960 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176609.320394 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176609.320394 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -146,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9942716 # DTB read hits -system.cpu.dtb.read_misses 44791 # DTB read misses -system.cpu.dtb.read_acv 565 # DTB read access violations -system.cpu.dtb.read_accesses 947396 # DTB read accesses -system.cpu.dtb.write_hits 6623666 # DTB write hits -system.cpu.dtb.write_misses 10259 # DTB write misses -system.cpu.dtb.write_acv 393 # DTB write access violations -system.cpu.dtb.write_accesses 338396 # DTB write accesses -system.cpu.dtb.data_hits 16566382 # DTB hits -system.cpu.dtb.data_misses 55050 # DTB misses -system.cpu.dtb.data_acv 958 # DTB access violations -system.cpu.dtb.data_accesses 1285792 # DTB accesses -system.cpu.itb.fetch_hits 1328947 # ITB hits -system.cpu.itb.fetch_misses 38142 # ITB misses -system.cpu.itb.fetch_acv 1080 # ITB acv -system.cpu.itb.fetch_accesses 1367089 # ITB accesses +system.cpu.dtb.read_hits 10013236 # DTB read hits +system.cpu.dtb.read_misses 44959 # DTB read misses +system.cpu.dtb.read_acv 558 # DTB read access violations +system.cpu.dtb.read_accesses 947796 # DTB read accesses +system.cpu.dtb.write_hits 6616814 # DTB write hits +system.cpu.dtb.write_misses 10390 # DTB write misses +system.cpu.dtb.write_acv 394 # DTB write access violations +system.cpu.dtb.write_accesses 338465 # DTB write accesses +system.cpu.dtb.data_hits 16630050 # DTB hits +system.cpu.dtb.data_misses 55349 # DTB misses +system.cpu.dtb.data_acv 952 # DTB access violations +system.cpu.dtb.data_accesses 1286261 # DTB accesses +system.cpu.itb.fetch_hits 1329992 # ITB hits +system.cpu.itb.fetch_misses 37108 # ITB misses +system.cpu.itb.fetch_acv 1110 # ITB acv +system.cpu.itb.fetch_accesses 1367100 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -174,277 +332,277 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 112948398 # number of cpu cycles simulated +system.cpu.numCycles 109331520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits +system.cpu.BPredUnit.lookups 14034298 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11727409 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 442398 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10070774 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5936443 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37395096 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81356871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67855364 83.40% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81356871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37116939 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19830183 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80190207 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479545 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38187514 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6228893 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1695379 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 248206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12171415 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10595299 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6961029 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1313529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81356871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56509821 69.46% 69.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81356871 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 375615 47.50% 58.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326165 41.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38947584 68.15% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61688 0.11% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued -system.cpu.iq.rate 0.505315 # Inst issue rate -system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued +system.cpu.iq.rate 0.522738 # Inst issue rate +system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195876832 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1500833 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3663 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13623 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 580148 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17973 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 208284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1354175 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9957840 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684465 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64406962 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 718774 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10595299 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6961029 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1833098 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512595 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19043 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13623 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 239398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 420347 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 659745 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56634449 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10087078 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 517300 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3555305 # number of nop insts executed -system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed -system.cpu.iew.exec_branches 8969939 # Number of branches executed -system.cpu.iew.exec_stores 6649129 # Number of stores executed -system.cpu.iew.exec_rate 0.500679 # Inst execution rate -system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27804186 # num instructions producing a value -system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value +system.cpu.iew.exec_nop 3558099 # number of nop insts executed +system.cpu.iew.exec_refs 16729501 # number of memory reference insts executed +system.cpu.iew.exec_branches 8966109 # Number of branches executed +system.cpu.iew.exec_stores 6642423 # Number of stores executed +system.cpu.iew.exec_rate 0.518007 # Inst execution rate +system.cpu.iew.wb_sent 56249945 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56126682 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27860065 # num instructions producing a value +system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back +system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80002696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59120918 73.90% 73.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56188905 # Number of instructions committed -system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80002696 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56184240 # Number of instructions committed +system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15476867 # Number of memory references committed -system.cpu.commit.loads 9095415 # Number of loads committed -system.cpu.commit.membars 226300 # Number of memory barriers committed -system.cpu.commit.branches 8447820 # Number of branches committed +system.cpu.commit.refs 15475347 # Number of memory references committed +system.cpu.commit.loads 9094466 # Number of loads committed +system.cpu.commit.membars 226347 # Number of memory barriers committed +system.cpu.commit.branches 8447798 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52034961 # Number of committed integer instructions. -system.cpu.commit.function_calls 740468 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. +system.cpu.commit.function_calls 740415 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141682968 # The number of ROB reads -system.cpu.rob.rob_writes 129465441 # The number of ROB writes -system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52998368 # Number of Instructions Simulated -system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated -system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads -system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74144483 # number of integer regfile reads -system.cpu.int_regfile_writes 40484328 # number of integer regfile writes -system.cpu.fp_regfile_reads 165992 # number of floating regfile reads -system.cpu.fp_regfile_writes 167427 # number of floating regfile writes -system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads -system.cpu.misc_regfile_writes 946826 # number of misc regfile writes +system.cpu.rob.rob_reads 142220967 # The number of ROB reads +system.cpu.rob.rob_writes 129940455 # The number of ROB writes +system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27974649 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52993965 # Number of Instructions Simulated +system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated +system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads +system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74218754 # number of integer regfile reads +system.cpu.int_regfile_writes 40498790 # number of integer regfile writes +system.cpu.fp_regfile_reads 166070 # number of floating regfile reads +system.cpu.fp_regfile_writes 167447 # number of floating regfile writes +system.cpu.misc_regfile_reads 1994018 # number of misc regfile reads +system.cpu.misc_regfile_writes 947042 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -476,245 +634,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1020348 # number of replacements -system.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use -system.cpu.icache.total_refs 7661720 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits -system.cpu.icache.overall_hits::total 7661721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses -system.cpu.icache.overall_misses::total 1079749 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.replacements 1020188 # number of replacements +system.cpu.icache.tagsinuse 510.304097 # Cycle average of tags in use +system.cpu.icache.total_refs 7717774 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1020696 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.561286 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20124452000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.304097 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996688 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7717775 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7717775 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7717775 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7717775 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7717775 # number of overall hits +system.cpu.icache.overall_hits::total 7717775 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1079494 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079494 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1079494 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1079494 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1079494 # number of overall misses +system.cpu.icache.overall_misses::total 1079494 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14680685994 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14680685994 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14680685994 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14680685994 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14680685994 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14680685994 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8797269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8797269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8797269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8797269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8797269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8797269 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122708 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122708 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122708 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122708 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122708 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122708 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13599.599436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13599.599436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13599.599436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13599.599436 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3410 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 686 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.890511 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 686 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 58677 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 58677 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021072 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1021072 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58579 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 58579 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 58579 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 58579 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 58579 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 58579 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1020915 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1020915 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1020915 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1020915 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1020915 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1020915 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12036646497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12036646497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12036646497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12036646497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12036646497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12036646497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.057446 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.057446 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.057446 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11790.057446 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.057446 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11790.057446 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1402622 # number of replacements -system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use -system.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7274743 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7274743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204816 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204816 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 190397 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 190397 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 219522 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219522 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11479559 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11479559 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11479559 # number of overall hits -system.cpu.dcache.overall_hits::total 11479559 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1797475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1797475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1942414 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1942414 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23040 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23040 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3739889 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses -system.cpu.dcache.overall_misses::total 3739889 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147230 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213437 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 213437 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 219523 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219523 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15219448 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15219448 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15219448 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15219448 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198130 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198130 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315982 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315982 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107948 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107948 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.254608 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.254608 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24545.090425 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24545.090425 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1615102 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 442 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.681144 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49.111111 # average number of cycles each access was blocked +system.cpu.dcache.replacements 1402245 # number of replacements +system.cpu.dcache.tagsinuse 511.995160 # Cycle average of tags in use +system.cpu.dcache.total_refs 11879672 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1402757 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.468803 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21544000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995160 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7264730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7264730 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4204895 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4204895 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190246 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190246 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 219552 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219552 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11469625 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11469625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11469625 # number of overall hits +system.cpu.dcache.overall_hits::total 11469625 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801434 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801434 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1941730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1941730 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22995 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22995 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3743164 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3743164 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3743164 # number of overall misses +system.cpu.dcache.overall_misses::total 3743164 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445086639 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 70445086639 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104297759139 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104297759139 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104297759139 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104297759139 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146625 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213241 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 213241 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 219554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15212789 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15212789 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15212789 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15212789 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198699 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198699 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315902 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.315902 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107836 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107836 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.547949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.547949 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27863.529126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27863.529126 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2571682 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946948 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks -system.cpu.dcache.writebacks::total 841878 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5152 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5152 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2354499 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2354499 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2354499 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2354499 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085162 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1085162 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300228 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300228 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17888 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17888 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1385390 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1385390 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402034783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402034783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065701283 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32065701283 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065701283 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997524498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048840 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048840 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083809 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083809 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 841139 # number of writebacks +system.cpu.dcache.writebacks::total 841139 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716695 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 716695 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1641513 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1641513 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5045 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5045 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2358208 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2358208 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2358208 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2358208 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084739 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084739 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300217 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300217 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17950 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17950 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384956 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384956 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384956 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712390769 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712390769 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907863269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31907863269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907863269 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31907863269 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997718998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997718998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421626998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421626998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048843 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084177 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084177 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091039 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.159135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.159135 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -722,105 +880,109 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 338417 # number of replacements -system.cpu.l2cache.tagsinuse 65352.111585 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2559541 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403585 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.342012 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4707423000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 53923.419199 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5354.651362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6074.041024 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.822806 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.081705 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092683 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997194 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 1005811 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 828504 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1834315 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 841878 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 841878 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.replacements 338360 # number of replacements +system.cpu.l2cache.tagsinuse 65364.997376 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2558215 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 53963.120653 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.081638 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.092341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997391 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1005648 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 828171 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1833819 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 841139 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 841139 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185452 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185452 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1005811 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1013956 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2019767 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1005811 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1013956 # number of overall hits -system.cpu.l2cache.overall_hits::total 2019767 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15151 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273885 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 289036 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115380 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115380 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15151 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389265 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404416 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses -system.cpu.l2cache.overall_misses::total 404416 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808283500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15073472500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187369500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6187369500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 808283500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20452558500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21260842000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 808283500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20452558500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21260842000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 841878 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 841878 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 59 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 59 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300832 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300832 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1020962 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1403221 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2424183 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1020962 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1403221 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2424183 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014840 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248447 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136123 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.559322 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.559322 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383536 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383536 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014840 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277408 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166826 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.524850 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.847991 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.014041 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.014041 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52571.713285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52571.713285 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 185483 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185483 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1005648 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1013654 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2019302 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1005648 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1013654 # number of overall hits +system.cpu.l2cache.overall_hits::total 2019302 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273859 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 289003 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 36 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 36 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115327 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115327 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389186 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404330 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15144 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389186 # number of overall misses +system.cpu.l2cache.overall_misses::total 404330 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 916217000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11804091500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496192000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8496192000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20300283500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21216500500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20300283500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21216500500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 841139 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 841139 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 67 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 67 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 300810 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 300810 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1020792 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1402840 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2423632 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1020792 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1402840 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2423632 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014836 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248504 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136141 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.537313 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.537313 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383388 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014836 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277427 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.166828 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014836 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277427 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.166828 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60500.330164 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.450111 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.450111 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52473.228551 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52473.228551 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -829,72 +991,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76030 # number of writebacks -system.cpu.l2cache.writebacks::total 76030 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75796 # number of writebacks +system.cpu.l2cache.writebacks::total 75796 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15150 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273885 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289035 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986768000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609687500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791050000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791050000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777818000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16400737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777818000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16400737500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.798680 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.529821 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40167.064542 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.094297 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.094297 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 289002 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115327 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115327 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389186 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404329 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389186 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067951103 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067951103 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327873464 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16052895904 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327873464 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16052895904 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331389500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331389500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1881061000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1881061000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212450500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212450500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383388 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.166828 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.178458 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.178458 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -903,28 +1073,28 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211013 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105569 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818451122500 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64044500 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561305000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35293166500 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854369638500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694295 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -963,29 +1133,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175126 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191902 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.callpal::total 191972 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu.kern.mode_good::kernel 1909 system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29748704000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2690261500 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1821930665000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |