regressions: update stats due to branch predictor changes

The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

3 files changed, 47 insertions, 39 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index ebcbd1b8c..8b454d95b 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -12,15 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 clock=1000
-console=/gem5/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 init_param=0
-kernel=/gem5/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/gem5/dist/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -46,22 +46,18 @@ slave=system.membus.master[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
 LSQDepCheckShift=4
-RASSize=16
 SQEntries=32
 SSITSize=1024
 activity=0
 backComSize=5
+branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
 clock=500
 commitToDecodeDelay=1
 commitToFetchDelay=1
@@ -84,23 +80,15 @@ forwardComSize=5
 fuPool=system.cpu.fuPool
 function_trace=false
 function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
 iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-instShiftAmt=2
 interrupts=system.cpu.interrupts
 isa=system.cpu.isa
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
@@ -112,7 +100,6 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
-predType=tournament
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -141,6 +128,24 @@ workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
 [system.cpu.dcache]
 type=BaseCache
 addr_ranges=0:18446744073709551615
@@ -514,7 +519,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -534,7 +539,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/gem5/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -637,7 +642,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 5e5126f62..4fc9bce9f 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  4 2013 21:09:21
-gem5 started Jan  4 2013 21:39:46
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:39:31
+gem5 executing on ribera.cs.wisc.edu
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1854349611000 because m5_exit instruction encountered
+Exiting @ tick 1854344296500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 7d46ecd48..2f976aa78 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.854344                       # Nu
 sim_ticks                                1854344296500                       # Number of ticks simulated
 final_tick                               1854344296500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131278                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131278                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4595190559                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 336376                       # Number of bytes of host memory used
-host_seconds                                   403.54                       # Real time elapsed on the host
+host_inst_rate                                  90928                       # Simulator instruction rate (inst/s)
+host_op_rate                                    90928                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3182808238                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 379332                       # Number of bytes of host memory used
+host_seconds                                   582.61                       # Real time elapsed on the host
 sim_insts                                    52976017                       # Number of instructions simulated
 sim_ops                                      52976017                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            964864                       # Number of bytes read from this memory
@@ -300,6 +300,15 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu.branchPred.lookups                13851594                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11614390                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            401305                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9533712                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5819078                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             61.036855                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  909714                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              39020                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -335,14 +344,6 @@ system.cpu.itb.data_accesses                        0                       # DT
 system.cpu.numCycles                        108725026                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 13851594                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11614390                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             401305                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups               9533712                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  5819078                       # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                   909714                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               39020                       # Number of incorrect RAS predictions.
 system.cpu.fetch.icacheStallCycles           28116472                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                       70876145                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                    13851594                       # Number of branches that fetch encountered