diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full | |
parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt | 2297 |
1 files changed, 1151 insertions, 1146 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 014619ced..1f0f241e7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,154 +1,141 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.841686 # Number of seconds simulated -sim_ticks 1841685645500 # Number of ticks simulated -final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1841685557500 # Number of ticks simulated +final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 300759 # Simulator instruction rate (inst/s) -host_op_rate 300759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7981184825 # Simulator tick rate (ticks/s) -host_mem_usage 313952 # Number of bytes of host memory used -host_seconds 230.75 # Real time elapsed on the host -sim_insts 69401254 # Number of instructions simulated -sim_ops 69401254 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19389440 # Number of bytes read from this memory +host_inst_rate 244491 # Simulator instruction rate (inst/s) +host_op_rate 244491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6478446279 # Simulator tick rate (ticks/s) +host_mem_usage 315916 # Number of bytes of host memory used +host_seconds 284.28 # Real time elapsed on the host +sim_insts 69503534 # Number of instructions simulated +sim_ops 69503534 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19348096 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2812736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 293952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2665600 # Number of bytes read from this memory -system.physmem.bytes_read::total 28438656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 293952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7476160 # Number of bytes written to this memory -system.physmem.bytes_written::total 7476160 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302960 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 150080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2814720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2705088 # Number of bytes read from this memory +system.physmem.bytes_read::total 28439424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 474240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7476992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7476992 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302314 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4593 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41650 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444354 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116815 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116815 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10528094 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 2345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 43980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444366 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116828 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116828 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 257503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10505646 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1527262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1447370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15441645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81595 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4059412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4059412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4059412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10528094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1528339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 160132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1468811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15442063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 257503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 160132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4059864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4059864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4059864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 257503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10505646 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1527262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1447370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19501057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109303 # Total number of read requests seen -system.physmem.writeReqs 45531 # Total number of write requests seen -system.physmem.cpureqs 156037 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6995392 # Total number of bytes read from memory -system.physmem.bytesWritten 2913984 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6995392 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2913984 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 81491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1528339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 160132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1468811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109963 # Total number of read requests seen +system.physmem.writeReqs 45515 # Total number of write requests seen +system.physmem.cpureqs 155620 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7037632 # Total number of bytes read from memory +system.physmem.bytesWritten 2912960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2912960 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6492 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6828 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6781 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2987 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2793 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2608 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2755 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2826 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2868 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2766 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 40 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6897 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6833 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7049 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6845 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2979 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2595 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2752 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3044 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2867 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2811 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1002 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840673558000 # Total gap between requests +system.physmem.numWrRetry 102 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840673470000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109303 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 46533 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 41 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 80133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.readPktSize::6 109963 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 45515 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 80954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 319 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,240 +148,242 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1965 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2420387927 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4417690427 # Sum of mem lat for all requests -system.physmem.totBusLat 546485000 # Total cycles spent in databus access -system.physmem.totBankLat 1450817500 # Total cycles spent in bank access -system.physmem.avgQLat 22145.05 # Average queueing delay per request -system.physmem.avgBankLat 13274.08 # Average bank access latency per request +system.physmem.wrQLenPdf::18 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.totQLat 2376401250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4386835000 # Sum of mem lat for all requests +system.physmem.totBusLat 549785000 # Total cycles spent in databus access +system.physmem.totBankLat 1460648750 # Total cycles spent in bank access +system.physmem.avgQLat 21612.10 # Average queueing delay per request +system.physmem.avgBankLat 13283.82 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40419.14 # Average memory access latency -system.physmem.avgRdBW 3.80 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 39895.91 # Average memory access latency +system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.16 # Average write queue length over time -system.physmem.readRowHits 99113 # Number of row buffer hits during reads -system.physmem.writeRowHits 34331 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.40 # Row buffer hit rate for writes -system.physmem.avgGap 11888044.99 # Average gap between requests -system.l2c.replacements 337419 # number of replacements -system.l2c.tagsinuse 65421.239766 # Cycle average of tags in use -system.l2c.total_refs 2475144 # Total number of references to valid blocks. -system.l2c.sampled_refs 402581 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.148189 # Average number of references to valid blocks. +system.physmem.readRowHits 99744 # Number of row buffer hits during reads +system.physmem.writeRowHits 34338 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.44 # Row buffer hit rate for writes +system.physmem.avgGap 11838803.37 # Average gap between requests +system.l2c.replacements 337431 # number of replacements +system.l2c.tagsinuse 65421.769821 # Cycle average of tags in use +system.l2c.total_refs 2476371 # Total number of references to valid blocks. +system.l2c.sampled_refs 402593 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.151053 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54789.025804 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2312.416873 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2671.189079 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 589.820867 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 668.130775 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2247.184130 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2143.472240 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.836014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.035285 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040759 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.009000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.010195 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.034289 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032707 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 513915 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491176 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 82893 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 298492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 243008 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1756065 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836144 # number of Writeback hits -system.l2c.Writeback_hits::total 836144 # number of Writeback hits +system.l2c.occ_blocks::writebacks 54783.846469 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2311.752265 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2671.563738 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 585.881665 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 667.174389 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2255.430098 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 2146.121197 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.835935 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.035275 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.040765 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.008940 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.010180 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.034415 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.032747 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998257 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 514621 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 491109 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 126725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83687 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 298608 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 242406 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1757156 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 836280 # number of Writeback hits +system.l2c.Writeback_hits::total 836280 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92052 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27044 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67842 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186938 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 513915 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 583228 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 126581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 109937 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 298492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 310850 # number of demand (read+write) hits -system.l2c.demand_hits::total 1943003 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 513915 # number of overall hits -system.l2c.overall_hits::cpu0.data 583228 # number of overall hits -system.l2c.overall_hits::cpu1.inst 126581 # number of overall hits -system.l2c.overall_hits::cpu1.data 109937 # number of overall hits -system.l2c.overall_hits::cpu2.inst 298492 # number of overall hits -system.l2c.overall_hits::cpu2.data 310850 # number of overall hits -system.l2c.overall_hits::total 1943003 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7412 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 226081 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2348 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 22980 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4593 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 24148 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287562 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 92033 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 27042 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67840 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186915 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 514621 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 583142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 126725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 110729 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 298608 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 310246 # number of demand (read+write) hits +system.l2c.demand_hits::total 1944071 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 514621 # number of overall hits +system.l2c.overall_hits::cpu0.data 583142 # number of overall hits +system.l2c.overall_hits::cpu1.inst 126725 # number of overall hits +system.l2c.overall_hits::cpu1.data 110729 # number of overall hits +system.l2c.overall_hits::cpu2.inst 298608 # number of overall hits +system.l2c.overall_hits::cpu2.data 310246 # number of overall hits +system.l2c.overall_hits::total 1944071 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7410 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 225248 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2345 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 23010 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4608 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 24959 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287580 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77155 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21018 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 17603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115776 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7412 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 303236 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2348 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 43998 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4593 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 41751 # number of demand (read+write) misses -system.l2c.demand_misses::total 403338 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7412 # number of overall misses -system.l2c.overall_misses::cpu0.data 303236 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2348 # number of overall misses -system.l2c.overall_misses::cpu1.data 43998 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4593 # number of overall misses -system.l2c.overall_misses::cpu2.data 41751 # number of overall misses -system.l2c.overall_misses::total 403338 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 154067000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1052058500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 311896500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1117922000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2635944000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_misses::cpu2.data 10 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 77341 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 21020 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 17409 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115770 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7410 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 302589 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2345 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 44030 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4608 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 42368 # number of demand (read+write) misses +system.l2c.demand_misses::total 403350 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7410 # number of overall misses +system.l2c.overall_misses::cpu0.data 302589 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2345 # number of overall misses +system.l2c.overall_misses::cpu1.data 44030 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4608 # number of overall misses +system.l2c.overall_misses::cpu2.data 42368 # number of overall misses +system.l2c.overall_misses::total 403350 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 151883500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1053888000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 310106500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1117642500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2633520500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 295000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 295000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 978614500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1291616000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2270230500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 154067000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2030673000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 311896500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2409538000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 4906174500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 154067000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2030673000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 311896500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2409538000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 4906174500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 521327 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 717257 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 128929 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 105873 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 303085 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 267156 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2043627 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 836144 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 836144 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::cpu1.data 979969000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1286505500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2266474500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 151883500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2033857000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 310106500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2404148000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 4899995000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 151883500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2033857000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 310106500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2404148000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 4899995000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 522031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 716357 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 129070 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 106697 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 303216 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 267365 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2044736 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 836280 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 836280 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 169207 # number of ReadExReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 169374 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 48062 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 85445 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302714 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 521327 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 886464 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 128929 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 153935 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 303085 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 352601 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2346341 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 521327 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 886464 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 128929 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 153935 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 303085 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 352601 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2346341 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.315202 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018212 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.217053 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.015154 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.090389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.140712 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu2.data 85249 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302685 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 522031 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 885731 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 129070 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 154759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 303216 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 352614 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2347421 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 522031 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 885731 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 129070 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 154759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 303216 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 352614 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2347421 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014195 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.314435 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.018168 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.215657 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.015197 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.093352 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.140644 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.733333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.703704 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.455980 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.437310 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.206016 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382460 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014218 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.342074 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018212 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.285822 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.015154 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.118409 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171901 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014218 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.342074 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018212 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.285822 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.015154 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.118409 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171901 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65616.269165 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 45781.483899 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67906.923579 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 46294.599967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9166.524089 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26818.181818 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 15526.315789 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46560.781235 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73374.765665 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 19608.817890 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46153.756989 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 67906.923579 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12163.928269 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46153.756989 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 67906.923579 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12163.928269 # average overall miss latency +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.714286 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.692308 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.456629 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.437352 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.204214 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382477 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014195 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.341626 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.018168 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.284507 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.015197 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.120154 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171827 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014195 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.341626 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.018168 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.284507 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.015197 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.120154 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171827 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64769.083156 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 45801.303781 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67297.417535 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 44779.137786 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9157.523124 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16388.888889 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46620.789724 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73898.874146 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 19577.390516 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 64769.083156 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46192.527822 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 67297.417535 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 56744.429758 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12148.245940 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 64769.083156 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46192.527822 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 67297.417535 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 56744.429758 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12148.245940 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,97 +392,97 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75303 # number of writebacks -system.l2c.writebacks::total 75303 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2348 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 22980 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4593 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 24148 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 54069 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 21018 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 17603 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 38621 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2348 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 43998 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4593 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 41751 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 92690 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2348 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 43998 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4593 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 41751 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 92690 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124527350 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 769462495 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 254598394 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 825079853 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1973668092 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 271507 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 271507 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 718879972 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1076725373 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1795605345 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 124527350 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1488342467 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 254598394 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1901805226 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 3769273437 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 124527350 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1488342467 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 254598394 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1901805226 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 3769273437 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269404000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320097000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 589501000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337106000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 394521000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 731627000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606510000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 714618000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1321128000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217053 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090389 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.026457 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.733333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.407407 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.437310 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.206016 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.127582 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.285822 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.118409 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.039504 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.285822 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.118409 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.039504 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33484.007615 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 34167.626843 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 36502.766687 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 24682.454545 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 24682.454545 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34203.062708 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61167.151792 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 46492.979079 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40665.373147 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40665.373147 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75316 # number of writebacks +system.l2c.writebacks::total 75316 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2345 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 23010 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4608 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 24959 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 54922 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 10 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 21020 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 17409 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 38429 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2345 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 44030 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4608 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 42368 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 93351 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2345 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 44030 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4608 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 42368 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 93351 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122370842 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 770894982 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 252658268 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 814852254 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1960776346 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 261506 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 261506 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 720185758 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1074026983 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1794212741 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 122370842 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1491080740 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 252658268 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1888879237 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 3754989087 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 122370842 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1491080740 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 252658268 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1888879237 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 3754989087 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269544000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 323045500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 592589500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337247500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 397454500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 734702000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606791500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 720500000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1327291500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.215657 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.093352 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.026860 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.714286 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.437352 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.204214 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.126960 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.284507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.120154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.039767 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.284507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.120154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.039767 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33502.606780 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 32647.632277 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 35701.109683 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26150.600000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26150.600000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34261.929496 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61693.778103 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 46689.030186 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33865.108789 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 44582.685919 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33865.108789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44582.685919 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -505,12 +494,12 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255467 # Cycle average of tags in use +system.iocache.tagsinuse 1.255479 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693876367000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255467 # Average occupied blocks per requestor +system.iocache.warmup_cycle 1693875860000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255479 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.078467 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.078467 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses @@ -521,14 +510,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 10497998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 10497998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4320435904 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4320435904 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4330933902 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4330933902 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4330933902 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4330933902 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4305588904 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4305588904 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4314766902 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4314766902 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4314766902 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4314766902 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -545,19 +534,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 60682.069364 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 60682.069364 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103976.605314 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 103976.605314 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 103797.097711 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 103797.097711 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 116360 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103619.293993 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 103619.293993 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 116041 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11123 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11151 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.461207 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.406331 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -571,14 +560,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 16837 system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6909249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6909249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3447972406 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3447972406 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3454881655 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3454881655 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3454881655 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3454881655 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433126461 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3433126461 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3438715710 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3438715710 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3438715710 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3438715710 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses @@ -587,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 100134.043478 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 100134.043478 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205628.125358 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 205628.125358 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204742.751729 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204742.751729 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,22 +601,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4870222 # DTB read hits -system.cpu0.dtb.read_misses 6004 # DTB read misses -system.cpu0.dtb.read_acv 119 # DTB read access violations -system.cpu0.dtb.read_accesses 427226 # DTB read accesses -system.cpu0.dtb.write_hits 3495920 # DTB write hits -system.cpu0.dtb.write_misses 662 # DTB write misses +system.cpu0.dtb.read_hits 4874109 # DTB read hits +system.cpu0.dtb.read_misses 5989 # DTB read misses +system.cpu0.dtb.read_acv 118 # DTB read access violations +system.cpu0.dtb.read_accesses 427176 # DTB read accesses +system.cpu0.dtb.write_hits 3500725 # DTB write hits +system.cpu0.dtb.write_misses 661 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162893 # DTB write accesses -system.cpu0.dtb.data_hits 8366142 # DTB hits -system.cpu0.dtb.data_misses 6666 # DTB misses -system.cpu0.dtb.data_acv 201 # DTB access violations -system.cpu0.dtb.data_accesses 590119 # DTB accesses -system.cpu0.itb.fetch_hits 2742252 # ITB hits -system.cpu0.itb.fetch_misses 2999 # ITB misses -system.cpu0.itb.fetch_acv 100 # ITB acv -system.cpu0.itb.fetch_accesses 2745251 # ITB accesses +system.cpu0.dtb.write_accesses 162885 # DTB write accesses +system.cpu0.dtb.data_hits 8374834 # DTB hits +system.cpu0.dtb.data_misses 6650 # DTB misses +system.cpu0.dtb.data_acv 200 # DTB access violations +system.cpu0.dtb.data_accesses 590061 # DTB accesses +system.cpu0.itb.fetch_hits 2743092 # ITB hits +system.cpu0.itb.fetch_misses 2995 # ITB misses +system.cpu0.itb.fetch_acv 98 # ITB acv +system.cpu0.itb.fetch_accesses 2746087 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -640,51 +629,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928524557 # number of cpu cycles simulated +system.cpu0.numCycles 928539725 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32346409 # Number of instructions committed -system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30227600 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses -system.cpu0.num_func_calls 807221 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30227600 # number of integer instructions -system.cpu0.num_fp_insts 167714 # number of float instructions -system.cpu0.num_int_register_reads 42120330 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22107857 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written -system.cpu0.num_mem_refs 8395829 # number of memory refs -system.cpu0.num_load_insts 4891258 # Number of load instructions -system.cpu0.num_store_insts 3504571 # Number of store instructions -system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles -system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles -system.cpu0.not_idle_fraction -228.514484 # Percentage of non-idle cycles -system.cpu0.idle_fraction 229.514484 # Percentage of idle cycles +system.cpu0.committedInsts 32518253 # Number of instructions committed +system.cpu0.committedOps 32518253 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30397519 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 168035 # Number of float alu accesses +system.cpu0.num_func_calls 808172 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4307008 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30397519 # number of integer instructions +system.cpu0.num_fp_insts 168035 # number of float instructions +system.cpu0.num_int_register_reads 42396693 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22221610 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 86774 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88345 # number of times the floating registers were written +system.cpu0.num_mem_refs 8404498 # number of memory refs +system.cpu0.num_load_insts 4895120 # Number of load instructions +system.cpu0.num_store_insts 3509378 # Number of store instructions +system.cpu0.num_idle_cycles 214025441196.436279 # Number of idle cycles +system.cpu0.num_busy_cycles -213096901471.436279 # Number of busy cycles +system.cpu0.not_idle_fraction -229.496806 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.496806 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211363 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74796 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211357 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105684 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182561 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73429 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818585888500 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39023500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22696621500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818586321500 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38755000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 363405500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22696319000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841684801000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815831 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694792 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -720,10 +709,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175304 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -732,21 +721,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192218 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.callpal::total 192213 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29741940500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2557110500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4178 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::total 0.391349 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29734416500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2561211500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809389169500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -778,356 +767,372 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 952688 # number of replacements -system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use -system.cpu0.icache.total_refs 41854962 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953199 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 43.909994 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 175.771257 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.155505 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.343303 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7734855 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2288179 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41854962 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31831928 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7734855 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2288179 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41854962 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31831928 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7734855 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2288179 # number of overall hits -system.cpu0.icache.overall_hits::total 41854962 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 521348 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 128929 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 320072 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970349 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 521348 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 128929 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 320072 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970349 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 521348 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 128929 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 320072 # number of overall misses -system.cpu0.icache.overall_misses::total 970349 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813964500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4473861486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6287825986 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1813964500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4473861486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6287825986 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1813964500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4473861486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6287825986 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32353276 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863784 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608251 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42825311 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32353276 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7863784 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2608251 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42825311 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32353276 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7863784 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2608251 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42825311 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016114 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016395 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122715 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122715 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122715 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.672168 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.963380 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6479.963380 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6479.963380 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5140 # number of cycles access was blocked +system.cpu0.icache.replacements 953667 # number of replacements +system.cpu0.icache.tagsinuse 511.197543 # Cycle average of tags in use +system.cpu0.icache.total_refs 42031546 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 954178 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 44.050005 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10246755000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 255.638706 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 78.351576 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 177.207261 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.499294 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.153030 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.346108 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998433 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 32003051 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7743805 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2284690 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42031546 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32003051 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7743805 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2284690 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42031546 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32003051 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7743805 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2284690 # number of overall hits +system.cpu0.icache.overall_hits::total 42031546 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 522052 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 129070 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 320206 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 971328 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 522052 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 129070 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 320206 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 971328 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 522052 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 129070 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 320206 # number of overall misses +system.cpu0.icache.overall_misses::total 971328 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813664500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4475771482 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6289435982 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1813664500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4475771482 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6289435982 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1813664500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4475771482 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6289435982 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32525103 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7872875 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2604896 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43002874 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32525103 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7872875 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2604896 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43002874 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32525103 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7872875 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2604896 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43002874 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016051 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016394 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122925 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022588 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016051 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016394 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122925 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022588 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016051 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016394 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122925 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022588 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14051.789727 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.787680 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6475.089755 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6475.089755 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6475.089755 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4631 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 184 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.235294 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.168478 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16975 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16975 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16975 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16975 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16975 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16975 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128929 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303097 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 432026 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 128929 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 303097 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 432026 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 128929 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 303097 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 432026 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1556106500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3684207988 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5240314488 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1556106500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3684207988 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5240314488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1556106500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3684207988 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5240314488 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010088 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010088 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010088 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12129.627587 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12129.627587 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12129.627587 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16976 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16976 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16976 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16976 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16976 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16976 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129070 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303230 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 432300 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 129070 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 303230 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 432300 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 129070 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 303230 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 432300 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1555524500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3682492984 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5238017484 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1555524500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3682492984 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5238017484 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1555524500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3682492984 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5238017484 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010053 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010053 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010053 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12116.626149 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12116.626149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12116.626149 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1392453 # number of replacements +system.cpu0.dcache.replacements 1392556 # number of replacements system.cpu0.dcache.tagsinuse 511.997817 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13322507 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1392965 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.564136 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 13323345 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1393068 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.564031 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 248.356869 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 87.947367 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 175.693580 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.485072 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.171772 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.343152 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 246.086905 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 89.137504 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 176.773408 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.480638 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.174097 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.345261 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4047369 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1097591 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2422191 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7567151 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3200230 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 858461 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1312963 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5371654 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116449 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19275 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48623 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184347 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125392 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21336 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52561 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199289 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7247599 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1956052 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3735154 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12938805 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7247599 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1956052 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3735154 # number of overall hits -system.cpu0.dcache.overall_hits::total 12938805 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 707756 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 103680 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 547661 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1359097 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169218 # number of WriteReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4052041 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1098209 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2416271 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7566521 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3204724 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 859151 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1309317 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5373192 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116570 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19297 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48424 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184291 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125555 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21359 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52366 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199280 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7256765 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1957360 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3725588 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12939713 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7256765 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1957360 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3725588 # number of overall hits +system.cpu0.dcache.overall_hits::total 12939713 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 706812 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 104504 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 547702 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1359018 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 169385 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 48063 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 563002 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 780283 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9501 # number of LoadLockedReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 561193 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 778641 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9545 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2193 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7002 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18696 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 876974 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 151743 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1110663 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2139380 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 876974 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 151743 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1110663 # number of overall misses -system.cpu0.dcache.overall_misses::total 2139380 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2172880000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9444239000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11617119000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393921500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14767149219 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16161070719 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28928500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 105213000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 134141500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3566801500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 24211388219 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 27778189719 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3566801500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 24211388219 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 27778189719 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4755125 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1201271 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2969852 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8926248 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3369448 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 906524 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1875965 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6151937 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21468 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55625 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203043 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125392 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21336 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52561 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199289 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8124573 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2107795 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4845817 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15078185 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8124573 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2107795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4845817 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15078185 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148841 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086309 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184407 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152258 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050221 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053019 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.300113 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.126835 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075435 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102152 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.125879 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092079 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107941 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.071991 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229200 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.141886 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107941 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.071991 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229200 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.141886 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20957.561728 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17244.680560 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8547.674669 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29001.966169 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26229.301528 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20711.806766 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13191.290470 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15026.135390 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7174.876979 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23505.542266 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21799.040950 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12984.224270 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23505.542266 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21799.040950 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12984.224270 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 420237 # number of cycles access was blocked +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7060 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18798 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 876197 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 152567 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1108895 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2137659 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 876197 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 152567 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1108895 # number of overall misses +system.cpu0.dcache.overall_misses::total 2137659 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2184733000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9442098000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11626831000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1395266000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14749790240 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16145056240 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29363000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 105564500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 134927500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 3579999000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 24191888240 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 27771887240 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3579999000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 24191888240 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 27771887240 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4758853 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1202713 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 2963973 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8925539 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3374109 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 907214 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1870510 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6151833 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126115 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21490 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55484 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203089 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125555 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21359 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52367 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8132962 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2109927 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 4834483 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15077372 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8132962 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2109927 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 4834483 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15077372 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148526 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086890 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184786 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152262 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050201 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.052979 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.300021 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.126571 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075685 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102047 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.127244 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092560 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107734 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.072309 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229372 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.141779 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107734 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.072309 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229372 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.141779 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20905.735666 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17239.480593 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8555.317884 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29029.939871 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26282.919138 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20734.916656 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13389.420885 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14952.478754 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7177.758272 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23465.094024 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21816.211851 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12991.729382 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23465.094024 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21816.211851 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12991.729382 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 421766 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 580 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 16818 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 16882 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.987335 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.983177 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 82.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 836144 # number of writebacks -system.cpu0.dcache.writebacks::total 836144 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285747 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 285747 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 477794 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 477794 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1510 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1510 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 763541 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 763541 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 763541 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 763541 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 103680 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 261914 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 365594 # number of ReadReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 836280 # number of writebacks +system.cpu0.dcache.writebacks::total 836280 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285653 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 285653 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 476174 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 476174 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1502 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1502 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 761827 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 761827 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 761827 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 761827 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 104504 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 262049 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366553 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48063 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85208 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133271 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85019 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133082 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5492 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7685 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 151743 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 347122 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 498865 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 151743 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 347122 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 498865 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1965520000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314579500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280099500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297795500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2151055620 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851120 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24542500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263315500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465635120 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9728950620 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263315500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465635120 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9728950620 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342020000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760662000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053019 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045421 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021663 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102152 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037849 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033085 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.267943 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.796955 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.966169 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.481590 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5558 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7751 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 152567 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 347068 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 499635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 152567 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 347068 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 499635 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1975725000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4306208500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6281933500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1299140000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2144349624 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3443489624 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24977000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70824000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95801000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3274865000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6450558124 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9725423124 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3274865000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6450558124 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9725423124 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287731500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 345150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 632882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357324500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 421745500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 779070000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645056000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 766896000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411952000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086890 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088411 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041068 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.052979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045452 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021633 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102047 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.100173 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038166 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033138 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033138 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18905.735666 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.836989 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17137.858645 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27029.939871 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25222.004775 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25874.946454 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11389.420885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12742.713206 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12359.824539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1142,22 +1147,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1220324 # DTB read hits -system.cpu1.dtb.read_misses 1556 # DTB read misses -system.cpu1.dtb.read_acv 46 # DTB read access violations -system.cpu1.dtb.read_accesses 144016 # DTB read accesses -system.cpu1.dtb.write_hits 928239 # DTB write hits -system.cpu1.dtb.write_misses 207 # DTB write misses +system.cpu1.dtb.read_hits 1221793 # DTB read hits +system.cpu1.dtb.read_misses 1550 # DTB read misses +system.cpu1.dtb.read_acv 45 # DTB read access violations +system.cpu1.dtb.read_accesses 143987 # DTB read accesses +system.cpu1.dtb.write_hits 928954 # DTB write hits +system.cpu1.dtb.write_misses 206 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 60107 # DTB write accesses -system.cpu1.dtb.data_hits 2148563 # DTB hits -system.cpu1.dtb.data_misses 1763 # DTB misses -system.cpu1.dtb.data_acv 70 # DTB access violations -system.cpu1.dtb.data_accesses 204123 # DTB accesses -system.cpu1.itb.fetch_hits 875123 # ITB hits -system.cpu1.itb.fetch_misses 774 # ITB misses +system.cpu1.dtb.write_accesses 60098 # DTB write accesses +system.cpu1.dtb.data_hits 2150747 # DTB hits +system.cpu1.dtb.data_misses 1756 # DTB misses +system.cpu1.dtb.data_acv 69 # DTB access violations +system.cpu1.dtb.data_accesses 204085 # DTB accesses +system.cpu1.itb.fetch_hits 875028 # ITB hits +system.cpu1.itb.fetch_misses 772 # ITB misses system.cpu1.itb.fetch_acv 46 # ITB acv -system.cpu1.itb.fetch_accesses 875897 # ITB accesses +system.cpu1.itb.fetch_accesses 875800 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1170,28 +1175,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953544041 # number of cpu cycles simulated +system.cpu1.numCycles 953543873 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7861950 # Number of instructions committed -system.cpu1.committedOps 7861950 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7314131 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses -system.cpu1.num_func_calls 212083 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7314131 # number of integer instructions -system.cpu1.num_fp_insts 45433 # number of float instructions -system.cpu1.num_int_register_reads 10166174 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5323213 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written -system.cpu1.num_mem_refs 2156447 # number of memory refs -system.cpu1.num_load_insts 1225739 # Number of load instructions -system.cpu1.num_store_insts 930708 # Number of store instructions -system.cpu1.num_idle_cycles 195910527.476772 # Number of idle cycles -system.cpu1.num_busy_cycles 757633513.523228 # Number of busy cycles -system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles +system.cpu1.committedInsts 7871049 # Number of instructions committed +system.cpu1.committedOps 7871049 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7322486 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45486 # Number of float alu accesses +system.cpu1.num_func_calls 212361 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 961543 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7322486 # number of integer instructions +system.cpu1.num_fp_insts 45486 # number of float instructions +system.cpu1.num_int_register_reads 10177666 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5328829 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24537 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24857 # number of times the floating registers were written +system.cpu1.num_mem_refs 2158619 # number of memory refs +system.cpu1.num_load_insts 1227197 # Number of load instructions +system.cpu1.num_store_insts 931422 # Number of store instructions +system.cpu1.num_idle_cycles -1678612352.135852 # Number of idle cycles +system.cpu1.num_busy_cycles 2632156225.135852 # Number of busy cycles +system.cpu1.not_idle_fraction 2.760393 # Percentage of non-idle cycles +system.cpu1.idle_fraction -1.760393 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1209,35 +1214,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8412639 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129283 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5762097 # Number of BTB hits +system.cpu2.branchPred.lookups 8388883 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7698653 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 129790 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6809522 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5746337 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.529003 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 288281 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.386790 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 285994 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15305 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3230838 # DTB read hits -system.cpu2.dtb.read_misses 11458 # DTB read misses -system.cpu2.dtb.read_acv 112 # DTB read access violations -system.cpu2.dtb.read_accesses 217040 # DTB read accesses -system.cpu2.dtb.write_hits 2001661 # DTB write hits -system.cpu2.dtb.write_misses 2605 # DTB write misses -system.cpu2.dtb.write_acv 143 # DTB write access violations -system.cpu2.dtb.write_accesses 81606 # DTB write accesses -system.cpu2.dtb.data_hits 5232499 # DTB hits -system.cpu2.dtb.data_misses 14063 # DTB misses -system.cpu2.dtb.data_acv 255 # DTB access violations -system.cpu2.dtb.data_accesses 298646 # DTB accesses -system.cpu2.itb.fetch_hits 371716 # ITB hits -system.cpu2.itb.fetch_misses 5691 # ITB misses -system.cpu2.itb.fetch_acv 245 # ITB acv -system.cpu2.itb.fetch_accesses 377407 # ITB accesses +system.cpu2.dtb.read_hits 3222753 # DTB read hits +system.cpu2.dtb.read_misses 11767 # DTB read misses +system.cpu2.dtb.read_acv 114 # DTB read access violations +system.cpu2.dtb.read_accesses 216394 # DTB read accesses +system.cpu2.dtb.write_hits 1997746 # DTB write hits +system.cpu2.dtb.write_misses 2597 # DTB write misses +system.cpu2.dtb.write_acv 133 # DTB write access violations +system.cpu2.dtb.write_accesses 81219 # DTB write accesses +system.cpu2.dtb.data_hits 5220499 # DTB hits +system.cpu2.dtb.data_misses 14364 # DTB misses +system.cpu2.dtb.data_acv 247 # DTB access violations +system.cpu2.dtb.data_accesses 297613 # DTB accesses +system.cpu2.itb.fetch_hits 371919 # ITB hits +system.cpu2.itb.fetch_misses 5650 # ITB misses +system.cpu2.itb.fetch_acv 270 # ITB acv +system.cpu2.itb.fetch_accesses 377569 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1250,141 +1255,141 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30535693 # number of cpu cycles simulated +system.cpu2.numCycles 30487191 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8533990 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34964700 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8412639 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8133501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 621341 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9684407 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2608255 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90277 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26910349 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.299303 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8524791 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34873991 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8388883 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6032331 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8111828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 622665 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9676306 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1940 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 62420 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 80561 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2604903 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90729 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26874751 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.297649 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.309099 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18776848 69.78% 69.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4254202 15.81% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1630674 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18762923 69.82% 69.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 273694 1.02% 70.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 440641 1.64% 72.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4237897 15.77% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 736346 2.74% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 166761 0.62% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 196079 0.73% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433619 1.61% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1626791 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26910349 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.145044 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8661368 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9779389 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7537152 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 392385 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 168928 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12969 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34563096 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40760 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 392385 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9017327 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2819479 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5795758 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7393745 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1245780 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33400490 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 410986 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22419818 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41624592 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41459015 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20587002 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1832816 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3692921 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2097986 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 374319 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30873003 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30415505 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2194500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1105040 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26910349 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565605 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26874751 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.275161 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.143890 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8657787 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9768162 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7515953 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293497 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 393434 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168963 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12933 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34472576 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40526 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 393434 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9012684 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2836795 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5769605 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7372565 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1243759 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33316352 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2373 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 234595 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 408588 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22366948 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41510379 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41345500 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 164879 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20534540 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1832408 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 504738 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 60071 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3686935 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3385510 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2088081 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 373278 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 254690 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30792200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 629969 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30337437 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 32004 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2187587 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1093629 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 444846 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26874751 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.128845 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.565283 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15319532 56.93% 56.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3107477 11.55% 68.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1555924 5.78% 74.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5075651 18.86% 93.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 913363 3.39% 96.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 492005 1.83% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286833 1.07% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 17804 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15311841 56.97% 56.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3103500 11.55% 68.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1551808 5.77% 74.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5059769 18.83% 93.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 912287 3.39% 96.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 489619 1.82% 98.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286015 1.06% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141615 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18297 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26910349 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26874751 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113310 45.00% 58.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34821 13.89% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112497 44.88% 58.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 103352 41.23% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24705611 81.23% 81.24% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24640378 81.22% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20252 0.07% 81.30% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1222 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8482 0.03% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued @@ -1406,114 +1411,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3362290 11.05% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2024696 6.66% 99.05% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3354206 11.06% 92.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2020424 6.66% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 290023 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30415505 # Type of FU issued -system.cpu2.iq.rate 0.996064 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87793654 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33586184 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 30009842 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30540947 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30337437 # Type of FU issued +system.cpu2.iq.rate 0.995088 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 250670 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008263 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87595744 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33498169 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29934734 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 236555 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 115613 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 112132 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30462481 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123178 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 189585 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 420180 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 166079 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 417411 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 964 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4105 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 161809 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4731 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 22958 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 392385 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32790350 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224390 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2097986 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 129831 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196511 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30250749 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3250588 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 164756 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 393434 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2055085 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 212014 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32707784 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224122 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3385510 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2088081 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 559310 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 150319 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2295 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4105 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 66873 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 130024 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196897 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30173481 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3242841 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 163956 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1286376 # number of nop insts executed -system.cpu2.iew.exec_refs 5259365 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6817857 # Number of branches executed -system.cpu2.iew.exec_stores 2008777 # Number of stores executed -system.cpu2.iew.exec_rate 0.990668 # Inst execution rate -system.cpu2.iew.wb_sent 30155480 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30122471 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17393530 # num instructions producing a value -system.cpu2.iew.wb_consumers 20640200 # num instructions consuming a value +system.cpu2.iew.exec_nop 1285615 # number of nop insts executed +system.cpu2.iew.exec_refs 5247672 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6797242 # Number of branches executed +system.cpu2.iew.exec_stores 2004831 # Number of stores executed +system.cpu2.iew.exec_rate 0.989710 # Inst execution rate +system.cpu2.iew.wb_sent 30079535 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30046866 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17352028 # num instructions producing a value +system.cpu2.iew.wb_consumers 20589621 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.986468 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.985557 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.842756 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182289 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26517964 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.145283 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.851177 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2372790 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 185123 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182681 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26481317 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.143824 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.850690 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16375646 61.75% 61.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2329504 8.78% 70.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1218959 4.60% 75.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4807373 18.13% 93.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186921 0.70% 95.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 179411 0.68% 96.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 736843 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16366667 61.80% 61.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2324205 8.78% 70.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1216165 4.59% 75.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4790733 18.09% 93.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 501931 1.90% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186373 0.70% 95.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 179761 0.68% 96.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180772 0.68% 97.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 734710 2.77% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26517964 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30370564 # Number of instructions committed -system.cpu2.commit.committedOps 30370564 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26481317 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30289973 # Number of instructions committed +system.cpu2.commit.committedOps 30289973 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4905590 # Number of memory references committed -system.cpu2.commit.loads 2973683 # Number of loads committed -system.cpu2.commit.membars 65235 # Number of memory barriers committed -system.cpu2.commit.branches 6667985 # Number of branches committed -system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28908366 # Number of committed integer instructions. -system.cpu2.commit.function_calls 232233 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 736843 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4894371 # Number of memory references committed +system.cpu2.commit.loads 2968099 # Number of loads committed +system.cpu2.commit.membars 65019 # Number of memory barriers committed +system.cpu2.commit.branches 6647353 # Number of branches committed +system.cpu2.commit.fp_insts 110870 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28830509 # Number of committed integer instructions. +system.cpu2.commit.function_calls 231619 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 734710 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58454819 # The number of ROB reads -system.cpu2.rob.rob_writes 65882909 # The number of ROB writes -system.cpu2.timesIdled 242872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3625344 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29192895 # Number of Instructions Simulated -system.cpu2.committedOps 29192895 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29192895 # Number of Instructions Simulated -system.cpu2.cpi 1.045997 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.045997 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39779596 # number of integer regfile reads -system.cpu2.int_regfile_writes 21289109 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads -system.cpu2.misc_regfile_writes 260558 # number of misc regfile writes +system.cpu2.rob.rob_reads 58337288 # The number of ROB reads +system.cpu2.rob.rob_writes 65718838 # The number of ROB writes +system.cpu2.timesIdled 243105 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3612440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745337726 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29114232 # Number of Instructions Simulated +system.cpu2.committedOps 29114232 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29114232 # Number of Instructions Simulated +system.cpu2.cpi 1.047158 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.047158 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.954966 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.954966 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39679960 # number of integer regfile reads +system.cpu2.int_regfile_writes 21237504 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68414 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68689 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4591435 # number of misc regfile reads +system.cpu2.misc_regfile_writes 259923 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |