diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 5197 insertions, 5170 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 3b6b51422..a07783bfc 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906037 # Number of seconds simulated -sim_ticks 1906037467000 # Number of ticks simulated -final_tick 1906037467000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906049 # Number of seconds simulated +sim_ticks 1906048606500 # Number of ticks simulated +final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252781 # Simulator instruction rate (inst/s) -host_op_rate 252781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8583432112 # Simulator tick rate (ticks/s) -host_mem_usage 376892 # Number of bytes of host memory used -host_seconds 222.06 # Real time elapsed on the host -sim_insts 56132533 # Number of instructions simulated -sim_ops 56132533 # Number of ops (including micro ops) simulated +host_inst_rate 269376 # Simulator instruction rate (inst/s) +host_op_rate 269376 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9144869235 # Simulator tick rate (ticks/s) +host_mem_usage 376080 # Number of bytes of host memory used +host_seconds 208.43 # Real time elapsed on the host +sim_insts 56145568 # Number of instructions simulated +sim_ops 56145568 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1050496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25909440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1050496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1050496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7561088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7561088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25904384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1044672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1044672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7563136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7563136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16323 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404835 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118142 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118142 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 551141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13041708 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404756 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118174 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118174 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 548083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13042035 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13593353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 551141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 551141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3966915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3966915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3966915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 551141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13041708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13590621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 548083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 548083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3967966 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3967966 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3967966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 548083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13042035 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17560268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404835 # Number of read requests accepted -system.physmem.writeReqs 118142 # Number of write requests accepted -system.physmem.readBursts 404835 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118142 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25902720 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 7559680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25909440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7561088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17558587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404756 # Number of read requests accepted +system.physmem.writeReqs 118174 # Number of write requests accepted +system.physmem.readBursts 404756 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118174 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25897280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 7561536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25904384 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7563136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41709 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25494 # Per bank write bursts -system.physmem.perBankRdBursts::1 25705 # Per bank write bursts -system.physmem.perBankRdBursts::2 25829 # Per bank write bursts -system.physmem.perBankRdBursts::3 25773 # Per bank write bursts -system.physmem.perBankRdBursts::4 25090 # Per bank write bursts -system.physmem.perBankRdBursts::5 25012 # Per bank write bursts -system.physmem.perBankRdBursts::6 24715 # Per bank write bursts -system.physmem.perBankRdBursts::7 24579 # Per bank write bursts -system.physmem.perBankRdBursts::8 25194 # Per bank write bursts -system.physmem.perBankRdBursts::9 25292 # Per bank write bursts -system.physmem.perBankRdBursts::10 25390 # Per bank write bursts -system.physmem.perBankRdBursts::11 24989 # Per bank write bursts -system.physmem.perBankRdBursts::12 24533 # Per bank write bursts -system.physmem.perBankRdBursts::13 25560 # Per bank write bursts -system.physmem.perBankRdBursts::14 25835 # Per bank write bursts -system.physmem.perBankRdBursts::15 25740 # Per bank write bursts -system.physmem.perBankWrBursts::0 7824 # Per bank write bursts -system.physmem.perBankWrBursts::1 7665 # Per bank write bursts -system.physmem.perBankWrBursts::2 8071 # Per bank write bursts -system.physmem.perBankWrBursts::3 7733 # Per bank write bursts -system.physmem.perBankWrBursts::4 7203 # Per bank write bursts -system.physmem.perBankWrBursts::5 7017 # Per bank write bursts -system.physmem.perBankWrBursts::6 6707 # Per bank write bursts -system.physmem.perBankWrBursts::7 6431 # Per bank write bursts -system.physmem.perBankWrBursts::8 7312 # Per bank write bursts -system.physmem.perBankWrBursts::9 6902 # Per bank write bursts -system.physmem.perBankWrBursts::10 7273 # Per bank write bursts -system.physmem.perBankWrBursts::11 6973 # Per bank write bursts -system.physmem.perBankWrBursts::12 7066 # Per bank write bursts -system.physmem.perBankWrBursts::13 8009 # Per bank write bursts -system.physmem.perBankWrBursts::14 7985 # Per bank write bursts -system.physmem.perBankWrBursts::15 7949 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 303809 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25477 # Per bank write bursts +system.physmem.perBankRdBursts::1 25704 # Per bank write bursts +system.physmem.perBankRdBursts::2 25816 # Per bank write bursts +system.physmem.perBankRdBursts::3 25780 # Per bank write bursts +system.physmem.perBankRdBursts::4 25083 # Per bank write bursts +system.physmem.perBankRdBursts::5 25011 # Per bank write bursts +system.physmem.perBankRdBursts::6 24709 # Per bank write bursts +system.physmem.perBankRdBursts::7 24576 # Per bank write bursts +system.physmem.perBankRdBursts::8 25197 # Per bank write bursts +system.physmem.perBankRdBursts::9 25297 # Per bank write bursts +system.physmem.perBankRdBursts::10 25389 # Per bank write bursts +system.physmem.perBankRdBursts::11 25021 # Per bank write bursts +system.physmem.perBankRdBursts::12 24535 # Per bank write bursts +system.physmem.perBankRdBursts::13 25530 # Per bank write bursts +system.physmem.perBankRdBursts::14 25795 # Per bank write bursts +system.physmem.perBankRdBursts::15 25725 # Per bank write bursts +system.physmem.perBankWrBursts::0 7822 # Per bank write bursts +system.physmem.perBankWrBursts::1 7672 # Per bank write bursts +system.physmem.perBankWrBursts::2 8075 # Per bank write bursts +system.physmem.perBankWrBursts::3 7744 # Per bank write bursts +system.physmem.perBankWrBursts::4 7196 # Per bank write bursts +system.physmem.perBankWrBursts::5 7016 # Per bank write bursts +system.physmem.perBankWrBursts::6 6702 # Per bank write bursts +system.physmem.perBankWrBursts::7 6427 # Per bank write bursts +system.physmem.perBankWrBursts::8 7310 # Per bank write bursts +system.physmem.perBankWrBursts::9 6908 # Per bank write bursts +system.physmem.perBankWrBursts::10 7272 # Per bank write bursts +system.physmem.perBankWrBursts::11 7002 # Per bank write bursts +system.physmem.perBankWrBursts::12 7086 # Per bank write bursts +system.physmem.perBankWrBursts::13 7981 # Per bank write bursts +system.physmem.perBankWrBursts::14 7993 # Per bank write bursts +system.physmem.perBankWrBursts::15 7943 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 13 # Number of times write queue was full causing retry -system.physmem.totGap 1906028705500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 1906039923500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404835 # Read request sizes (log2) +system.physmem.readPktSize::6 404756 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118142 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 64 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118174 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,122 +148,124 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 519.304127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.318074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.802576 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14872 23.08% 23.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11053 17.15% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5024 7.80% 48.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3269 5.07% 53.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2580 4.00% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1937 3.01% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4194 6.51% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1317 2.04% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20191 31.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64437 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.190700 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2898.366893 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5309 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 519.603311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.318586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 407.156918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14830 23.03% 23.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11097 17.23% 40.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4950 7.69% 47.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3246 5.04% 52.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2531 3.93% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1970 3.06% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4174 6.48% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1358 2.11% 68.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20237 31.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64393 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5299 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5312 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5312 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.236446 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.912972 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.909399 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4665 87.82% 87.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.36% 88.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 18 0.34% 88.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 199 3.75% 92.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.09% 92.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.47% 92.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 40 0.75% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.11% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.43% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.11% 94.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.08% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.17% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.38% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.45% 95.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 32 0.60% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 171 3.22% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.08% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.06% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.08% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 8 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5312 # Writes before turning the bus around for reads -system.physmem.totQLat 2653633250 # Total ticks spent queuing -system.physmem.totMemAccLat 10242320750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6556.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5302 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.283855 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.921998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.156721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4666 88.00% 88.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 22 0.41% 88.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 20 0.38% 88.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 187 3.53% 92.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 6 0.11% 92.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.47% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 43 0.81% 93.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.11% 93.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.15% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.34% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.06% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 6 0.11% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 18 0.34% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.47% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 27 0.51% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.04% 95.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 172 3.24% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.13% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.06% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 7 0.13% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 8 0.15% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads +system.physmem.totQLat 2636864500 # Total ticks spent queuing +system.physmem.totMemAccLat 10223958250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6516.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25306.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25266.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s @@ -273,71 +275,71 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing -system.physmem.readRowHits 362859 # Number of row buffer hits during reads -system.physmem.writeRowHits 95554 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads +system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing +system.physmem.readRowHits 362818 # Number of row buffer hits during reads +system.physmem.writeRowHits 95583 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes -system.physmem.avgGap 3644574.63 # Average gap between requests -system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 238049280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 129888000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577136600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 380058480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67941192465 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1084023651750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278782921775 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.912502 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1803110214250 # Time in different power states -system.physmem_0.memoryStateTime::REF 63646700000 # Time in different power states +system.physmem.avgGap 3644923.65 # Average gap between requests +system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 237542760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 129611625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67952834145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084018111500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278788448510 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.912661 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1803102997000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39278414500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39293158000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249094440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135914625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579757400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385359120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68603580630 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1083442617750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278889269165 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.968292 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1802146960250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63646700000 # Time in different power states +system.physmem_1.actEnergy 249268320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136009500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68401366290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1083624670500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278869710170 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.955290 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1802449451000 # Time in different power states +system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 40241682250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 39946717750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15005157 # Number of BP lookups -system.cpu.branchPred.condPredicted 13016352 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370563 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9544476 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5200630 # Number of BTB hits +system.cpu.branchPred.lookups 15009028 # Number of BP lookups +system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 370758 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9666577 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5199223 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.488376 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807259 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30802 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.785564 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807911 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31459 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9242284 # DTB read hits -system.cpu.dtb.read_misses 17197 # DTB read misses +system.cpu.dtb.read_hits 9243045 # DTB read hits +system.cpu.dtb.read_misses 17179 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 765766 # DTB read accesses -system.cpu.dtb.write_hits 6387071 # DTB write hits -system.cpu.dtb.write_misses 2294 # DTB write misses -system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298411 # DTB write accesses -system.cpu.dtb.data_hits 15629355 # DTB hits -system.cpu.dtb.data_misses 19491 # DTB misses -system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1064177 # DTB accesses -system.cpu.itb.fetch_hits 4015320 # ITB hits -system.cpu.itb.fetch_misses 6841 # ITB misses -system.cpu.itb.fetch_acv 659 # ITB acv -system.cpu.itb.fetch_accesses 4022161 # ITB accesses +system.cpu.dtb.read_accesses 765860 # DTB read accesses +system.cpu.dtb.write_hits 6388437 # DTB write hits +system.cpu.dtb.write_misses 2336 # DTB write misses +system.cpu.dtb.write_acv 159 # DTB write access violations +system.cpu.dtb.write_accesses 298458 # DTB write accesses +system.cpu.dtb.data_hits 15631482 # DTB hits +system.cpu.dtb.data_misses 19515 # DTB misses +system.cpu.dtb.data_acv 370 # DTB access violations +system.cpu.dtb.data_accesses 1064318 # DTB accesses +system.cpu.itb.fetch_hits 4012772 # ITB hits +system.cpu.itb.fetch_misses 6839 # ITB misses +system.cpu.itb.fetch_acv 666 # ITB acv +system.cpu.itb.fetch_accesses 4019611 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -350,39 +352,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 223168437 # number of cpu cycles simulated +system.cpu.numCycles 221706697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56132533 # Number of instructions committed -system.cpu.committedOps 56132533 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2504504 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5489 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3590815720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.975741 # CPI: cycles per instruction -system.cpu.ipc 0.251525 # IPC: instructions per cycle +system.cpu.committedInsts 56145568 # Number of instructions committed +system.cpu.committedOps 56145568 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2506376 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5532 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3590390516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.948784 # CPI: cycles per instruction +system.cpu.ipc 0.253243 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211546 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74811 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211538 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74805 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105910 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182756 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73444 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105906 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182748 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73444 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148923 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837436986000 96.40% 96.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 81017000 0.00% 96.41% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 682412000 0.04% 96.44% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 67836062500 3.56% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1906036477500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981727 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837271257000 96.39% 96.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 67985555000 3.57% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693457 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814873 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693436 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814860 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -421,112 +423,112 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175591 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175581 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5129 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192481 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.callpal::total 192472 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.325047 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324370 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393243 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 38636753000 2.03% 2.03% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4528404000 0.24% 2.26% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862871310500 97.74% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392706 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 86394668 # Number of cycles that the object actually ticked -system.cpu.idleCycles 136773769 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395457 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.977331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13772866 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395969 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.866169 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 121717500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.977331 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy +system.cpu.tickCycles 84511190 # Number of cycles that the object actually ticked +system.cpu.idleCycles 137195507 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395430 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.867732 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63663599 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63663599 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7815159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5575814 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5575814 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182834 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182834 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199026 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199026 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13390973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13390973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13390973 # number of overall hits -system.cpu.dcache.overall_hits::total 13390973 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201770 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201770 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 575091 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 575091 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17213 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17213 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1776861 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1776861 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1776861 # number of overall misses -system.cpu.dcache.overall_misses::total 1776861 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 46961675000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 46961675000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33993891500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33993891500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 235176000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 235176000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80955566500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80955566500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80955566500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80955566500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9016929 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9016929 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150905 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150905 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200047 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200047 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199026 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199026 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15167834 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15167834 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15167834 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15167834 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133279 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133279 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093497 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093497 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117147 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117147 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117147 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39077.090458 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39077.090458 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59110.456432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59110.456432 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13662.696799 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13662.696799 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45561.001395 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45561.001395 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63671171 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63671171 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7816045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576846 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576846 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182827 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182827 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199029 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199029 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13392891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392891 # number of overall hits +system.cpu.dcache.overall_hits::total 13392891 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201631 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201631 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 575205 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 575205 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17224 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776836 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses +system.cpu.dcache.overall_misses::total 1776836 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974936500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46974936500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956179000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33956179000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80931115500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80931115500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80931115500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80931115500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152051 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200051 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200051 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15169727 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15169727 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15169727 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15169727 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093498 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093498 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086098 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086098 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117130 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45547.881459 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45547.881459 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,129 +537,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838295 # number of writebacks -system.cpu.dcache.writebacks::total 838295 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127341 # 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miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011173 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249378 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249378 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011173 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278565 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141825 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011173 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278565 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141825 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,132 +817,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76630 # number of writebacks -system.cpu.l2cache.writebacks::total 76630 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 317 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 317 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16415 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16415 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272186 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272186 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16415 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388836 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405251 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16415 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388836 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405251 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9622 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9622 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16552 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16552 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1214500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1214500 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1987583500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44646880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46634463500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364010000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364010000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931836500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931836500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3295846500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3295846500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383239 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383239 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011240 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249344 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249344 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141874 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141874 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71441.176471 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71441.176471 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117402.850407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117402.850407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121083.368870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121083.368870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113715.758709 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113715.758709 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196826.839827 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196826.839827 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200772.864269 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200772.864269 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199120.740696 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199120.740696 # average overall mshr uncacheable latency +system.cpu.l2cache.writebacks::writebacks 76662 # number of writebacks +system.cpu.l2cache.writebacks::total 76662 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116659 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116659 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16324 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16324 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272207 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272207 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16324 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388866 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405190 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16324 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388866 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405190 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13670938000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13670938000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978703000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978703000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960659500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960659500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978703000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631597500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46610300500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978703000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631597500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46610300500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443571000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443571000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3495402500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3495402500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383225 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011173 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249378 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249378 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141825 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5711775 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2855459 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1248 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2559171 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 956450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2277896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304379 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304379 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1460498 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559702 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 956425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1459802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 818923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091718 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4380147 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219373 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8599520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93467712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143047028 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236514740 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422969 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6151080 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000871 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.029504 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4381906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8601216 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186932672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041565 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 329974237 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 423215 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3296619 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001032 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032108 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6145721 99.91% 99.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5359 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3293217 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3402 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6151080 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3707269500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 284383 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3296619 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5168164000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2190955582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2191892463 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105716998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105680997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -948,81 +953,81 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51174 # Transaction distribution -system.iobus.trans_dist::WriteResp 51174 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5100 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7107 # Transaction distribution +system.iobus.trans_dist::ReadResp 7107 # Transaction distribution +system.iobus.trans_dist::WriteReq 51176 # Transaction distribution +system.iobus.trans_dist::WriteResp 51176 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5110 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33104 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116554 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116566 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44340 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44381 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705948 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4711000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 386000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 186500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14813500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 224500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 98500 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 142500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215087245 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215092991 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23482000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.290787 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.290814 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1748608829000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.290787 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080674 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080674 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1748612865000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.290814 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080676 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080676 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1036,14 +1041,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21943883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21943883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427163362 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427163362 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21943883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21943883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21943883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21943883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21944383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21944383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429292608 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5429292608 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21944383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21944383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21944383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21944383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1060,19 +1065,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126843.254335 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126843.254335 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130611.363159 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130611.363159 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126843.254335 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126843.254335 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126846.144509 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126846.144509 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130662.606084 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130662.606084 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126846.144509 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126846.144509 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 77 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.833333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1086,14 +1091,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13293883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13293883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3349563362 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3349563362 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13293883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13293883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13293883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13293883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13294383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351692608 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3351692608 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13294383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13294383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13294383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13294383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1102,63 +1107,63 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76843.254335 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80611.363159 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80611.363159 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76846.144509 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80662.606084 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80662.606084 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295688 # Transaction distribution -system.membus.trans_dist::WriteReq 9622 # Transaction distribution -system.membus.trans_dist::WriteResp 9622 # Transaction distribution -system.membus.trans_dist::Writeback 118142 # Transaction distribution -system.membus.trans_dist::CleanEvict 262192 # Transaction distribution -system.membus.trans_dist::UpgradeReq 159 # Transaction distribution -system.membus.trans_dist::UpgradeResp 159 # Transaction distribution -system.membus.trans_dist::ReadExReq 116508 # Transaction distribution -system.membus.trans_dist::ReadExResp 116508 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288774 # Transaction distribution +system.membus.trans_dist::ReadReq 6934 # Transaction distribution +system.membus.trans_dist::ReadResp 295622 # Transaction distribution +system.membus.trans_dist::WriteReq 9624 # Transaction distribution +system.membus.trans_dist::WriteResp 9624 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118174 # Transaction distribution +system.membus.trans_dist::CleanEvict 262081 # Transaction distribution +system.membus.trans_dist::UpgradeReq 178 # Transaction distribution +system.membus.trans_dist::UpgradeResp 178 # Transaction distribution +system.membus.trans_dist::ReadExReq 116499 # Transaction distribution +system.membus.trans_dist::ReadExResp 116499 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288704 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1149038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148839 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1182174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181987 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306991 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44340 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30812800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30857140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1306804 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44381 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854173 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33514868 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33511901 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 844052 # Request fanout histogram +system.membus.snoop_fanout::samples 843925 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 844052 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843925 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 844052 # Request fanout histogram -system.membus.reqLayer0.occupancy 29776500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843925 # Request fanout histogram +system.membus.reqLayer0.occupancy 29573500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319401645 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319381154 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160603841 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160247074 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69882415 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index c3ff68c1f..4156232eb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.921764 # Number of seconds simulated -sim_ticks 1921763645000 # Number of ticks simulated -final_tick 1921763645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922762 # Number of seconds simulated +sim_ticks 1922761887500 # Number of ticks simulated +final_tick 1922761887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133766 # Simulator instruction rate (inst/s) -host_op_rate 133766 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4532754153 # Simulator tick rate (ticks/s) -host_mem_usage 384052 # Number of bytes of host memory used -host_seconds 423.97 # Real time elapsed on the host -sim_insts 56713315 # Number of instructions simulated -sim_ops 56713315 # Number of ops (including micro ops) simulated +host_inst_rate 132982 # Simulator instruction rate (inst/s) +host_op_rate 132982 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4507220686 # Simulator tick rate (ticks/s) +host_mem_usage 384024 # Number of bytes of host memory used +host_seconds 426.60 # Real time elapsed on the host +sim_insts 56729467 # Number of instructions simulated +sim_ops 56729467 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 874240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24774144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 869760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24778624 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 514944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 515712 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26267328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 874240 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 26268096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 869760 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7875136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7875136 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13660 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387096 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::total 972800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7882944 # Number of bytes written to this memory +system.physmem.bytes_written::total 7882944 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13590 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387166 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8046 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8058 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410427 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123049 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123049 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 454915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12891358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 267954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13668345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 454915 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53617 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 508533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4097869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4097869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4097869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 454915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12891358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 267954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17766214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410427 # Number of read requests accepted -system.physmem.writeReqs 123049 # Number of write requests accepted -system.physmem.readBursts 410427 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123049 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26259904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7874176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26267328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7875136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410439 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123171 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123171 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 452349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12886996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 268214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13661648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 452349 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4099803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4099803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4099803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 452349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12886996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 268214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17761450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410439 # Number of read requests accepted +system.physmem.writeReqs 123171 # Number of write requests accepted +system.physmem.readBursts 410439 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123171 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26260800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue +system.physmem.bytesWritten 7881088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26268096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7882944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 46661 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25500 # Per bank write bursts -system.physmem.perBankRdBursts::1 25969 # Per bank write bursts -system.physmem.perBankRdBursts::2 26011 # Per bank write bursts -system.physmem.perBankRdBursts::3 25727 # Per bank write bursts -system.physmem.perBankRdBursts::4 25508 # Per bank write bursts -system.physmem.perBankRdBursts::5 25811 # Per bank write bursts -system.physmem.perBankRdBursts::6 25519 # Per bank write bursts -system.physmem.perBankRdBursts::7 25160 # Per bank write bursts -system.physmem.perBankRdBursts::8 25451 # Per bank write bursts -system.physmem.perBankRdBursts::9 25839 # Per bank write bursts -system.physmem.perBankRdBursts::10 25659 # Per bank write bursts -system.physmem.perBankRdBursts::11 25030 # Per bank write bursts -system.physmem.perBankRdBursts::12 26076 # Per bank write bursts -system.physmem.perBankRdBursts::13 25978 # Per bank write bursts -system.physmem.perBankRdBursts::14 25473 # Per bank write bursts -system.physmem.perBankRdBursts::15 25600 # Per bank write bursts -system.physmem.perBankWrBursts::0 8066 # Per bank write bursts -system.physmem.perBankWrBursts::1 8046 # Per bank write bursts -system.physmem.perBankWrBursts::2 8027 # Per bank write bursts -system.physmem.perBankWrBursts::3 7668 # Per bank write bursts -system.physmem.perBankWrBursts::4 7376 # Per bank write bursts -system.physmem.perBankWrBursts::5 7761 # Per bank write bursts -system.physmem.perBankWrBursts::6 7583 # Per bank write bursts -system.physmem.perBankWrBursts::7 6991 # Per bank write bursts -system.physmem.perBankWrBursts::8 7326 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 309493 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25497 # Per bank write bursts +system.physmem.perBankRdBursts::1 25956 # Per bank write bursts +system.physmem.perBankRdBursts::2 26004 # Per bank write bursts +system.physmem.perBankRdBursts::3 25724 # Per bank write bursts +system.physmem.perBankRdBursts::4 25504 # Per bank write bursts +system.physmem.perBankRdBursts::5 25939 # Per bank write bursts +system.physmem.perBankRdBursts::6 25634 # Per bank write bursts +system.physmem.perBankRdBursts::7 25247 # Per bank write bursts +system.physmem.perBankRdBursts::8 25446 # Per bank write bursts +system.physmem.perBankRdBursts::9 25836 # Per bank write bursts +system.physmem.perBankRdBursts::10 25660 # Per bank write bursts +system.physmem.perBankRdBursts::11 25037 # Per bank write bursts +system.physmem.perBankRdBursts::12 26054 # Per bank write bursts +system.physmem.perBankRdBursts::13 25864 # Per bank write bursts +system.physmem.perBankRdBursts::14 25329 # Per bank write bursts +system.physmem.perBankRdBursts::15 25594 # Per bank write bursts +system.physmem.perBankWrBursts::0 8072 # Per bank write bursts +system.physmem.perBankWrBursts::1 8040 # Per bank write bursts +system.physmem.perBankWrBursts::2 8032 # Per bank write bursts +system.physmem.perBankWrBursts::3 7672 # Per bank write bursts +system.physmem.perBankWrBursts::4 7388 # Per bank write bursts +system.physmem.perBankWrBursts::5 7843 # Per bank write bursts +system.physmem.perBankWrBursts::6 7702 # Per bank write bursts +system.physmem.perBankWrBursts::7 7083 # Per bank write bursts +system.physmem.perBankWrBursts::8 7329 # Per bank write bursts system.physmem.perBankWrBursts::9 7600 # Per bank write bursts -system.physmem.perBankWrBursts::10 7532 # Per bank write bursts -system.physmem.perBankWrBursts::11 7413 # Per bank write bursts -system.physmem.perBankWrBursts::12 7962 # Per bank write bursts -system.physmem.perBankWrBursts::13 8267 # Per bank write bursts -system.physmem.perBankWrBursts::14 7722 # Per bank write bursts +system.physmem.perBankWrBursts::10 7538 # Per bank write bursts +system.physmem.perBankWrBursts::11 7420 # Per bank write bursts +system.physmem.perBankWrBursts::12 7961 # Per bank write bursts +system.physmem.perBankWrBursts::13 8153 # Per bank write bursts +system.physmem.perBankWrBursts::14 7615 # Per bank write bursts system.physmem.perBankWrBursts::15 7694 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 1921759329500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times write queue was full causing retry +system.physmem.totGap 1922757529500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410427 # Read request sizes (log2) +system.physmem.readPktSize::6 410439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123049 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123171 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,199 +158,199 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 72 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65305 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 522.687084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.252168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 410.914363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14928 22.86% 22.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11344 17.37% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5465 8.37% 48.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2873 4.40% 53.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2572 3.94% 56.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1636 2.51% 59.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3782 5.79% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1204 1.84% 67.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21501 32.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65305 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5548 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.956561 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2834.723442 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5545 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 45 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 522.630582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.337054 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.684018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14917 22.83% 22.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11339 17.36% 40.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5448 8.34% 48.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2879 4.41% 52.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2603 3.98% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1650 2.53% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3828 5.86% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1203 1.84% 67.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21460 32.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65327 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5559 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.810757 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2831.423020 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5556 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5548 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.176280 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.947134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.868875 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4772 86.01% 86.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 155 2.79% 88.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 19 0.34% 89.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 186 3.35% 92.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 8 0.14% 92.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.38% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.74% 93.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 18 0.32% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 27 0.49% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.16% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.36% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.43% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 29 0.52% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 158 2.85% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5559 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5559 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.151826 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.921629 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.873132 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4760 85.63% 85.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 185 3.33% 88.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.47% 89.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 178 3.20% 92.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 6 0.11% 92.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.31% 93.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 45 0.81% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.07% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.27% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.36% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.16% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 23 0.41% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 22 0.40% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 34 0.61% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 160 2.88% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.04% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.05% 99.32% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.04% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.07% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 14 0.25% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.05% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 11 0.20% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5548 # Writes before turning the bus around for reads -system.physmem.totQLat 4465229000 # Total ticks spent queuing -system.physmem.totMemAccLat 12158560250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10882.55 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5559 # Writes before turning the bus around for reads +system.physmem.totQLat 4492977750 # Total ticks spent queuing +system.physmem.totMemAccLat 12186571500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051625000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10949.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29632.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29699.80 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.67 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing -system.physmem.readRowHits 369445 # Number of row buffer hits during reads -system.physmem.writeRowHits 98595 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes -system.physmem.avgGap 3602335.12 # Average gap between requests +system.physmem.avgWrQLen 25.48 # Average write queue length when enqueuing +system.physmem.readRowHits 369433 # Number of row buffer hits during reads +system.physmem.writeRowHits 98707 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.14 # Row buffer hit rate for writes +system.physmem.avgGap 3603301.16 # Average gap between requests system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245919240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134182125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1600599000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 398636640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63180018945 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097637063000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1288716655350 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.590642 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1825809460500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64171900000 # Time in different power states +system.physmem_0.actEnergy 247242240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134904000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1602939000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 400671360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63449600445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1097998572000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289419261125 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.608464 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1826410636250 # Time in different power states +system.physmem_0.memoryStateTime::REF 64205180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31782207000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32144391250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247786560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135201000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1599826800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398623680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62993858085 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1097800353750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1288695886275 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.579840 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1826084104500 # Time in different power states -system.physmem_1.memoryStateTime::REF 64171900000 # Time in different power states +system.physmem_1.actEnergy 246629880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134569875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597596000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397288800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62800369875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1098568064250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289329850760 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.561968 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1827364141250 # Time in different power states +system.physmem_1.memoryStateTime::REF 64205180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31507549250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31190872500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16172722 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14147320 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 315974 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10263532 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5327857 # Number of BTB hits +system.cpu0.branchPred.lookups 16164803 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14134057 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 313974 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10204663 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5324382 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.910561 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 805529 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17788 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 52.175971 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 806868 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17359 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9178933 # DTB read hits -system.cpu0.dtb.read_misses 32423 # DTB read misses -system.cpu0.dtb.read_acv 530 # DTB read access violations -system.cpu0.dtb.read_accesses 683199 # DTB read accesses -system.cpu0.dtb.write_hits 5878949 # DTB write hits -system.cpu0.dtb.write_misses 7260 # DTB write misses -system.cpu0.dtb.write_acv 384 # DTB write access violations -system.cpu0.dtb.write_accesses 235377 # DTB write accesses -system.cpu0.dtb.data_hits 15057882 # DTB hits -system.cpu0.dtb.data_misses 39683 # DTB misses -system.cpu0.dtb.data_acv 914 # DTB access violations -system.cpu0.dtb.data_accesses 918576 # DTB accesses -system.cpu0.itb.fetch_hits 1433805 # ITB hits -system.cpu0.itb.fetch_misses 20098 # ITB misses -system.cpu0.itb.fetch_acv 602 # ITB acv -system.cpu0.itb.fetch_accesses 1453903 # ITB accesses +system.cpu0.dtb.read_hits 9175640 # DTB read hits +system.cpu0.dtb.read_misses 32141 # DTB read misses +system.cpu0.dtb.read_acv 535 # DTB read access violations +system.cpu0.dtb.read_accesses 683139 # DTB read accesses +system.cpu0.dtb.write_hits 5880520 # DTB write hits +system.cpu0.dtb.write_misses 7287 # DTB write misses +system.cpu0.dtb.write_acv 388 # DTB write access violations +system.cpu0.dtb.write_accesses 235457 # DTB write accesses +system.cpu0.dtb.data_hits 15056160 # DTB hits +system.cpu0.dtb.data_misses 39428 # DTB misses +system.cpu0.dtb.data_acv 923 # DTB access violations +system.cpu0.dtb.data_accesses 918596 # DTB accesses +system.cpu0.itb.fetch_hits 1432352 # ITB hits +system.cpu0.itb.fetch_misses 20066 # ITB misses +system.cpu0.itb.fetch_acv 603 # ITB acv +system.cpu0.itb.fetch_accesses 1452418 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -363,256 +363,255 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 146988157 # number of cpu cycles simulated +system.cpu0.numCycles 147492353 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26434329 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70323281 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16172722 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6133386 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 112438747 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1062414 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 847 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 30229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 925731 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 462393 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 403 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8125656 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 231201 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 140823886 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.499370 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.736005 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26474453 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70295181 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16164803 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6131250 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 112661982 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1056864 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 660 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 29689 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 929577 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 461648 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 350 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8123308 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 229144 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 141086791 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.498241 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.734215 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 127673480 90.66% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 835079 0.59% 91.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1817427 1.29% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 778983 0.55% 93.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2600412 1.85% 94.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 568090 0.40% 95.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 652333 0.46% 95.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 824353 0.59% 96.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5073729 3.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 127943316 90.68% 90.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 834789 0.59% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1813592 1.29% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 779670 0.55% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2595829 1.84% 94.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 572321 0.41% 95.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 651682 0.46% 95.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 825551 0.59% 96.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5070041 3.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 140823886 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.110027 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.478428 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21407057 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108692435 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8462793 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1765937 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 495663 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 515138 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35957 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61540375 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 109013 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 495663 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22243524 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 77757616 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19856258 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9307175 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11163648 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59419645 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 199110 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2023904 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 235068 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7176378 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39704161 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72277966 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72138515 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 129817 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34987460 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4716693 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1464722 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 211632 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12540163 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9262921 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6150917 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1355884 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 997025 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52994830 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1876718 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52216371 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52644 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6477091 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2861227 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1292062 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 140823886 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.370792 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088351 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 141086791 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109598 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.476602 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21397284 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108971969 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8457985 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1766417 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 493135 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 516601 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35757 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61523411 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 108836 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 493135 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22231623 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 77943277 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19950150 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9304003 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11164601 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59421423 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 199471 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2023547 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 224739 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7186522 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39708138 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72284773 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72145342 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 129802 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34979364 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4728766 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1463848 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 211077 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12544775 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9257817 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6153108 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1360057 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1005705 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53010072 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1876155 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52220775 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 51551 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6501427 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2875305 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1291728 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 141086791 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.370132 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.087511 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 119350315 84.75% 84.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9307127 6.61% 91.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3871720 2.75% 94.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2724493 1.93% 96.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2821208 2.00% 98.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1374944 0.98% 99.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 898986 0.64% 99.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 361887 0.26% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 113206 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 119618317 84.78% 84.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9300566 6.59% 91.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3865351 2.74% 94.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2730572 1.94% 96.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2821391 2.00% 98.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1375833 0.98% 99.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 902269 0.64% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 360488 0.26% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 112004 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 140823886 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 141086791 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 180499 18.19% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 473486 47.73% 65.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 338115 34.08% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 182068 18.38% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 471621 47.60% 65.98% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 337015 34.02% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35829212 68.62% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56563 0.11% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28580 0.05% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35835166 68.62% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56519 0.11% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28571 0.05% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9526937 18.25% 87.04% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5949680 11.39% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 819736 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9523186 18.24% 87.03% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5952100 11.40% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 819570 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52216371 # Type of FU issued -system.cpu0.iq.rate 0.355242 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 992101 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019000 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 245730281 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61098362 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50826597 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 571091 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267903 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 262355 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52896880 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 307812 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 579556 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52220775 # Type of FU issued +system.cpu0.iq.rate 0.354058 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 990706 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018971 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 245999962 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61137242 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50831283 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 570635 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 267757 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 262095 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52900144 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307557 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 581308 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1070231 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2809 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17956 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 496898 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1065241 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3900 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17685 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 500436 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18718 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 406168 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18736 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 408208 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 495663 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 74229287 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1063310 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58247929 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 119878 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9262921 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6150917 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1658630 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39535 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 822687 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17956 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 156887 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351474 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 508361 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51713827 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9234499 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 502543 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 493135 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 74418027 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1058724 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58259516 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 116557 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9257817 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6153108 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1657861 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39988 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 817674 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17685 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 153306 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 351909 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 505215 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51717296 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9230924 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 503478 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3376381 # number of nop insts executed -system.cpu0.iew.exec_refs 15134335 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8213447 # Number of branches executed -system.cpu0.iew.exec_stores 5899836 # Number of stores executed -system.cpu0.iew.exec_rate 0.351823 # Inst execution rate -system.cpu0.iew.wb_sent 51204042 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51088952 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26321891 # num instructions producing a value -system.cpu0.iew.wb_consumers 36458900 # num instructions consuming a value +system.cpu0.iew.exec_nop 3373289 # number of nop insts executed +system.cpu0.iew.exec_refs 15132335 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8216790 # Number of branches executed +system.cpu0.iew.exec_stores 5901411 # Number of stores executed +system.cpu0.iew.exec_rate 0.350644 # Inst execution rate +system.cpu0.iew.wb_sent 51207379 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51093378 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26334207 # num instructions producing a value +system.cpu0.iew.wb_consumers 36473944 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.347572 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.721961 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.346414 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.722001 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6803374 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 584656 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 464905 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 139620670 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.367725 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.257359 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6824839 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 584427 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 463110 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 139882457 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.366962 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.256012 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 121488072 87.01% 87.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7189020 5.15% 92.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3942453 2.82% 94.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2051651 1.47% 96.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1610967 1.15% 97.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 576073 0.41% 98.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 437348 0.31% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 435843 0.31% 98.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1889243 1.35% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 121750983 87.04% 87.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7187616 5.14% 92.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3944064 2.82% 95.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2051217 1.47% 96.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1611428 1.15% 97.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 577022 0.41% 98.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 437359 0.31% 98.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 434985 0.31% 98.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1887783 1.35% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 139620670 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51342045 # Number of instructions committed -system.cpu0.commit.committedOps 51342045 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 139882457 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51331530 # Number of instructions committed +system.cpu0.commit.committedOps 51331530 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13846709 # Number of memory references committed -system.cpu0.commit.loads 8192690 # Number of loads committed -system.cpu0.commit.membars 198882 # Number of memory barriers committed -system.cpu0.commit.branches 7762297 # Number of branches committed -system.cpu0.commit.fp_insts 259271 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47551840 # Number of committed integer instructions. -system.cpu0.commit.function_calls 657143 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2951360 5.75% 5.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33433980 65.12% 70.87% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55376 0.11% 70.98% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.98% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28117 0.05% 71.03% # Class of committed instruction +system.cpu0.commit.refs 13845248 # Number of memory references committed +system.cpu0.commit.loads 8192576 # Number of loads committed +system.cpu0.commit.membars 198790 # Number of memory barriers committed +system.cpu0.commit.branches 7761926 # Number of branches committed +system.cpu0.commit.fp_insts 259003 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47542487 # Number of committed integer instructions. +system.cpu0.commit.function_calls 656882 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2950502 5.75% 5.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33426097 65.12% 70.87% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55327 0.11% 70.97% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28109 0.05% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction @@ -638,324 +637,326 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8391572 16.34% 87.38% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5660021 11.02% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 819736 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8391366 16.35% 87.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5658677 11.02% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 819569 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51342045 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1889243 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 195675599 # The number of ROB reads -system.cpu0.rob.rob_writes 117488366 # The number of ROB writes -system.cpu0.timesIdled 519286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6164271 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3696539134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48394452 # Number of Instructions Simulated -system.cpu0.committedOps 48394452 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 3.037294 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.037294 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.329240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.329240 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67992315 # number of integer regfile reads -system.cpu0.int_regfile_writes 36972661 # number of integer regfile writes -system.cpu0.fp_regfile_reads 128885 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130381 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1712039 # number of misc regfile reads -system.cpu0.misc_regfile_writes 819549 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1282830 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.258957 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10531989 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1283342 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.206689 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.258957 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988787 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988787 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 51331530 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1887783 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 195950193 # The number of ROB reads +system.cpu0.rob.rob_writes 117511428 # The number of ROB writes +system.cpu0.timesIdled 525574 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6405562 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3698031423 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48384795 # Number of Instructions Simulated +system.cpu0.committedOps 48384795 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.048320 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.048320 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.328050 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.328050 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67995096 # number of integer regfile reads +system.cpu0.int_regfile_writes 36974255 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128760 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130249 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1711265 # number of misc regfile reads +system.cpu0.misc_regfile_writes 819270 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1282737 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.160384 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10524244 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1283249 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.201249 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.160384 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988595 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988595 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56925383 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56925383 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6490454 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6490454 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3680062 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3680062 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162917 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 162917 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187619 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 187619 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10170516 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10170516 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10170516 # number of overall hits -system.cpu0.dcache.overall_hits::total 10170516 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1594902 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1594902 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1768783 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1768783 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20957 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20957 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2842 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2842 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3363685 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3363685 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3363685 # number of overall misses -system.cpu0.dcache.overall_misses::total 3363685 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54779472000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54779472000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114120076576 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114120076576 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 388638000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 388638000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44723000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44723000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 168899548576 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 168899548576 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 168899548576 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 168899548576 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8085356 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8085356 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5448845 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5448845 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183874 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183874 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190461 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190461 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13534201 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13534201 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13534201 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13534201 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197258 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197258 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324616 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324616 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113975 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113975 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014922 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014922 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248532 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248532 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248532 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248532 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34346.606876 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34346.606876 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64518.980890 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64518.980890 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18544.543589 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18544.543589 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15736.453202 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15736.453202 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50212.653259 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50212.653259 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6977235 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 18493 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 119566 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 125 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.354674 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 147.944000 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 56891628 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56891628 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6483780 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6483780 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3678701 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3678701 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162607 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 162607 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187520 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 187520 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10162481 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10162481 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10162481 # number of overall hits +system.cpu0.dcache.overall_hits::total 10162481 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1594725 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1594725 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1768883 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1768883 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21044 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21044 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2856 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2856 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3363608 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3363608 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3363608 # number of overall misses +system.cpu0.dcache.overall_misses::total 3363608 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54837998000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54837998000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114303059042 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114303059042 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389087500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 389087500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45510000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45510000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 169141057042 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 169141057042 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 169141057042 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 169141057042 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8078505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8078505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5447584 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5447584 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183651 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183651 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190376 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 190376 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13526089 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13526089 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13526089 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13526089 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197403 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197403 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324710 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324710 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114587 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114587 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248676 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248676 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248676 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248676 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34387.118782 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34387.118782 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64618.778654 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64618.778654 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50285.603151 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50285.603151 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50285.603151 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50285.603151 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6995611 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 14546 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119540 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 103 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.521089 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 141.223301 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 756224 # number of writebacks -system.cpu0.dcache.writebacks::total 756224 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579464 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 579464 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502811 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1502811 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5193 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5193 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082275 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2082275 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082275 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2082275 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015438 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1015438 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265972 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 265972 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15764 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15764 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2841 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2841 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281410 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1281410 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281410 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1281410 # number of overall MSHR misses +system.cpu0.dcache.writebacks::writebacks 756067 # number of writebacks +system.cpu0.dcache.writebacks::total 756067 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579442 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 579442 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502906 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1502906 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5209 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5209 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082348 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2082348 # 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number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1281260 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281260 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1281260 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10125 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17170 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43462270000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43462270000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18192812239 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18192812239 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186019000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186019000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41882000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41882000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61655082239 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61655082239 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61655082239 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 61655082239 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1482526500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1482526500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2174117500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2174117500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3656644000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3656644000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048813 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048813 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014916 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014916 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094679 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094679 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42801.500436 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42801.500436 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68401.231103 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68401.231103 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11800.241056 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11800.241056 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14741.992256 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14741.992256 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210436.692690 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210436.692690 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214727.654321 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214727.654321 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212967.035527 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212967.035527 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10126 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10126 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17171 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17171 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43466083500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43466083500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18236016784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18236016784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 187455000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 187455000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42654000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42654000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61702100284 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61702100284 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61702100284 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61702100284 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563410000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563410000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2299016000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2299016000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3862426000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3862426000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125677 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125677 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048825 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048825 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086223 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086223 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094725 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094725 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.790900 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.790900 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.382401 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.382401 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48157.360945 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48157.360945 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48157.360945 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48157.360945 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221917.672108 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221917.672108 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224938.908625 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224938.908625 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 909478 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.072720 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7170024 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 909987 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.879260 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42291813500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.072720 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992330 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992330 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 908501 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.069795 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7168696 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 909010 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.886267 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42372449500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.069795 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992324 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992324 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9035950 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9035950 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7170024 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7170024 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7170024 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7170024 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7170024 # number of overall hits -system.cpu0.icache.overall_hits::total 7170024 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 955631 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 955631 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 955631 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 955631 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 955631 # number of overall misses -system.cpu0.icache.overall_misses::total 955631 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14538250986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14538250986 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14538250986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14538250986 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14538250986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14538250986 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8125655 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8125655 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8125655 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8125655 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8125655 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8125655 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117607 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117607 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117607 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117607 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117607 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117607 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15213.247567 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15213.247567 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15213.247567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15213.247567 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8860 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9032627 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9032627 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7168696 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7168696 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7168696 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7168696 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7168696 # number of overall hits +system.cpu0.icache.overall_hits::total 7168696 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 954611 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 954611 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 954611 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 954611 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 954611 # number of overall misses +system.cpu0.icache.overall_misses::total 954611 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14636609987 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14636609987 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14636609987 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14636609987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14636609987 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14636609987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8123307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8123307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8123307 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8123307 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8123307 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8123307 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117515 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117515 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117515 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117515 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117515 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117515 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15332.538581 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15332.538581 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15332.538581 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15332.538581 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15332.538581 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15332.538581 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8572 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 285 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 278 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 31.087719 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.834532 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45336 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45336 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45336 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45336 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45336 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45336 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 910295 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 910295 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 910295 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 910295 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 910295 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 910295 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12844771491 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12844771491 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12844771491 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12844771491 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12844771491 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12844771491 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112027 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.112027 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.112027 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14110.559204 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 908501 # number of writebacks +system.cpu0.icache.writebacks::total 908501 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45291 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45291 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45291 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45291 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45291 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45291 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909320 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 909320 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 909320 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 909320 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 909320 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 909320 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12934939493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12934939493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12934939493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12934939493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12934939493 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12934939493 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111940 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111940 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14224.848780 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14224.848780 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14224.848780 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3566695 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3123821 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 62988 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1777720 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 839763 # Number of BTB hits +system.cpu1.branchPred.lookups 3578846 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3133511 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 63586 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2063930 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 845641 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 47.238204 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 169438 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 5003 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 40.972368 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 169933 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4992 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1880373 # DTB read hits -system.cpu1.dtb.read_misses 9576 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 286028 # DTB read accesses -system.cpu1.dtb.write_hits 1172828 # DTB write hits -system.cpu1.dtb.write_misses 2034 # DTB write misses +system.cpu1.dtb.read_hits 1885255 # DTB read hits +system.cpu1.dtb.read_misses 9531 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 285831 # DTB read accesses +system.cpu1.dtb.write_hits 1175917 # DTB write hits +system.cpu1.dtb.write_misses 2028 # DTB write misses system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 108538 # DTB write accesses -system.cpu1.dtb.data_hits 3053201 # DTB hits -system.cpu1.dtb.data_misses 11610 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 394566 # DTB accesses -system.cpu1.itb.fetch_hits 516269 # ITB hits -system.cpu1.itb.fetch_misses 4737 # ITB misses -system.cpu1.itb.fetch_acv 64 # ITB acv -system.cpu1.itb.fetch_accesses 521006 # ITB accesses +system.cpu1.dtb.write_accesses 108552 # DTB write accesses +system.cpu1.dtb.data_hits 3061172 # DTB hits +system.cpu1.dtb.data_misses 11559 # DTB misses +system.cpu1.dtb.data_acv 40 # DTB access violations +system.cpu1.dtb.data_accesses 394383 # DTB accesses +system.cpu1.itb.fetch_hits 516958 # ITB hits +system.cpu1.itb.fetch_misses 4674 # ITB misses +system.cpu1.itb.fetch_acv 66 # ITB acv +system.cpu1.itb.fetch_accesses 521632 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -968,255 +969,255 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14959639 # number of cpu cycles simulated +system.cpu1.numCycles 15151136 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6140426 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13703075 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3566695 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1009201 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7602996 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 256204 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 312 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 176452 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 62292 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1530550 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50498 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14135722 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.969393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.379564 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6180932 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13745317 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3578846 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1015574 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7699604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 257606 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 14 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 173727 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 62622 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1537985 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 51060 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14270827 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.963176 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.372632 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11742806 83.07% 83.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 150793 1.07% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 240174 1.70% 85.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 177797 1.26% 87.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 306821 2.17% 89.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 121463 0.86% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 138409 0.98% 91.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 186182 1.32% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1071277 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11867377 83.16% 83.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 153441 1.08% 84.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 242213 1.70% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 178756 1.25% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 307848 2.16% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 121777 0.85% 90.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 138851 0.97% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 186713 1.31% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1073851 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14135722 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.238421 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.916003 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5035823 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7049483 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1732735 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 195750 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 121930 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 104865 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6244 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11127162 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 19879 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 121930 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5174702 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 499846 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5538858 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1790125 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1010259 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10570144 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4276 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 68050 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 20115 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 516529 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6943229 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12595828 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12537363 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52773 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5938747 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1004482 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 436817 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 40607 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1800852 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1926573 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1243636 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 225182 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 130261 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9311043 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 502453 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9112092 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20417 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1494632 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 673391 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 369352 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14135722 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644615 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.367603 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14270827 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.236210 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.907214 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5071818 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7138589 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1741534 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 196274 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 122611 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 106199 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6268 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11163667 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 19967 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 122611 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5211151 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 520290 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5613443 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1798962 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1004368 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10604371 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4257 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 67823 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18974 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 511038 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6965041 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12634725 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12576141 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52884 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5956129 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1008912 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 437815 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 40748 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1803693 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1932664 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1246799 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 224198 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 128085 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9340268 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 503829 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9138713 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20420 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1499424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 677663 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 370337 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14270827 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.640377 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.363961 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10331729 73.09% 73.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1677616 11.87% 84.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 710014 5.02% 89.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 492260 3.48% 93.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 443396 3.14% 96.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 237464 1.68% 98.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 151784 1.07% 99.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 65612 0.46% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 25847 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10455091 73.26% 73.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1683189 11.79% 85.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 712225 4.99% 90.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 493511 3.46% 93.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 444759 3.12% 96.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 238311 1.67% 98.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 152079 1.07% 99.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 65820 0.46% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 25842 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14135722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14270827 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 23101 9.34% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 135152 54.66% 64.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 89008 36.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22910 9.24% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 135436 54.62% 63.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 89607 36.14% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5665609 62.18% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16110 0.18% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10836 0.12% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1960524 21.52% 84.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1194738 13.11% 97.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 258998 2.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5683316 62.19% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16216 0.18% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10845 0.12% 62.52% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.52% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.52% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.52% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1965659 21.51% 84.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1197875 13.11% 97.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 259525 2.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9112092 # Type of FU issued -system.cpu1.iq.rate 0.609112 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 247261 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027135 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32423377 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11214835 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8782259 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 204207 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 97217 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 94699 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9246642 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 109193 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94025 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9138713 # Type of FU issued +system.cpu1.iq.rate 0.603170 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247953 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027132 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 32611679 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11249940 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8808383 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 204947 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 97488 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 94992 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9273516 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 109632 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94173 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 261324 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4031 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 123982 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 262201 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 474 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4003 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 124065 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 65647 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.cacheBlocked 65383 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 121930 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 296920 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 166801 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10329862 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 27466 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1926573 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1243636 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 455903 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4091 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 161850 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4031 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28253 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 94223 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 122476 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8997942 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1896570 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 114150 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 122611 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 306675 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 177978 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10362316 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 27137 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1932664 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1246799 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 457137 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4115 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 173001 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4003 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 29001 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 94231 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 123232 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9024161 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1901420 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 114552 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 516366 # number of nop insts executed -system.cpu1.iew.exec_refs 3077114 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1335580 # Number of branches executed -system.cpu1.iew.exec_stores 1180544 # Number of stores executed -system.cpu1.iew.exec_rate 0.601481 # Inst execution rate -system.cpu1.iew.wb_sent 8905860 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8876958 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4235192 # num instructions producing a value -system.cpu1.iew.wb_consumers 6022422 # num instructions consuming a value +system.cpu1.iew.exec_nop 518219 # number of nop insts executed +system.cpu1.iew.exec_refs 3085060 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1341299 # Number of branches executed +system.cpu1.iew.exec_stores 1183640 # Number of stores executed +system.cpu1.iew.exec_rate 0.595610 # Inst execution rate +system.cpu1.iew.wb_sent 8932335 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8903375 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4245423 # num instructions producing a value +system.cpu1.iew.wb_consumers 6036438 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.593394 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.703237 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.587637 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.703299 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1521482 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 133101 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 111980 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13855601 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.631015 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.609308 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1526496 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 133492 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 112683 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13989586 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.626917 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.604217 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10693520 77.18% 77.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1462734 10.56% 87.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 528018 3.81% 91.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 318233 2.30% 93.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 242012 1.75% 95.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 100894 0.73% 96.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 90931 0.66% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 102553 0.74% 97.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 316706 2.29% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10816267 77.32% 77.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1467149 10.49% 87.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 531154 3.80% 91.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 320114 2.29% 93.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 241905 1.73% 95.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 101551 0.73% 96.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 91287 0.65% 97.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 103861 0.74% 97.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 316298 2.26% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13855601 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8743092 # Number of instructions committed -system.cpu1.commit.committedOps 8743092 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13989586 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8770307 # Number of instructions committed +system.cpu1.commit.committedOps 8770307 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2784903 # Number of memory references committed -system.cpu1.commit.loads 1665249 # Number of loads committed -system.cpu1.commit.membars 42287 # Number of memory barriers committed -system.cpu1.commit.branches 1247450 # Number of branches committed -system.cpu1.commit.fp_insts 93039 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8096711 # Number of committed integer instructions. -system.cpu1.commit.function_calls 139604 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 427747 4.89% 4.89% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5200103 59.48% 64.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 15945 0.18% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10829 0.12% 64.68% # Class of committed instruction +system.cpu1.commit.refs 2793197 # Number of memory references committed +system.cpu1.commit.loads 1670463 # Number of loads committed +system.cpu1.commit.membars 42427 # Number of memory barriers committed +system.cpu1.commit.branches 1252873 # Number of branches committed +system.cpu1.commit.fp_insts 93374 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8120952 # Number of committed integer instructions. +system.cpu1.commit.function_calls 139980 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 429153 4.89% 4.89% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5216835 59.48% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16050 0.18% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10839 0.12% 64.68% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction @@ -1242,290 +1243,292 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1707536 19.53% 84.23% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1120175 12.81% 97.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 258998 2.96% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1712890 19.53% 84.23% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1123256 12.81% 97.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 259525 2.96% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8743092 # Class of committed instruction -system.cpu1.commit.bw_lim_events 316706 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 23719092 # The number of ROB reads -system.cpu1.rob.rob_writes 20805392 # The number of ROB writes -system.cpu1.timesIdled 122607 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 823917 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3827854089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8318863 # Number of Instructions Simulated -system.cpu1.committedOps 8318863 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.798279 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.798279 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556087 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556087 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11586341 # number of integer regfile reads -system.cpu1.int_regfile_writes 6325577 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52057 # number of floating regfile reads -system.cpu1.fp_regfile_writes 51356 # number of floating regfile writes -system.cpu1.misc_regfile_reads 501983 # number of misc regfile reads -system.cpu1.misc_regfile_writes 207801 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 98586 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.617617 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2459541 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 98896 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.869975 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 61777830500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.617617 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950425 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.950425 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11508888 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11508888 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1514240 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1514240 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 887339 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 887339 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 31145 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 31145 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29838 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 29838 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2401579 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2401579 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2401579 # number of overall hits -system.cpu1.dcache.overall_hits::total 2401579 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 186104 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 186104 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 193582 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 193582 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4934 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4934 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2994 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2994 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 379686 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 379686 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 379686 # number of overall misses -system.cpu1.dcache.overall_misses::total 379686 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2502679500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2502679500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9084892318 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9084892318 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46731500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 46731500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48320000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 48320000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11587571818 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11587571818 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11587571818 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11587571818 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1700344 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1700344 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1080921 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1080921 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36079 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 36079 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32832 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32832 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2781265 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2781265 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2781265 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2781265 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109451 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.109451 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179090 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.179090 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136755 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136755 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091192 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091192 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136516 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.136516 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136516 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.136516 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13447.746959 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13447.746959 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46930.460053 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 46930.460053 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9471.321443 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9471.321443 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16138.944556 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16138.944556 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30518.828237 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 30518.828237 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 537858 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1114 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 16003 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.609823 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 123.777778 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 8770307 # Class of committed instruction +system.cpu1.commit.bw_lim_events 316298 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 23885701 # The number of ROB reads +system.cpu1.rob.rob_writes 20870962 # The number of ROB writes +system.cpu1.timesIdled 125875 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 880309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3829642661 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8344672 # Number of Instructions Simulated +system.cpu1.committedOps 8344672 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.815666 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.815666 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550762 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550762 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11618114 # number of integer regfile reads +system.cpu1.int_regfile_writes 6343189 # number of integer regfile writes +system.cpu1.fp_regfile_reads 52190 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51516 # number of floating regfile writes +system.cpu1.misc_regfile_reads 503472 # number of misc regfile reads +system.cpu1.misc_regfile_writes 210349 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 98962 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.970751 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2466427 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 99271 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.845393 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048837181500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.970751 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951115 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.951115 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 309 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.603516 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11541624 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11541624 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1517477 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1517477 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 889696 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 889696 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32286 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 32286 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29965 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 29965 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2407173 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2407173 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2407173 # number of overall hits +system.cpu1.dcache.overall_hits::total 2407173 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 186675 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 186675 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 194181 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 194181 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4996 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4996 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2988 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2988 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 380856 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 380856 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 380856 # number of overall misses +system.cpu1.dcache.overall_misses::total 380856 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2524860000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2524860000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9140210329 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9140210329 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 47601500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 47601500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47681500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 47681500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11665070329 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11665070329 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11665070329 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11665070329 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1704152 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1704152 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1083877 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1083877 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 37282 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 37282 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32953 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 32953 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2788029 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2788029 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2788029 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2788029 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109541 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.109541 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179154 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.179154 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134006 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134006 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090675 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090675 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136604 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.136604 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136604 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.136604 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13525.431900 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13525.431900 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47070.569876 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 47070.569876 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9527.922338 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9527.922338 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15957.663989 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15957.663989 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30628.558639 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30628.558639 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30628.558639 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 30628.558639 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 543818 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1735 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 16052 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.878520 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 173.500000 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 63787 # number of writebacks -system.cpu1.dcache.writebacks::total 63787 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 112960 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 112960 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 158580 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 158580 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 454 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 454 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 271540 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 271540 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 271540 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 271540 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73144 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 73144 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35002 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 35002 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4480 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4480 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2993 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2993 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 108146 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 108146 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 108146 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 108146 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 64059 # number of writebacks +system.cpu1.dcache.writebacks::total 64059 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 113306 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 113306 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 159042 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 159042 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 272348 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 272348 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 272348 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 272348 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73369 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 73369 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35139 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 35139 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4523 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4523 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2988 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2988 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 108508 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 108508 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 108508 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 108508 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2930 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3080 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 925590000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 925590000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553309551 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1553309551 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37834000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37834000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45327000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45327000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2478899551 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2478899551 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2478899551 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2478899551 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 28469500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 28469500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 648479500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 648479500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676949000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676949000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043017 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043017 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032382 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032382 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124172 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124172 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091161 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091161 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.038884 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.038884 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12654.353057 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12654.353057 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44377.737015 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44377.737015 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8445.089286 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8445.089286 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15144.336786 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15144.336786 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189796.666667 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189796.666667 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221324.061433 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 221324.061433 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 219788.636364 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 219788.636364 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2931 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2931 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3081 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3081 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 931066500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 931066500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1566203053 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1566203053 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38495000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38495000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2497269553 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2497269553 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2497269553 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2497269553 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30161500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30161500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 685230000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 685230000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 715391500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 715391500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043053 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043053 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032420 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032420 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121319 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121319 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090675 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090675 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038919 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038919 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038919 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038919 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12690.189317 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12690.189317 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44571.645551 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44571.645551 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8510.944064 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8510.944064 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14957.663989 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14957.663989 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23014.612314 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23014.612314 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23014.612314 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23014.612314 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201076.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201076.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 233787.103378 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 233787.103378 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 232194.579682 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 232194.579682 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 222828 # number of replacements -system.cpu1.icache.tags.tagsinuse 467.348174 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1300089 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 223338 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.821172 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1895764140500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.348174 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912789 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.912789 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 223833 # number of replacements +system.cpu1.icache.tags.tagsinuse 467.351638 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1306354 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 224343 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.823021 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1896743746500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.351638 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912796 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.912796 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1753949 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1753949 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1300089 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1300089 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1300089 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1300089 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1300089 # number of overall hits -system.cpu1.icache.overall_hits::total 1300089 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 230461 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 230461 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 230461 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 230461 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 230461 # number of overall misses -system.cpu1.icache.overall_misses::total 230461 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3280299500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3280299500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3280299500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3280299500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3280299500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3280299500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1530550 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1530550 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1530550 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1530550 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1530550 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1530550 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150574 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.150574 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150574 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.150574 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150574 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.150574 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.642569 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14233.642569 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14233.642569 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14233.642569 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 780 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 1762389 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1762389 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1306354 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1306354 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1306354 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1306354 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1306354 # number of overall hits +system.cpu1.icache.overall_hits::total 1306354 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 231631 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 231631 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 231631 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 231631 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 231631 # number of overall misses +system.cpu1.icache.overall_misses::total 231631 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3331435000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3331435000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3331435000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3331435000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3331435000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3331435000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1537985 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1537985 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1537985 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1537985 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1537985 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1537985 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150607 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.150607 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150607 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.150607 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150607 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.150607 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14382.509250 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14382.509250 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14382.509250 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14382.509250 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14382.509250 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14382.509250 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 764 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.571429 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.105263 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7062 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7062 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7062 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7062 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7062 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7062 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223399 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 223399 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 223399 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 223399 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 223399 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 223399 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2948315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2948315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2948315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2948315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2948315500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2948315500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145960 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.145960 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.145960 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13197.532218 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 223833 # number of writebacks +system.cpu1.icache.writebacks::total 223833 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7227 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7227 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7227 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7227 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7227 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7227 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 224404 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 224404 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 224404 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 224404 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 224404 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 224404 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2997413500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2997413500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2997413500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2997413500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2997413500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2997413500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145908 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.145908 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.145908 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.219568 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.219568 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.219568 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1541,9 +1544,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7371 # Transaction distribution system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 54607 # Transaction distribution -system.iobus.trans_dist::WriteResp 54607 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11900 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54609 # Transaction distribution +system.iobus.trans_dist::WriteResp 54609 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1555,11 +1558,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40504 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1571,49 +1574,49 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73826 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11255000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735474 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12353500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 448000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14420500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5954500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 217500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 87000 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 131500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215099741 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215061495 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27445000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27447000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.507802 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.507724 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1725999022000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.507802 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031738 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031738 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1726981783000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.507724 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031733 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031733 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1627,14 +1630,14 @@ system.iocache.demand_misses::tsunami.ide 176 # n system.iocache.demand_misses::total 176 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 176 # number of overall misses system.iocache.overall_misses::total 176 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22249883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22249883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427997858 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427997858 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22249883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22249883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22249883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22249883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22155383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22155383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5431231112 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5431231112 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22155383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22155383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22155383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22155383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1651,19 +1654,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126419.789773 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126419.789773 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.446332 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130631.446332 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126419.789773 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126419.789773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125882.857955 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125882.857955 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130709.258568 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130709.258568 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125882.857955 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125882.857955 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125882.857955 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125882.857955 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.411765 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1677,14 +1680,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 176 system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13449883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13449883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350397858 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350397858 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13449883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13449883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13449883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13449883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13355383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13355383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353631112 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3353631112 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13355383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13355383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13355383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13355383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1693,195 +1696,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76419.789773 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.446332 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.446332 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75882.857955 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80709.258568 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80709.258568 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 344948 # number of replacements -system.l2c.tags.tagsinuse 65190.787367 # Cycle average of tags in use -system.l2c.tags.total_refs 3990905 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410112 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.731256 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 11174884000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53006.163408 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5332.464187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6575.010887 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 209.732945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 67.415939 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.808810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081367 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.100327 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy +system.l2c.tags.replacements 345304 # number of replacements +system.l2c.tags.tagsinuse 65190.216948 # Cycle average of tags in use +system.l2c.tags.total_refs 3990482 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410468 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.721786 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11177481000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53120.456427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5260.305215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6531.960123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 208.754945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 68.740237 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.810554 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080266 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.099670 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001049 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994724 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1750 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6246 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5661 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51290 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1730 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6285 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6556 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 50377 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38374495 # Number of tag accesses -system.l2c.tags.data_accesses 38374495 # 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number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 736901 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 66152 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 803053 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 896343 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 892342 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 221742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 88887 # number of demand (read+write) hits -system.l2c.demand_hits::total 2099314 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 896343 # number of overall hits -system.l2c.overall_hits::cpu0.data 892342 # number of overall hits -system.l2c.overall_hits::cpu1.inst 221742 # number of overall hits -system.l2c.overall_hits::cpu1.data 88887 # number of overall hits -system.l2c.overall_hits::total 2099314 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2756 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1092 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3848 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 412 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 449 # number of SCUpgradeReq misses +system.l2c.tags.tag_accesses 38372212 # Number of tag accesses +system.l2c.tags.data_accesses 38372212 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 820126 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 820126 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 859282 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 859282 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 249 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 421 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 25 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 155330 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 22838 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 178168 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 895446 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 222750 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1118196 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 736882 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 66420 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 803302 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 895446 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 892212 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 222750 # 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number of demand (read+write) misses +system.l2c.demand_misses::total 411229 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13592 # number of overall misses +system.l2c.overall_misses::cpu0.data 387850 # number of overall misses system.l2c.overall_misses::cpu1.inst 1628 # number of overall misses -system.l2c.overall_misses::cpu1.data 8146 # number of overall misses -system.l2c.overall_misses::total 411192 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 3749500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 17004000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 20753500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2598000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 405500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3003500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 15999286000 # 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miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.810089 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.898016 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.893709 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945263 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.919872 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.424719 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.243604 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.406588 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015013 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007288 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013491 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.270321 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 201578500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1201944500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 49149701500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1475287500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28274500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1503562000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2182363000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 649671500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2832034500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3657650500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 677946000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4335596500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938372 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.810089 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.898016 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.893709 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.945263 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.919872 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.424719 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.243604 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.406588 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013474 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270321 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012303 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254274 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71779.934688 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71691.391941 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71754.807692 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71285.194175 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71790.645880 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71548.780488 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129416.394357 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 148234.089047 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 130545.015195 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124263.473250 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114195.362953 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130834.344660 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114245.434061 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197936.692690 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177296.666667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197506.393329 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203210.666667 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209194.197952 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204553.581003 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201046.709377 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 207640.746753 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202049.654321 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941457 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.902229 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.891720 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.946352 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.918890 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425138 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.242973 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.406842 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013412 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270311 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012327 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254204 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.302993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.083753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163770 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.302993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.083753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163770 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71726.319595 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71754.691689 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129638.451695 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.998036 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123814.255641 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114198.936903 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114249.542558 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118771.835761 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119524.577467 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118771.835761 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119524.577467 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209409.155429 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208973.175817 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213013.249083 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214082.386925 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 296388 # Transaction distribution -system.membus.trans_dist::WriteReq 13055 # Transaction distribution -system.membus.trans_dist::WriteResp 13055 # Transaction distribution -system.membus.trans_dist::Writeback 123049 # Transaction distribution -system.membus.trans_dist::CleanEvict 262884 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10279 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5759 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5112 # Transaction distribution -system.membus.trans_dist::ReadExReq 122086 # Transaction distribution -system.membus.trans_dist::ReadExResp 121678 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289268 # Transaction distribution -system.membus.trans_dist::BadAddressError 75 # Transaction distribution +system.membus.trans_dist::ReadResp 296301 # Transaction distribution +system.membus.trans_dist::WriteReq 13057 # Transaction distribution +system.membus.trans_dist::WriteResp 13057 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123171 # Transaction distribution +system.membus.trans_dist::CleanEvict 262771 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10335 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5768 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5173 # Transaction distribution +system.membus.trans_dist::ReadExReq 122191 # Transaction distribution +system.membus.trans_dist::ReadExResp 121777 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289182 # Transaction distribution +system.membus.trans_dist::BadAddressError 76 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1227712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40504 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187227 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1227883 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1352540 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73826 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31484224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31558050 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1352711 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73842 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31492800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31566642 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34216290 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 11781 # Total snoops (count) -system.membus.snoop_fanout::samples 875308 # Request fanout histogram +system.membus.pkt_size::total 34224882 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11791 # Total snoops (count) +system.membus.snoop_fanout::samples 875399 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 875308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875399 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 875308 # Request fanout histogram -system.membus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875399 # Request fanout histogram +system.membus.reqLayer0.occupancy 36670000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1356119148 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1357207403 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 92500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 98500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2187698407 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2187694355 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69909650 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69834733 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 5063061 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2531463 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 338644 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1334 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1266 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5063738 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2531809 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 339719 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1340 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2238892 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13055 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13055 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 943078 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1635745 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10313 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5834 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16147 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301580 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301580 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1133694 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1098094 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2239104 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13057 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13057 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 943311 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 859282 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 775827 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10329 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5844 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16173 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301707 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301707 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1133724 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1098277 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 76 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2554026 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3861302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 573119 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 309440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7297887 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58240320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130381048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 14295680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10315306 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213232354 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 462162 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5511701 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.123436 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.329209 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2546826 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3860959 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 579596 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 310532 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7297913 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 104800384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130368640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22732288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10357298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 268258610 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462469 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2998699 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.119628 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.324813 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4831850 87.67% 87.67% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 679365 12.33% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 482 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2640250 88.05% 88.05% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 358173 11.94% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 274 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5511701 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3368234918 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2998699 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4501023919 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1366825726 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1365634171 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1954242307 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1954807358 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 335428339 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 338746615 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 167784154 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 168528157 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2172,32 +2180,32 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6535 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184475 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65083 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.20% 41.79% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 184433 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65060 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1928 1.20% 41.78% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93355 58.10% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 160682 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64077 49.21% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 93335 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 160640 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64056 49.21% 49.21% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.48% 50.79% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.48% 50.79% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63891 49.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130212 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864797723000 97.04% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61900500 0.00% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 553477500 0.03% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 85562000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56264153500 2.93% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1921762816500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984543 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 63870 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130171 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865607975500 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63996500 0.00% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577908500 0.03% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 88293000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56422873000 2.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1922761046500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684388 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810371 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684309 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810327 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed @@ -2233,56 +2241,56 @@ system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3533 2.09% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3530 2.09% 2.26% # number of callpals executed system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 153850 90.93% 93.22% # number of callpals executed -system.cpu0.kern.callpal::rdps 6345 3.75% 96.97% # number of callpals executed +system.cpu0.kern.callpal::swpipl 153808 90.93% 93.22% # number of callpals executed +system.cpu0.kern.callpal::rdps 6346 3.75% 96.97% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rti 4587 2.71% 99.69% # number of callpals executed +system.cpu0.kern.callpal::rti 4586 2.71% 99.69% # number of callpals executed system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169199 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7137 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1347 # number of protection mode switches +system.cpu0.kern.callpal::total 169154 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7135 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1348 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1346 -system.cpu0.kern.mode_good::user 1347 +system.cpu0.kern.mode_good::kernel 1347 +system.cpu0.kern.mode_good::user 1348 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.188595 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188788 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.317421 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1919561135500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2201673000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.317694 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1920558467500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2202571000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3534 # number of times the context was actually changed +system.cpu0.kern.swap_context 3531 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 55164 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17245 36.53% 36.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 4.08% 40.61% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 55289 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 17293 36.54% 36.54% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 4.07% 40.61% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27750 58.79% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 47204 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16874 47.30% 47.30% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.40% 52.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.80% 53.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16590 46.51% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35673 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874997277000 97.58% 97.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 538569500 0.03% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 135298500 0.01% 97.62% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45735704500 2.38% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1921406849500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978487 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_count::31 27821 58.79% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 47324 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16920 47.31% 47.31% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 5.39% 52.69% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 284 0.79% 53.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16636 46.51% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 35766 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1875921374000 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 562894500 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 139598000 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45773010000 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1922396876500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978431 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.597838 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.755720 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.597966 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.755769 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed @@ -2301,32 +2309,32 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1056 2.16% 2.55% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1060 2.16% 2.55% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 42024 86.04% 88.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2414 4.94% 93.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.56% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rti 2970 6.08% 99.65% # number of callpals executed +system.cpu1.kern.callpal::swpipl 42140 86.06% 88.63% # number of callpals executed +system.cpu1.kern.callpal::rdps 2415 4.93% 93.56% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.58% # number of callpals executed +system.cpu1.kern.callpal::rti 2973 6.07% 99.65% # number of callpals executed system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48843 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1253 # number of protection mode switches -system.cpu1.kern.mode_switch::user 392 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2414 # number of protection mode switches +system.cpu1.kern.callpal::total 48967 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1257 # number of protection mode switches +system.cpu1.kern.mode_switch::user 391 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2415 # number of protection mode switches system.cpu1.kern.mode_good::kernel 600 -system.cpu1.kern.mode_good::user 392 -system.cpu1.kern.mode_good::idle 208 -system.cpu1.kern.mode_switch_good::kernel 0.478851 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::user 391 +system.cpu1.kern.mode_good::idle 209 +system.cpu1.kern.mode_switch_good::kernel 0.477327 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086164 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.295639 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4354098000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 702561000 0.04% 0.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1916032066000 99.74% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1057 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.086542 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.295348 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4412319000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 702202000 0.04% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1916962357500 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1061 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 3a598fe00..30a63d50f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.875745 # Number of seconds simulated -sim_ticks 1875745192000 # Number of ticks simulated -final_tick 1875745192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.875760 # Number of seconds simulated +sim_ticks 1875760362000 # Number of ticks simulated +final_tick 1875760362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131976 # Simulator instruction rate (inst/s) -host_op_rate 131976 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4672432142 # Simulator tick rate (ticks/s) -host_mem_usage 378172 # Number of bytes of host memory used -host_seconds 401.45 # Real time elapsed on the host -sim_insts 52981683 # Number of instructions simulated -sim_ops 52981683 # Number of ops (including micro ops) simulated +host_inst_rate 133605 # Simulator instruction rate (inst/s) +host_op_rate 133605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4730094094 # Simulator tick rate (ticks/s) +host_mem_usage 378388 # Number of bytes of host memory used +host_seconds 396.56 # Real time elapsed on the host +sim_insts 52982087 # Number of instructions simulated +sim_ops 52982087 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 962112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881088 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25844608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 962112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7523648 # Number of bytes written to this memory -system.physmem.bytes_written::total 7523648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15033 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388774 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25840256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7524736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388767 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403822 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117557 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117557 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 512923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13264881 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403754 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117574 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117574 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 510837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13264534 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13778315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4011018 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4011018 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4011018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13264881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13775883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 510837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 510837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4011566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4011566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4011566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 510837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13264534 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17789333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403822 # Number of read requests accepted -system.physmem.writeReqs 117557 # Number of write requests accepted -system.physmem.readBursts 403822 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117557 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25836864 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue -system.physmem.bytesWritten 7522176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25844608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7523648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17787449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403754 # Number of read requests accepted +system.physmem.writeReqs 117574 # Number of write requests accepted +system.physmem.readBursts 403754 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117574 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25832192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25840256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7524736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25633 # Per bank write bursts -system.physmem.perBankRdBursts::1 25421 # Per bank write bursts -system.physmem.perBankRdBursts::2 25565 # Per bank write bursts -system.physmem.perBankRdBursts::3 25492 # Per bank write bursts -system.physmem.perBankRdBursts::4 25387 # Per bank write bursts -system.physmem.perBankRdBursts::5 24737 # Per bank write bursts -system.physmem.perBankRdBursts::6 24937 # Per bank write bursts -system.physmem.perBankRdBursts::7 25080 # Per bank write bursts -system.physmem.perBankRdBursts::8 24933 # Per bank write bursts -system.physmem.perBankRdBursts::9 25019 # Per bank write bursts -system.physmem.perBankRdBursts::10 25561 # Per bank write bursts -system.physmem.perBankRdBursts::11 24878 # Per bank write bursts -system.physmem.perBankRdBursts::12 24487 # Per bank write bursts -system.physmem.perBankRdBursts::13 25242 # Per bank write bursts -system.physmem.perBankRdBursts::14 25745 # Per bank write bursts -system.physmem.perBankRdBursts::15 25584 # Per bank write bursts -system.physmem.perBankWrBursts::0 7946 # Per bank write bursts -system.physmem.perBankWrBursts::1 7515 # Per bank write bursts -system.physmem.perBankWrBursts::2 7960 # Per bank write bursts -system.physmem.perBankWrBursts::3 7517 # Per bank write bursts -system.physmem.perBankWrBursts::4 7330 # Per bank write bursts -system.physmem.perBankWrBursts::5 6676 # Per bank write bursts -system.physmem.perBankWrBursts::6 6762 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 303613 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25610 # Per bank write bursts +system.physmem.perBankRdBursts::1 25424 # Per bank write bursts +system.physmem.perBankRdBursts::2 25555 # Per bank write bursts +system.physmem.perBankRdBursts::3 25501 # Per bank write bursts +system.physmem.perBankRdBursts::4 25379 # Per bank write bursts +system.physmem.perBankRdBursts::5 24724 # Per bank write bursts +system.physmem.perBankRdBursts::6 24941 # Per bank write bursts +system.physmem.perBankRdBursts::7 25082 # Per bank write bursts +system.physmem.perBankRdBursts::8 24938 # Per bank write bursts +system.physmem.perBankRdBursts::9 25020 # Per bank write bursts +system.physmem.perBankRdBursts::10 25562 # Per bank write bursts +system.physmem.perBankRdBursts::11 24881 # Per bank write bursts +system.physmem.perBankRdBursts::12 24459 # Per bank write bursts +system.physmem.perBankRdBursts::13 25275 # Per bank write bursts +system.physmem.perBankRdBursts::14 25708 # Per bank write bursts +system.physmem.perBankRdBursts::15 25569 # Per bank write bursts +system.physmem.perBankWrBursts::0 7930 # Per bank write bursts +system.physmem.perBankWrBursts::1 7523 # Per bank write bursts +system.physmem.perBankWrBursts::2 7959 # Per bank write bursts +system.physmem.perBankWrBursts::3 7525 # Per bank write bursts +system.physmem.perBankWrBursts::4 7322 # Per bank write bursts +system.physmem.perBankWrBursts::5 6662 # Per bank write bursts +system.physmem.perBankWrBursts::6 6770 # Per bank write bursts system.physmem.perBankWrBursts::7 6719 # Per bank write bursts -system.physmem.perBankWrBursts::8 7146 # Per bank write bursts -system.physmem.perBankWrBursts::9 6702 # Per bank write bursts -system.physmem.perBankWrBursts::10 7407 # Per bank write bursts -system.physmem.perBankWrBursts::11 6970 # Per bank write bursts -system.physmem.perBankWrBursts::12 7148 # Per bank write bursts -system.physmem.perBankWrBursts::13 7861 # Per bank write bursts -system.physmem.perBankWrBursts::14 8061 # Per bank write bursts -system.physmem.perBankWrBursts::15 7814 # Per bank write bursts +system.physmem.perBankWrBursts::8 7147 # Per bank write bursts +system.physmem.perBankWrBursts::9 6703 # Per bank write bursts +system.physmem.perBankWrBursts::10 7409 # Per bank write bursts +system.physmem.perBankWrBursts::11 6974 # Per bank write bursts +system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::13 7893 # Per bank write bursts +system.physmem.perBankWrBursts::14 8063 # Per bank write bursts +system.physmem.perBankWrBursts::15 7807 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1875739913500 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 1875755162500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403822 # Read request sizes (log2) +system.physmem.readPktSize::6 403754 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117557 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117574 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 35937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -148,123 +148,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.822002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.292900 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 411.615573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13686 22.02% 22.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10474 16.86% 38.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4974 8.00% 46.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2759 4.44% 51.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2428 3.91% 55.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1656 2.66% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3743 6.02% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1149 1.85% 65.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21272 34.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62141 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.350259 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2906.647984 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5216 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5219 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5219 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.520406 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.103659 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.296995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4441 85.09% 85.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 172 3.30% 88.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 18 0.34% 88.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 180 3.45% 92.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.08% 92.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.40% 92.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.69% 93.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.04% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.23% 93.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 25 0.48% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.08% 94.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 11 0.21% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.08% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.38% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 29 0.56% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 29 0.56% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 164 3.14% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.06% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.11% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.08% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 11 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5219 # Writes before turning the bus around for reads -system.physmem.totQLat 4201414500 # Total ticks spent queuing -system.physmem.totMemAccLat 11770808250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018505000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10407.24 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.237934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 330.496904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 411.905259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13738 22.09% 22.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10541 16.95% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4957 7.97% 47.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2730 4.39% 51.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2467 3.97% 55.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1593 2.56% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3726 5.99% 63.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1160 1.86% 65.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21290 34.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62202 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5203 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.574092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2240.859567 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5198 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5203 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5203 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.592927 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.087485 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.896632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4449 85.51% 85.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 153 2.94% 88.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.29% 88.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 183 3.52% 92.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7 0.13% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.40% 92.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 39 0.75% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.02% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.19% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.33% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.12% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.15% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 19 0.37% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.52% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 31 0.60% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.06% 95.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 162 3.11% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.13% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.08% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.08% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.08% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 10 0.19% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5203 # Writes before turning the bus around for reads +system.physmem.totQLat 4177241750 # Total ticks spent queuing +system.physmem.totMemAccLat 11745266750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10349.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29157.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29099.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s @@ -273,72 +276,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing -system.physmem.readRowHits 363834 # Number of row buffer hits during reads -system.physmem.writeRowHits 95259 # Number of row buffer hits during writes +system.physmem.avgRdQLen 2.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing +system.physmem.readRowHits 363742 # Number of row buffer hits during reads +system.physmem.writeRowHits 95234 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.03 # Row buffer hit rate for writes -system.physmem.avgGap 3597651.45 # Average gap between requests -system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233286480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127289250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577565600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378594000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61659983700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1071355704750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1257846562020 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.587193 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1782093997750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62635040000 # Time in different power states +system.physmem.writeRowHitRate 81.00 # Row buffer hit rate for writes +system.physmem.avgGap 3598032.64 # Average gap between requests +system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232553160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126889125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577284800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378496800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61473435525 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1071528687000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1257832501770 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.574130 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1782381530500 # Time in different power states +system.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31009992250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30737512000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 236499480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129042375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571255400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383026320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61488464715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1071506168250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1257828594780 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.577609 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1782344410500 # Time in different power states -system.physmem_1.memoryStateTime::REF 62635040000 # Time in different power states +system.physmem_1.actEnergy 237693960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129694125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1570966800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383233680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61441070355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1071557085750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1257834900030 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.575404 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1782427454500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30760024500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30691601750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17977610 # Number of BP lookups -system.cpu.branchPred.condPredicted 15676073 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370677 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11479744 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5859077 # Number of BTB hits +system.cpu.branchPred.lookups 17943789 # Number of BP lookups +system.cpu.branchPred.condPredicted 15652252 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 367731 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11526734 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5853564 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 51.038394 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 912903 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21206 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.782503 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 912127 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21143 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10250294 # DTB read hits -system.cpu.dtb.read_misses 41452 # DTB read misses -system.cpu.dtb.read_acv 531 # DTB read access violations -system.cpu.dtb.read_accesses 965916 # DTB read accesses -system.cpu.dtb.write_hits 6642949 # DTB write hits -system.cpu.dtb.write_misses 9723 # DTB write misses -system.cpu.dtb.write_acv 398 # DTB write access violations -system.cpu.dtb.write_accesses 342082 # DTB write accesses -system.cpu.dtb.data_hits 16893243 # DTB hits -system.cpu.dtb.data_misses 51175 # DTB misses -system.cpu.dtb.data_acv 929 # DTB access violations -system.cpu.dtb.data_accesses 1307998 # DTB accesses -system.cpu.itb.fetch_hits 1771116 # ITB hits -system.cpu.itb.fetch_misses 27251 # ITB misses -system.cpu.itb.fetch_acv 655 # ITB acv -system.cpu.itb.fetch_accesses 1798367 # ITB accesses +system.cpu.dtb.read_hits 10250861 # DTB read hits +system.cpu.dtb.read_misses 41155 # DTB read misses +system.cpu.dtb.read_acv 533 # DTB read access violations +system.cpu.dtb.read_accesses 965519 # DTB read accesses +system.cpu.dtb.write_hits 6643163 # DTB write hits +system.cpu.dtb.write_misses 9679 # DTB write misses +system.cpu.dtb.write_acv 405 # DTB write access violations +system.cpu.dtb.write_accesses 341919 # DTB write accesses +system.cpu.dtb.data_hits 16894024 # DTB hits +system.cpu.dtb.data_misses 50834 # DTB misses +system.cpu.dtb.data_acv 938 # DTB access violations +system.cpu.dtb.data_accesses 1307438 # DTB accesses +system.cpu.itb.fetch_hits 1771509 # ITB hits +system.cpu.itb.fetch_misses 27218 # ITB misses +system.cpu.itb.fetch_acv 651 # ITB acv +system.cpu.itb.fetch_accesses 1798727 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,136 +354,136 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 153807945 # number of cpu cycles simulated +system.cpu.numCycles 154312476 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29589963 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78082078 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17977610 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6771980 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115315004 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1233982 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 2306 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1247451 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 470617 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 460 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8997640 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271780 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 147272342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.530188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.786973 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29589684 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78040473 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17943789 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6765691 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115537778 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1228012 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1868 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28793 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1263154 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 470523 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8990852 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 270749 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 147506364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.529065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.785295 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132738967 90.13% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 930397 0.63% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1956016 1.33% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 907001 0.62% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2772714 1.88% 94.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 615474 0.42% 95.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 727209 0.49% 95.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009346 0.69% 96.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5615218 3.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132982346 90.15% 90.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 927735 0.63% 90.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1956667 1.33% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 905254 0.61% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772061 1.88% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 613974 0.42% 95.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 725766 0.49% 95.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009556 0.68% 96.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5613005 3.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 147272342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116883 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.507660 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24002291 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 111345789 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9440793 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1908530 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 574938 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 581140 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42414 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68062016 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 132549 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 574938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24926396 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78168566 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21593766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10339140 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11669534 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65637228 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204564 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2092706 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 229144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7400964 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43743792 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79597549 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79416724 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168373 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38181235 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5562549 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1689699 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239435 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13568621 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10378795 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6951631 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1513940 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1098335 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58473138 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2139162 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57493462 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7630612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3411321 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1477941 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 147272342 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.390389 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.114131 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 147506364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116282 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.505730 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23997501 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 111590886 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9436404 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1909016 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 572556 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 581578 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 41802 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68051611 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 132447 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 572556 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24921357 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78408678 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21682628 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10334897 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11586246 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65629261 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204540 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2094496 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 230878 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7314004 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43742271 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79592757 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79412100 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168205 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38181578 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5560685 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1689598 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239417 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13566674 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10375081 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6952014 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1510108 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1095838 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58467931 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2138048 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57495227 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57340 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7623887 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3407756 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476848 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147506364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.389781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.113625 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 123663895 83.97% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10186331 6.92% 90.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4292878 2.91% 93.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3019293 2.05% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3081041 2.09% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1488323 1.01% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1011420 0.69% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 404091 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125070 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 123908569 84.00% 84.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10178941 6.90% 90.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4283785 2.90% 93.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3020720 2.05% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3080791 2.09% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1492273 1.01% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011784 0.69% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404685 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124816 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 147272342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147506364 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210189 18.68% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 539111 47.92% 66.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375615 33.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210138 18.65% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 541379 48.04% 66.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375311 33.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39049173 67.92% 67.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61879 0.11% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7282 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39050505 67.92% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61871 0.11% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued @@ -508,97 +511,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10660314 18.54% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6723536 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949085 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10660993 18.54% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6723341 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949046 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57493462 # Type of FU issued -system.cpu.iq.rate 0.373800 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1124915 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019566 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262728196 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67925320 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55850502 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 713041 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336604 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329051 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58228243 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382848 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 635438 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57495227 # Type of FU issued +system.cpu.iq.rate 0.372590 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1126828 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019599 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262968198 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67912529 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55849103 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712787 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336322 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328951 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58232052 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382721 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 635480 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1285740 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3115 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19427 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 573353 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1282102 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3336 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 573763 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18203 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 457581 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 460620 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 574938 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74485816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1122121 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64302959 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 140159 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10378795 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6951631 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1891041 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 44126 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 874685 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19427 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 179710 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409314 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 589024 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56907888 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10319427 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 585573 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 572556 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 74664170 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1189821 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64295080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139940 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10375081 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6952014 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1890560 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 943025 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 177030 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409389 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 586419 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56909008 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10319700 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586218 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3690659 # number of nop insts executed -system.cpu.iew.exec_refs 16987198 # number of memory reference insts executed -system.cpu.iew.exec_branches 8973802 # Number of branches executed -system.cpu.iew.exec_stores 6667771 # Number of stores executed -system.cpu.iew.exec_rate 0.369993 # Inst execution rate -system.cpu.iew.wb_sent 56315493 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56179553 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28757989 # num instructions producing a value -system.cpu.iew.wb_consumers 39945326 # num instructions consuming a value +system.cpu.iew.exec_nop 3689101 # number of nop insts executed +system.cpu.iew.exec_refs 16987647 # number of memory reference insts executed +system.cpu.iew.exec_branches 8974026 # Number of branches executed +system.cpu.iew.exec_stores 6667947 # Number of stores executed +system.cpu.iew.exec_rate 0.368791 # Inst execution rate +system.cpu.iew.wb_sent 56315336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56178054 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28756989 # num instructions producing a value +system.cpu.iew.wb_consumers 39942344 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.365258 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719934 # average fanout of values written-back +system.cpu.iew.wb_rate 0.364054 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719962 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8014233 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661221 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 539644 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 145865842 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.385097 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.287358 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8005033 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661200 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537292 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146103821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.384473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.286210 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 126089885 86.44% 86.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7851403 5.38% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4272179 2.93% 94.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2235192 1.53% 96.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1747101 1.20% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615790 0.42% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475839 0.33% 98.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 478833 0.33% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2099620 1.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 126321778 86.46% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7855301 5.38% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4275066 2.93% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2236699 1.53% 96.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1745226 1.19% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615725 0.42% 97.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 478401 0.33% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 477554 0.33% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2098071 1.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 145865842 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56172516 # Number of instructions committed -system.cpu.commit.committedOps 56172516 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146103821 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56172911 # Number of instructions committed +system.cpu.commit.committedOps 56172911 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471333 # Number of memory references committed -system.cpu.commit.loads 9093055 # Number of loads committed -system.cpu.commit.membars 226352 # Number of memory barriers committed -system.cpu.commit.branches 8440752 # Number of branches committed +system.cpu.commit.refs 15471230 # Number of memory references committed +system.cpu.commit.loads 9092979 # Number of loads committed +system.cpu.commit.membars 226353 # Number of memory barriers committed +system.cpu.commit.branches 8440862 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52021823 # Number of committed integer instructions. -system.cpu.commit.function_calls 740586 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198106 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36219281 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60683 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52022252 # Number of committed integer instructions. +system.cpu.commit.function_calls 740590 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198097 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36219833 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -626,36 +629,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319407 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384233 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949085 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9319332 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6384206 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949045 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56172516 # Class of committed instruction -system.cpu.commit.bw_lim_events 2099620 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 207703277 # The number of ROB reads -system.cpu.rob.rob_writes 129775597 # The number of ROB writes -system.cpu.timesIdled 576321 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6535603 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3597682440 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52981683 # Number of Instructions Simulated -system.cpu.committedOps 52981683 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.903040 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.903040 # CPI: Total CPI of All Threads -system.cpu.ipc 0.344466 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.344466 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74566924 # number of integer regfile reads -system.cpu.int_regfile_writes 40527176 # number of integer regfile writes -system.cpu.fp_regfile_reads 167101 # number of floating regfile reads -system.cpu.fp_regfile_writes 167535 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985778 # number of misc regfile reads -system.cpu.misc_regfile_writes 939467 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1402095 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.992786 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11832212 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1402607 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.435871 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.992786 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56172911 # Class of committed instruction +system.cpu.commit.bw_lim_events 2098071 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 207934044 # The number of ROB reads +system.cpu.rob.rob_writes 129754094 # The number of ROB writes +system.cpu.timesIdled 581359 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6806112 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3597208249 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52982087 # Number of Instructions Simulated +system.cpu.committedOps 52982087 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.912541 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.912541 # CPI: Total CPI of All Threads +system.cpu.ipc 0.343343 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.343343 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74569026 # number of integer regfile reads +system.cpu.int_regfile_writes 40527111 # number of integer regfile writes +system.cpu.fp_regfile_reads 166982 # number of floating regfile reads +system.cpu.fp_regfile_writes 167538 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985520 # number of misc regfile reads +system.cpu.misc_regfile_writes 939432 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1401817 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11831384 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1402329 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.436953 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -663,380 +666,386 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63847952 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63847952 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7239475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7239475 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4190405 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4190405 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186164 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186164 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215760 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215760 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15186082 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15186082 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15186082 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15186082 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.199020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318391 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318391 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111364 # 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average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19142.370339 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19142.370339 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 32692.307692 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 32692.307692 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46367.601779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46367.601779 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7156530 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5457 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133923 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437647 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 188.172414 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 63839342 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63839342 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7238802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7238802 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4190242 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4190242 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186215 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186215 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215725 # 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number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3754990 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3754990 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3754990 # number of overall misses +system.cpu.dcache.overall_misses::total 3754990 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57215692000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57215692000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116805325608 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116805325608 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447608000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 447608000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 892500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 892500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 174021017608 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 174021017608 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 174021017608 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 174021017608 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9036240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9036240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147794 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147794 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209465 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209465 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15184034 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15184034 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15184034 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15184034 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198914 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198914 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318415 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318415 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110997 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.110997 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247299 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247299 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247299 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247299 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.802822 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.802822 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59669.079344 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59669.079344 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46343.936364 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46343.936364 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7142845 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5288 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 134029 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.293280 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 188.857143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841276 # number of writebacks -system.cpu.dcache.writebacks::total 841276 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 704782 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 704782 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666649 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1666649 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5284 # 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number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384771 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384771 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384771 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384771 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 841132 # number of writebacks +system.cpu.dcache.writebacks::total 841132 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703605 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 703605 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1666863 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5233 # 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number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384522 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384522 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384522 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384522 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62998918220 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62998918220 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529906000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529906000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154205500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154205500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3684111500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3684111500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121050 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121050 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047283 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047283 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086014 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086014 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091183 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091183 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 7900594 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1036606 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.621598 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 507.835115 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.991865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10037466 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10037466 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7904302 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7904302 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7904302 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7904302 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7904302 # number of overall hits -system.cpu.icache.overall_hits::total 7904302 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1093336 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1093336 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1093336 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8997638 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8997638 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8997638 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8997638 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121514 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121514 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121514 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121514 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.257083 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14903.257083 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.257083 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14903.257083 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.257083 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14903.257083 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 10533 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10027828 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10027828 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7900595 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7900595 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7900595 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7900595 # 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number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 304 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 34.993355 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 36.726974 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53508 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53508 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53508 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53508 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53508 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53508 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039828 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1039828 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1039828 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1039828 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1039828 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1039828 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14359854493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14359854493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14359854493 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13809.836332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1036098 # number of writebacks +system.cpu.icache.writebacks::total 1036098 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53275 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53275 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53275 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53275 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.680280 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338309 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65280.236813 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4173910 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403476 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.344878 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 9183094000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53277.296150 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.937838 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6694.002825 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.812947 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081008 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.102142 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996097 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 338547 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65279.196063 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4167773 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403714 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.323578 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 9186443000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53290.316378 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5240.255410 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6748.624275 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.813146 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.079960 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.102976 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996081 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # 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average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71428.571429 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.477773 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.477773 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124665.197355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124665.197355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114209.347842 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114209.347842 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208254.906205 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208254.906205 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210975.042352 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210975.042352 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4883718 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2441508 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4877464 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2438379 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2147995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2144933 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 958852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1860290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 154 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301527 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301527 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039828 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 958726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1035547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 821965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301462 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301462 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1036979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3117755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4239617 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7357372 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66528832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143662708 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210191540 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422209 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5321984 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032932 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3109189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4238791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7347980 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132621440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143635700 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 276257140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422449 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2878054 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001305 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.036107 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5316206 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5778 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2874297 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3757 0.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5321984 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3296198000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2878054 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4329025000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1561216545 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1556715501 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2115809899 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2115441305 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1235,45 +1241,45 @@ system.iobus.pkt_size_system.bridge.master::total 44148 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 444000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14342000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5944500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 219000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 132500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215079498 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215036503 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.249403 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.249428 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1725991887000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.249403 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078088 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078088 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1725995793000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.249428 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1287,14 +1293,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21903883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21903883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427983615 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427983615 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21903883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21903883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21903883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21903883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5430705120 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5430705120 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21806383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1311,19 +1317,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126612.040462 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126612.040462 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.103557 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130631.103557 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126612.040462 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126612.040462 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130696.599923 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130696.599923 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 216 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.705882 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1337,14 +1343,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13253883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13253883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350383615 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350383615 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13253883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13253883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13253883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13253883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353105120 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3353105120 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13156383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1353,64 +1359,64 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76612.040462 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.103557 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.103557 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80696.599923 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80696.599923 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295909 # Transaction distribution +system.membus.trans_dist::ReadResp 295855 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117557 # Transaction distribution -system.membus.trans_dist::CleanEvict 261789 # Transaction distribution -system.membus.trans_dist::UpgradeReq 334 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117574 # Transaction distribution +system.membus.trans_dist::CleanEvict 261706 # Transaction distribution +system.membus.trans_dist::UpgradeReq 351 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 341 # Transaction distribution -system.membus.trans_dist::ReadExReq 115275 # Transaction distribution -system.membus.trans_dist::ReadExResp 115275 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289062 # Transaction distribution -system.membus.trans_dist::BadAddressError 83 # Transaction distribution +system.membus.trans_dist::UpgradeResp 358 # Transaction distribution +system.membus.trans_dist::ReadExReq 115261 # Transaction distribution +system.membus.trans_dist::ReadExResp 115261 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289006 # Transaction distribution +system.membus.trans_dist::BadAddressError 81 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146388 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179610 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179438 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1304427 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1304255 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754676 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751412 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33412404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33409140 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842283 # Request fanout histogram +system.membus.snoop_fanout::samples 842165 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842283 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842165 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842283 # Request fanout histogram -system.membus.reqLayer0.occupancy 28662500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842165 # Request fanout histogram +system.membus.reqLayer0.occupancy 28939500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313672631 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314315898 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 106500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139416664 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139099889 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69895667 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69817453 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1444,28 +1450,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74668 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211011 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182251 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73301 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105567 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182242 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73301 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148613 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818203066500 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62700500 0.00% 96.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 538036000 0.03% 96.96% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 56940563000 3.04% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1875744366000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818035067000 96.92% 96.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64907500 0.00% 96.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561478000 0.03% 96.96% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57098083500 3.04% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1875759536000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815430 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815427 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1504,7 +1510,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175134 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175125 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1513,20 +1519,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191979 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191970 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326325 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29901576500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2896080000 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1842946701500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394011 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29997949500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2897677500 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842863901000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 8f58e32e6..54688b406 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841615 # Number of seconds simulated -sim_ticks 1841615117500 # Number of ticks simulated -final_tick 1841615117500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.843590 # Number of seconds simulated +sim_ticks 1843589966000 # Number of ticks simulated +final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220643 # Simulator instruction rate (inst/s) -host_op_rate 220643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5550131764 # Simulator tick rate (ticks/s) -host_mem_usage 377148 # Number of bytes of host memory used -host_seconds 331.81 # Real time elapsed on the host -sim_insts 73212541 # Number of instructions simulated -sim_ops 73212541 # Number of ops (including micro ops) simulated +host_inst_rate 220463 # Simulator instruction rate (inst/s) +host_op_rate 220463 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5656183181 # Simulator tick rate (ticks/s) +host_mem_usage 378132 # Number of bytes of host memory used +host_seconds 325.94 # Real time elapsed on the host +sim_insts 71858146 # Number of instructions simulated +sim_ops 71858146 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 495296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20794752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 141504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1560960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 279936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2513472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 498752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20812864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 142016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1542016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 270784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2513856 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25786880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 495296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 141504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 279936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 916736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7468864 # Number of bytes written to this memory -system.physmem.bytes_written::total 7468864 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 324918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24390 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4374 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39273 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25781248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 498752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 142016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 270784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 911552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7470272 # Number of bytes written to this memory +system.physmem.bytes_written::total 7470272 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 325201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39279 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 268947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 11291584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 847604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 152006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1364819 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116723 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116723 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 270533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 11289313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 836420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 146879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1363566 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14002318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 268947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 152006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 497789 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4055605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4055605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4055605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 268947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 11291584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 847604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 152006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1364819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13984264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 270533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 146879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494444 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4052025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4052025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 270533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 11289313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 836420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 146879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1363566 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18057923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 70263 # Number of read requests accepted -system.physmem.writeReqs 43985 # Number of write requests accepted -system.physmem.readBursts 70263 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 43985 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 4495872 # Total number of bytes read from DRAM +system.physmem.bw_total::total 18036288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 69838 # Number of read requests accepted +system.physmem.writeReqs 42816 # Number of write requests accepted +system.physmem.readBursts 69838 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 42816 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 4468672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue -system.physmem.bytesWritten 2813888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 4496832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2815040 # Total written bytes from the system interface side +system.physmem.bytesWritten 2738752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 4469632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2740224 # Total written bytes from the system interface side system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 17213 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4359 # Per bank write bursts -system.physmem.perBankRdBursts::1 4121 # Per bank write bursts -system.physmem.perBankRdBursts::2 4307 # Per bank write bursts -system.physmem.perBankRdBursts::3 4650 # Per bank write bursts -system.physmem.perBankRdBursts::4 3946 # Per bank write bursts -system.physmem.perBankRdBursts::5 4779 # Per bank write bursts -system.physmem.perBankRdBursts::6 4258 # Per bank write bursts -system.physmem.perBankRdBursts::7 4152 # Per bank write bursts -system.physmem.perBankRdBursts::8 4721 # Per bank write bursts -system.physmem.perBankRdBursts::9 4422 # Per bank write bursts -system.physmem.perBankRdBursts::10 4675 # Per bank write bursts -system.physmem.perBankRdBursts::11 4103 # Per bank write bursts -system.physmem.perBankRdBursts::12 4083 # Per bank write bursts -system.physmem.perBankRdBursts::13 4580 # Per bank write bursts -system.physmem.perBankRdBursts::14 4738 # Per bank write bursts -system.physmem.perBankRdBursts::15 4354 # Per bank write bursts -system.physmem.perBankWrBursts::0 2794 # Per bank write bursts -system.physmem.perBankWrBursts::1 2415 # Per bank write bursts -system.physmem.perBankWrBursts::2 2758 # Per bank write bursts -system.physmem.perBankWrBursts::3 3153 # Per bank write bursts -system.physmem.perBankWrBursts::4 2458 # Per bank write bursts -system.physmem.perBankWrBursts::5 2922 # Per bank write bursts -system.physmem.perBankWrBursts::6 2626 # Per bank write bursts -system.physmem.perBankWrBursts::7 2424 # Per bank write bursts -system.physmem.perBankWrBursts::8 3273 # Per bank write bursts -system.physmem.perBankWrBursts::9 2590 # Per bank write bursts -system.physmem.perBankWrBursts::10 2930 # Per bank write bursts -system.physmem.perBankWrBursts::11 2458 # Per bank write bursts -system.physmem.perBankWrBursts::12 2433 # Per bank write bursts -system.physmem.perBankWrBursts::13 2833 # Per bank write bursts -system.physmem.perBankWrBursts::14 3042 # Per bank write bursts -system.physmem.perBankWrBursts::15 2858 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 59609 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4348 # Per bank write bursts +system.physmem.perBankRdBursts::1 4129 # Per bank write bursts +system.physmem.perBankRdBursts::2 4337 # Per bank write bursts +system.physmem.perBankRdBursts::3 4598 # Per bank write bursts +system.physmem.perBankRdBursts::4 3888 # Per bank write bursts +system.physmem.perBankRdBursts::5 4661 # Per bank write bursts +system.physmem.perBankRdBursts::6 4236 # Per bank write bursts +system.physmem.perBankRdBursts::7 4148 # Per bank write bursts +system.physmem.perBankRdBursts::8 4711 # Per bank write bursts +system.physmem.perBankRdBursts::9 4417 # Per bank write bursts +system.physmem.perBankRdBursts::10 4595 # Per bank write bursts +system.physmem.perBankRdBursts::11 4084 # Per bank write bursts +system.physmem.perBankRdBursts::12 4057 # Per bank write bursts +system.physmem.perBankRdBursts::13 4571 # Per bank write bursts +system.physmem.perBankRdBursts::14 4705 # Per bank write bursts +system.physmem.perBankRdBursts::15 4338 # Per bank write bursts +system.physmem.perBankWrBursts::0 2799 # Per bank write bursts +system.physmem.perBankWrBursts::1 2436 # Per bank write bursts +system.physmem.perBankWrBursts::2 2776 # Per bank write bursts +system.physmem.perBankWrBursts::3 2976 # Per bank write bursts +system.physmem.perBankWrBursts::4 2273 # Per bank write bursts +system.physmem.perBankWrBursts::5 2670 # Per bank write bursts +system.physmem.perBankWrBursts::6 2480 # Per bank write bursts +system.physmem.perBankWrBursts::7 2289 # Per bank write bursts +system.physmem.perBankWrBursts::8 3133 # Per bank write bursts +system.physmem.perBankWrBursts::9 2510 # Per bank write bursts +system.physmem.perBankWrBursts::10 2861 # Per bank write bursts +system.physmem.perBankWrBursts::11 2441 # Per bank write bursts +system.physmem.perBankWrBursts::12 2439 # Per bank write bursts +system.physmem.perBankWrBursts::13 2832 # Per bank write bursts +system.physmem.perBankWrBursts::14 3033 # Per bank write bursts +system.physmem.perBankWrBursts::15 2845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 1840603135000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 1842578089000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 70263 # Read request sizes (log2) +system.physmem.readPktSize::6 69838 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 43985 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 42816 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,195 +153,199 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 1909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.690812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 203.028180 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 371.433574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7252 35.78% 35.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4628 22.84% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1637 8.08% 66.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 935 4.61% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 704 3.47% 74.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 532 2.63% 77.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 447 2.21% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 402 1.98% 81.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3729 18.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20266 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1889 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.186342 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 837.829732 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 1887 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.185887 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.348650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 370.654869 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7177 35.77% 35.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4604 22.94% 58.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1640 8.17% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 939 4.68% 71.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 711 3.54% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 484 2.41% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 449 2.24% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 396 1.97% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3666 18.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20066 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.694924 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 845.707060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1850 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1889 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.275278 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.746797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.833114 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.80% 1.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.48% 2.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.11% 2.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.11% 2.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1521 80.52% 83.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51 2.70% 85.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 9 0.48% 86.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 92 4.87% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.11% 91.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 5 0.26% 91.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.90% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.64% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.42% 93.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.05% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.11% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.16% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.11% 93.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.21% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.53% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 16 0.85% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 73 3.86% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.05% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.11% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 6 0.32% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.11% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1889 # Writes before turning the bus around for reads -system.physmem.totQLat 866118250 # Total ticks spent queuing -system.physmem.totMemAccLat 2183268250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 351240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12329.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 1852 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.106371 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.632339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.643623 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.84% 1.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.38% 2.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.22% 2.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 3 0.16% 2.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1503 81.16% 83.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 52 2.81% 86.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 11 0.59% 87.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 74 4.00% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.22% 91.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 8 0.43% 91.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.92% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.43% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.38% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.05% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.16% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.43% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.43% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.05% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 15 0.81% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.05% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 66 3.56% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.05% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 2 0.11% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.11% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.16% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1852 # Writes before turning the bus around for reads +system.physmem.totQLat 871326250 # Total ticks spent queuing +system.physmem.totMemAccLat 2180507500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 349115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12479.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31079.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31229.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.98 # Average write queue length when enqueuing -system.physmem.readRowHits 59265 # Number of row buffer hits during reads -system.physmem.writeRowHits 34684 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.85 # Row buffer hit rate for writes -system.physmem.avgGap 16110593.93 # Average gap between requests -system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75993120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 41365500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 269661600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 139644000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36119290320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 800836482750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 926543498730 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.762999 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1308404512000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45532240000 # Time in different power states +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.08 # Average write queue length when enqueuing +system.physmem.readRowHits 58948 # Number of row buffer hits during reads +system.physmem.writeRowHits 33602 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.48 # Row buffer hit rate for writes +system.physmem.avgGap 16356082.24 # Average gap between requests +system.physmem.pageHitRate 82.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75161520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 40936500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 267891000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 134129520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 36125026515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 799629184500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 925463073795 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.948938 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1310373436000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9805597500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9753765000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 77217840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41955375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 278272800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 145262160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35704397295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 801349556250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 926657723160 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.725709 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1308993682000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45532240000 # Time in different power states +system.physmem_1.actEnergy 76537440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41650125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 276728400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 143169120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35621035650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799049139750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 924399004725 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.002289 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1311095993000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9217388750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9016803000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4860395 # DTB read hits -system.cpu0.dtb.read_misses 6162 # DTB read misses +system.cpu0.dtb.read_hits 4864865 # DTB read hits +system.cpu0.dtb.read_misses 6190 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428546 # DTB read accesses -system.cpu0.dtb.write_hits 3431856 # DTB write hits -system.cpu0.dtb.write_misses 685 # DTB write misses +system.cpu0.dtb.read_accesses 429298 # DTB read accesses +system.cpu0.dtb.write_hits 3435007 # DTB write hits +system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 164529 # DTB write accesses -system.cpu0.dtb.data_hits 8292251 # DTB hits -system.cpu0.dtb.data_misses 6847 # DTB misses +system.cpu0.dtb.write_accesses 165213 # DTB write accesses +system.cpu0.dtb.data_hits 8299872 # DTB hits +system.cpu0.dtb.data_misses 6878 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 593075 # DTB accesses -system.cpu0.itb.fetch_hits 2736971 # ITB hits -system.cpu0.itb.fetch_misses 3081 # ITB misses +system.cpu0.dtb.data_accesses 594511 # DTB accesses +system.cpu0.itb.fetch_hits 2740787 # ITB hits +system.cpu0.itb.fetch_misses 3088 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2740052 # ITB accesses +system.cpu0.itb.fetch_accesses 2743875 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -354,87 +358,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 927057463 # number of cpu cycles simulated +system.cpu0.numCycles 928566651 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31701170 # Number of instructions committed -system.cpu0.committedOps 31701170 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29591762 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 163845 # Number of float alu accesses -system.cpu0.num_func_calls 797475 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4044448 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29591762 # number of integer instructions -system.cpu0.num_fp_insts 163845 # number of float instructions -system.cpu0.num_int_register_reads 41150829 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21753171 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84843 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86199 # number of times the floating registers were written -system.cpu0.num_mem_refs 8322031 # number of memory refs -system.cpu0.num_load_insts 4881580 # Number of load instructions -system.cpu0.num_store_insts 3440451 # Number of store instructions -system.cpu0.num_idle_cycles 904905994.152015 # Number of idle cycles -system.cpu0.num_busy_cycles 22151468.847985 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023894 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976106 # Percentage of idle cycles -system.cpu0.Branches 5099323 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1600258 5.05% 5.05% # Class of executed instruction -system.cpu0.op_class::IntAlu 21086062 66.50% 71.55% # Class of executed instruction -system.cpu0.op_class::IntMult 31841 0.10% 71.65% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12946 0.04% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1618 0.01% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 5012305 15.81% 87.50% # Class of executed instruction -system.cpu0.op_class::MemWrite 3443548 10.86% 98.36% # Class of executed instruction -system.cpu0.op_class::IprAccess 519649 1.64% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31708227 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211399 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211440 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818498105000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39129500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 356633500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22720515500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841614383500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1820420159000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39420000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 369089000 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22760564000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1843589232000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -473,451 +422,508 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192207 # number of callpals executed +system.cpu0.kern.callpal::total 192243 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 169 system.cpu0.kern.mode_switch_good::kernel 0.322243 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29940410000 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2625898500 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809048073000 98.23% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29996442500 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2592008500 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1811000779000 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393243 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13232435 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393755 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.494090 # Average number of references to valid blocks. +system.cpu0.committedInsts 32582067 # Number of instructions committed +system.cpu0.committedOps 32582067 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30467910 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163902 # Number of float alu accesses +system.cpu0.num_func_calls 798063 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4326151 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30467910 # number of integer instructions +system.cpu0.num_fp_insts 163902 # number of float instructions +system.cpu0.num_int_register_reads 42599897 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22343202 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84869 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86282 # number of times the floating registers were written +system.cpu0.num_mem_refs 8329685 # number of memory refs +system.cpu0.num_load_insts 4886081 # Number of load instructions +system.cpu0.num_store_insts 3443604 # Number of store instructions +system.cpu0.num_idle_cycles 904742998.483282 # Number of idle cycles +system.cpu0.num_busy_cycles 23823652.516718 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025656 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974344 # Percentage of idle cycles +system.cpu0.Branches 5381713 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1604740 4.92% 4.92% # Class of executed instruction +system.cpu0.op_class::IntAlu 21953707 67.37% 72.29% # Class of executed instruction +system.cpu0.op_class::IntMult 32143 0.10% 72.39% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.39% # Class of executed instruction +system.cpu0.op_class::FloatAdd 13006 0.04% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1630 0.01% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::MemRead 5016903 15.39% 87.83% # Class of executed instruction +system.cpu0.op_class::MemWrite 3446713 10.58% 98.40% # Class of executed instruction +system.cpu0.op_class::IprAccess 520313 1.60% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 32589155 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1393262 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13241810 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393774 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.500687 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 242.565333 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 83.938780 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 185.493697 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.473760 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.163943 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.362292 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.746834 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216845 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034134 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497552 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236752 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265692 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63378181 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63378181 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4021743 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1010855 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2545337 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7577935 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3142602 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 763669 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1364636 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5270907 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114486 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18184 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51520 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184190 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123337 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20114 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55874 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199325 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7164345 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1774524 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3909973 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12848842 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7164345 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1774524 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3909973 # number of overall hits -system.cpu0.dcache.overall_hits::total 12848842 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 725431 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 86189 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 553303 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1364923 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 164575 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 38232 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 676790 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 879597 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9407 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2049 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7768 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19224 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63387052 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63387052 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4025112 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1019452 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2537983 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7582547 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3145682 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 772489 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1357389 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275560 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114073 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19050 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51169 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184292 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122917 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21014 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55400 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199331 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7170794 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1791941 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3895372 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12858107 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7170794 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1791941 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3895372 # number of overall hits +system.cpu0.dcache.overall_hits::total 12858107 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 726690 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 86798 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 548610 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1362098 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 165054 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 38388 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 671853 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 875295 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9398 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2090 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7704 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19192 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 890006 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 124421 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1230093 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2244520 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 890006 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 124421 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1230093 # number of overall misses -system.cpu0.dcache.overall_misses::total 2244520 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2328658500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8887314500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11215973000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2137506500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29622827624 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 31760334124 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27247000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 151557500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 178804500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 125000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 125000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4466165000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 38510142124 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42976307124 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4466165000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 38510142124 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42976307124 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4747174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1097044 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3098640 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8942858 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3307177 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 801901 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2041426 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6150504 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123893 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20233 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 59288 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203414 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55878 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199330 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8054351 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1898945 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5140066 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15093362 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8054351 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1898945 # 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miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101270 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.131021 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094507 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 891744 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 125186 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1220463 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2237393 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 891744 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 125186 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1357576500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078565 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084593 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038949 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047677 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048912 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022451 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101270 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.104338 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040484 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000072 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070422 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032226 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070422 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032226 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 26018.047547 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17855.619859 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19875.387941 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54908.832915 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46358.797366 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.122282 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12297.706198 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12560.459101 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12495.081967 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 30250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34895.588365 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25718.179806 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28065.782784 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34895.588365 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25718.179806 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28065.782784 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 209105.145414 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 204871.673004 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206816.546763 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 217426.851852 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 210949.317227 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213927.071510 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 213658.054711 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 208195.002872 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210705.649542 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_hits::cpu2.data 860938 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 860938 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 860938 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 860938 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86798 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 260253 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 347051 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38388 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99272 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137660 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2090 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6122 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8212 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 125186 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 359525 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484711 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 125186 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 359525 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484711 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2652 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1618 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 1898 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3516 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223501500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676661000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6900162500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2093885000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4616741882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6710626882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25771500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103207500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 108000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 108000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4317386500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9293402882 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13610789382 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4317386500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9293402882 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13610789382 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 293417500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 298094000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591511500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372514000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 424017500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796531500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665931500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 722111500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388043000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078461 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084317 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048921 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022381 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.098865 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103987 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25616.966981 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17969.671819 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19882.272346 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54545.300615 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46505.982372 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48747.834389 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.807579 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.888456 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 36000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230231.149567 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226544.795222 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225969.290804 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.396887 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 964359 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.170929 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 40638696 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 964870 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.118312 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10553576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 255.050326 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 76.933985 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 179.186618 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.498145 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.150262 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.349974 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998381 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 963474 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.175730 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41537475 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 963985 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 43.089337 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10558559500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250464 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956509 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.968757 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.510255 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160071 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328064 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998390 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42585531 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42585531 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31196035 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7004527 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2438134 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 40638696 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31196035 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7004527 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2438134 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 40638696 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31196035 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7004527 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2438134 # number of overall hits -system.cpu0.icache.overall_hits::total 40638696 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 512192 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 123075 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 346520 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 981787 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 512192 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 123075 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 346520 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 981787 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 512192 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 123075 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 346520 # number of overall misses -system.cpu0.icache.overall_misses::total 981787 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1869616000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5082111473 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6951727473 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1869616000 # 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ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -930,64 +936,9 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953409174 # number of cpu cycles simulated +system.cpu1.numCycles 953452897 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7126126 # Number of instructions committed -system.cpu1.committedOps 7126126 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6614481 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 39892 # Number of float alu accesses -system.cpu1.num_func_calls 202987 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 849967 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6614481 # number of integer instructions -system.cpu1.num_fp_insts 39892 # number of float instructions -system.cpu1.num_int_register_reads 9205425 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4843983 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 21026 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21409 # number of times the floating registers were written -system.cpu1.num_mem_refs 1944596 # number of memory refs -system.cpu1.num_load_insts 1119921 # Number of load instructions -system.cpu1.num_store_insts 824675 # Number of store instructions -system.cpu1.num_idle_cycles 926242764.786654 # Number of idle cycles -system.cpu1.num_busy_cycles 27166409.213346 # Number of busy cycles -system.cpu1.not_idle_fraction 0.028494 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.971506 # Percentage of idle cycles -system.cpu1.Branches 1116663 # Number of branches fetched -system.cpu1.op_class::No_OpClass 388723 5.45% 5.45% # Class of executed instruction -system.cpu1.op_class::IntAlu 4626654 64.91% 70.37% # Class of executed instruction -system.cpu1.op_class::IntMult 7726 0.11% 70.47% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.47% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3756 0.05% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatDiv 538 0.01% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::MemRead 1147644 16.10% 86.64% # Class of executed instruction -system.cpu1.op_class::MemWrite 825879 11.59% 98.22% # Class of executed instruction -system.cpu1.op_class::IprAccess 126681 1.78% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7127601 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1005,35 +956,90 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 11557403 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10821969 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 122344 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 9245404 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 7393469 # Number of BTB hits +system.cpu1.committedInsts 7155032 # Number of instructions committed +system.cpu1.committedOps 7155032 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6639972 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 39507 # Number of float alu accesses +system.cpu1.num_func_calls 205327 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 849342 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6639972 # number of integer instructions +system.cpu1.num_fp_insts 39507 # number of float instructions +system.cpu1.num_int_register_reads 9236476 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4860513 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 20546 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21005 # number of times the floating registers were written +system.cpu1.num_mem_refs 1964570 # number of memory refs +system.cpu1.num_load_insts 1130012 # Number of load instructions +system.cpu1.num_store_insts 834558 # Number of store instructions +system.cpu1.num_idle_cycles 924897585.359422 # Number of idle cycles +system.cpu1.num_busy_cycles 28555311.640577 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029949 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970051 # Percentage of idle cycles +system.cpu1.Branches 1119214 # Number of branches fetched +system.cpu1.op_class::No_OpClass 390317 5.45% 5.45% # Class of executed instruction +system.cpu1.op_class::IntAlu 4631234 64.71% 70.17% # Class of executed instruction +system.cpu1.op_class::IntMult 7711 0.11% 70.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3307 0.05% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatDiv 440 0.01% 70.33% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::MemRead 1158585 16.19% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 835763 11.68% 98.20% # Class of executed instruction +system.cpu1.op_class::IprAccess 129140 1.80% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 7156497 # Class of executed instruction +system.cpu2.branchPred.lookups 10791906 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10058996 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 121698 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8434906 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6656118 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.969128 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 299976 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7838 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 78.911585 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 298697 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7721 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3543723 # DTB read hits -system.cpu2.dtb.read_misses 12250 # DTB read misses -system.cpu2.dtb.read_acv 123 # DTB read access violations -system.cpu2.dtb.read_accesses 249931 # DTB read accesses -system.cpu2.dtb.write_hits 2185333 # DTB write hits -system.cpu2.dtb.write_misses 2753 # DTB write misses -system.cpu2.dtb.write_acv 125 # DTB write access violations -system.cpu2.dtb.write_accesses 92110 # DTB write accesses -system.cpu2.dtb.data_hits 5729056 # DTB hits -system.cpu2.dtb.data_misses 15003 # DTB misses -system.cpu2.dtb.data_acv 248 # DTB access violations -system.cpu2.dtb.data_accesses 342041 # DTB accesses -system.cpu2.itb.fetch_hits 552866 # ITB hits -system.cpu2.itb.fetch_misses 5354 # ITB misses -system.cpu2.itb.fetch_acv 182 # ITB acv -system.cpu2.itb.fetch_accesses 558220 # ITB accesses +system.cpu2.dtb.read_hits 3520448 # DTB read hits +system.cpu2.dtb.read_misses 12146 # DTB read misses +system.cpu2.dtb.read_acv 125 # DTB read access violations +system.cpu2.dtb.read_accesses 256305 # DTB read accesses +system.cpu2.dtb.write_hits 2173477 # DTB write hits +system.cpu2.dtb.write_misses 2690 # DTB write misses +system.cpu2.dtb.write_acv 124 # DTB write access violations +system.cpu2.dtb.write_accesses 93625 # DTB write accesses +system.cpu2.dtb.data_hits 5693925 # DTB hits +system.cpu2.dtb.data_misses 14836 # DTB misses +system.cpu2.dtb.data_acv 249 # DTB access violations +system.cpu2.dtb.data_accesses 349930 # DTB accesses +system.cpu2.itb.fetch_hits 553155 # ITB hits +system.cpu2.itb.fetch_misses 5226 # ITB misses +system.cpu2.itb.fetch_acv 187 # ITB acv +system.cpu2.itb.fetch_accesses 558381 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1046,304 +1052,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 33083271 # number of cpu cycles simulated +system.cpu2.numCycles 32236279 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9301099 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 42932048 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 11557403 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 7693445 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 21583805 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 404638 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 962 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10456 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1990 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 197395 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 92170 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2784665 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90858 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 31390787 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.367664 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.311444 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9243840 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40617547 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10791906 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6954815 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20753592 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 401538 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 916 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10212 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2008 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 193151 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 89388 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1068 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2772679 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90084 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 30494706 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.331954 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.325119 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 21183291 67.48% 67.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 297740 0.95% 68.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 468841 1.49% 69.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5764163 18.36% 88.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 882544 2.81% 91.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 193394 0.62% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 232558 0.74% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 434405 1.38% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1933851 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 21037778 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 294298 0.97% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 469114 1.54% 71.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5033169 16.51% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 879924 2.89% 90.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194801 0.64% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 230028 0.75% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433107 1.42% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1922487 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 31390787 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.349343 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.297697 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7618981 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 14231209 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8576643 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 528584 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 189420 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 174742 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13252 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 39552027 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 41601 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 189420 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7898470 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4727919 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6647041 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8797977 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2884017 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 38737545 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 58522 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 372966 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 93481 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1809588 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 25849349 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 48570643 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 48506980 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 59488 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 23977354 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1871995 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 535640 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63418 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3866497 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3518835 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2279192 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 461417 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 331685 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 36218811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 686292 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 35933838 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15798 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2519858 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1130776 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 490718 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 31390787 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.144726 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.617565 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30494706 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.334775 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.259995 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7573321 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 14126025 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7836977 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 524605 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 187915 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 174630 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13216 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37265458 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 41467 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 187915 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7850244 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4676437 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6613578 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8057400 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2863279 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 36458401 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 57802 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 368784 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 93789 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1799072 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 24336413 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 45554095 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 45489801 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 60051 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22465786 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1870627 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 531021 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 62908 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3828322 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3503706 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2266582 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 453499 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 325031 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33954893 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 679527 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 33661057 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16143 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2513373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1127788 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 486024 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30494706 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.103833 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.612725 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18577248 59.18% 59.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2723782 8.68% 67.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1358088 4.33% 72.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 6489843 20.67% 92.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1045865 3.33% 96.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 589790 1.88% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 396015 1.26% 99.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 165397 0.53% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44759 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18452821 60.51% 60.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2702851 8.86% 69.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1349809 4.43% 73.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5753089 18.87% 92.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1041578 3.42% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 588420 1.93% 98.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 396893 1.30% 99.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 164409 0.54% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44836 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 31390787 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30494706 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 81235 20.78% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 183347 46.90% 67.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126357 32.32% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 81527 21.02% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179819 46.37% 67.39% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126481 32.61% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2960 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 29699192 82.65% 82.66% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21615 0.06% 82.72% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 21814 0.06% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1480 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3672081 10.22% 93.00% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2209398 6.15% 99.15% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 305298 0.85% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 3131 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27465013 81.59% 81.60% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21327 0.06% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 22209 0.07% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3648084 10.84% 92.57% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2197360 6.53% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 302367 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 35933838 # Type of FU issued -system.cpu2.iq.rate 1.086163 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 390939 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.010879 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 103401518 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39305388 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 35307106 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 263682 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 125410 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122335 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36181025 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 140792 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 202971 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 33661057 # Type of FU issued +system.cpu2.iq.rate 1.044198 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387827 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011522 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 97956454 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 37027606 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 33043548 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 264336 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 125822 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122705 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 33904668 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 141085 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 200240 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 432355 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1077 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5954 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178558 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 431120 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5749 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178621 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4490 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 225000 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4239 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 217381 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 189420 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4054480 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 208473 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 38277538 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51152 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3518835 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2279192 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 610930 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12812 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 160010 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5954 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 60508 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134714 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 35737943 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3564708 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 195895 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 187915 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4008679 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 205535 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35998675 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51747 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3503706 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2266582 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 605109 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12931 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 157162 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5749 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 59808 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134012 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193820 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33465262 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3541255 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 195795 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1372435 # number of nop insts executed -system.cpu2.iew.exec_refs 5757521 # number of memory reference insts executed -system.cpu2.iew.exec_branches 8471480 # Number of branches executed -system.cpu2.iew.exec_stores 2192813 # Number of stores executed -system.cpu2.iew.exec_rate 1.080242 # Inst execution rate -system.cpu2.iew.wb_sent 35472276 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 35429441 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 20887132 # num instructions producing a value -system.cpu2.iew.wb_consumers 24638595 # num instructions consuming a value +system.cpu2.iew.exec_nop 1364255 # number of nop insts executed +system.cpu2.iew.exec_refs 5722116 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7732316 # Number of branches executed +system.cpu2.iew.exec_stores 2180861 # Number of stores executed +system.cpu2.iew.exec_rate 1.038124 # Inst execution rate +system.cpu2.iew.wb_sent 33208664 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 33166253 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 19395256 # num instructions producing a value +system.cpu2.iew.wb_consumers 23138933 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.070917 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.847740 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.028849 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.838209 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2638965 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 195574 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 178349 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 30927462 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.150843 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846358 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2630446 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 193503 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 177071 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 30033551 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.109504 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.847540 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 19331784 62.51% 62.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2240622 7.24% 69.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1164134 3.76% 73.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6211408 20.08% 93.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 591221 1.91% 95.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 197085 0.64% 96.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 163594 0.53% 96.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 163249 0.53% 97.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 864365 2.79% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 19200071 63.93% 63.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2226295 7.41% 71.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1158853 3.86% 75.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5473619 18.23% 93.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 589521 1.96% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 197097 0.66% 96.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164200 0.55% 96.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 162437 0.54% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 861458 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 30927462 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 35592650 # Number of instructions committed -system.cpu2.commit.committedOps 35592650 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 30033551 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 33322350 # Number of instructions committed +system.cpu2.commit.committedOps 33322350 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5187114 # Number of memory references committed -system.cpu2.commit.loads 3086480 # Number of loads committed -system.cpu2.commit.membars 68869 # Number of memory barriers committed -system.cpu2.commit.branches 8299152 # Number of branches committed -system.cpu2.commit.fp_insts 120520 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 34085086 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241488 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1210365 3.40% 3.40% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 28775352 80.85% 84.25% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 21144 0.06% 84.31% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21379 0.06% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1480 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3155349 8.87% 93.24% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2102283 5.91% 99.14% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 305298 0.86% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5160547 # Number of memory references committed +system.cpu2.commit.loads 3072586 # Number of loads committed +system.cpu2.commit.membars 67946 # Number of memory barriers committed +system.cpu2.commit.branches 7560075 # Number of branches committed +system.cpu2.commit.fp_insts 120848 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31822701 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240099 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1204434 3.61% 3.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26541208 79.65% 83.26% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20874 0.06% 83.33% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21768 0.07% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3140532 9.42% 92.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2089601 6.27% 99.09% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 302367 0.91% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 35592650 # Class of committed instruction -system.cpu2.commit.bw_lim_events 864365 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 68219321 # The number of ROB reads -system.cpu2.rob.rob_writes 76925100 # The number of ROB writes -system.cpu2.timesIdled 177793 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1692484 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1742724515 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 34385245 # Number of Instructions Simulated -system.cpu2.committedOps 34385245 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.962136 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.962136 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.039354 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.039354 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 46956630 # number of integer regfile reads -system.cpu2.int_regfile_writes 24762728 # number of integer regfile writes -system.cpu2.fp_regfile_reads 74199 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74347 # number of floating regfile writes -system.cpu2.misc_regfile_reads 6109617 # number of misc regfile reads -system.cpu2.misc_regfile_writes 275370 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 33322350 # Class of committed instruction +system.cpu2.commit.bw_lim_events 861458 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 65049813 # The number of ROB reads +system.cpu2.rob.rob_writes 72365341 # The number of ROB writes +system.cpu2.timesIdled 178213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1741573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747477665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 32121047 # Number of Instructions Simulated +system.cpu2.committedOps 32121047 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.003587 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.003587 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.996425 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.996425 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 43934131 # number of integer regfile reads +system.cpu2.int_regfile_writes 23251716 # number of integer regfile writes +system.cpu2.fp_regfile_reads 74710 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74652 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5374912 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272966 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1358,9 +1365,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51362 # Transaction distribution -system.iobus.trans_dist::WriteResp 51362 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51364 # Transaction distribution +system.iobus.trans_dist::WriteResp 51364 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5196 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1372,11 +1379,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1388,37 +1395,37 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45584 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2206000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2564500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 116500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 55500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5525000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2084000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2121000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 88878376 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 84230549 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9362000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17358000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16458000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254039 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261273 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693946387000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254039 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078377 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078377 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694926918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261273 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078830 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1432,14 +1439,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9722962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9722962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2243179414 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2243179414 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9722962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9722962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9722962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9722962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9458962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9458962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2126843587 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2126843587 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9458962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9458962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9458962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9458962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1456,266 +1463,270 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56202.092486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 56202.092486 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 53984.872305 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 53984.872305 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 56202.092486 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 56202.092486 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54676.080925 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54676.080925 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 51185.107504 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 51185.107504 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54676.080925 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54676.080925 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5.166667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 71 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17168 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 17168 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 71 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 71 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 71 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 71 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6172962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6172962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1384779414 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1384779414 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 6172962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6172962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 6172962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6172962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.410405 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.413169 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.413169 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.410405 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.410405 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 86943.126761 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80660.497088 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80660.497088 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 86943.126761 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86943.126761 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 86943.126761 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16272 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 16272 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 69 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 69 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 69 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 69 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6008962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6008962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1313243587 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1313243587 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 6008962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6008962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 6008962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6008962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.391606 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.391606 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.398844 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.398844 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 87086.405797 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80705.726831 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80705.726831 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337421 # number of replacements -system.l2c.tags.tagsinuse 65422.020035 # Cycle average of tags in use -system.l2c.tags.total_refs 4006967 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402583 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.953145 # Average number of references to valid blocks. +system.l2c.tags.replacements 337614 # number of replacements +system.l2c.tags.tagsinuse 65425.004009 # Cycle average of tags in use +system.l2c.tags.total_refs 4005267 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402776 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.944155 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54749.853403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2632.785518 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2879.050483 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 437.699618 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 567.874446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2112.962465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2041.794102 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.040173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043931 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.006679 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008665 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032241 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.031155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998261 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54894.973613 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2664.591905 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2878.625445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 441.912379 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 553.808439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2003.360689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1987.731539 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837631 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.040658 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.006743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008450 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.030569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.030330 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998306 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 717 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6187 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2728 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55352 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 713 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2779 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55356 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38426412 # Number of tag accesses -system.l2c.tags.data_accesses 38426412 # Number of data accesses -system.l2c.Writeback_hits::writebacks 835815 # number of Writeback hits -system.l2c.Writeback_hits::total 835815 # number of Writeback hits +system.l2c.tags.tag_accesses 38412750 # Number of tag accesses +system.l2c.tags.data_accesses 38412750 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 835859 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 835859 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 963177 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 963177 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 90170 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 24197 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 72759 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187126 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 504433 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 120864 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 325383 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 950680 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 484059 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 77838 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 255762 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 817659 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 504433 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 574229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 120864 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 102035 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 325383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 328521 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955465 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 504433 # number of overall hits -system.l2c.overall_hits::cpu0.data 574229 # number of overall hits -system.l2c.overall_hits::cpu1.inst 120864 # number of overall hits -system.l2c.overall_hits::cpu1.data 102035 # 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mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.363456 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.273358 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.135832 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006690 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.114594 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046721 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.029775 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.029775 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 71750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71750 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 70500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117392.867322 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125466.345449 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 122724.652761 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122845.861807 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116726.778846 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117147.104153 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116954.769447 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117109.355816 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122877.763756 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 120879.499993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122264.586160 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117109.355816 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123139.689072 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122877.763756 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 120879.499993 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196605.145414 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 192371.673004 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 194316.546763 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 205926.851852 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 199449.317227 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 202427.071510 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 201705.167173 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 196241.815049 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 198752.599721 # average overall mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117532.325115 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125700.959841 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 122930.961987 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123226.356589 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116441.046534 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117536.509851 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117043.234163 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208275.395034 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 212804.232804 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210534.690799 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218725.587145 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211900.421496 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215041.240046 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214012.894469 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212271.654766 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213103.599222 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294893 # Transaction distribution -system.membus.trans_dist::WriteReq 9810 # Transaction distribution -system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116701 # Transaction distribution -system.membus.trans_dist::CleanEvict 261800 # Transaction distribution -system.membus.trans_dist::UpgradeReq 141 # Transaction distribution +system.membus.trans_dist::ReadResp 294754 # Transaction distribution +system.membus.trans_dist::WriteReq 9812 # Transaction distribution +system.membus.trans_dist::WriteResp 9812 # Transaction distribution +system.membus.trans_dist::WritebackDirty 116723 # Transaction distribution +system.membus.trans_dist::CleanEvict 261691 # Transaction distribution +system.membus.trans_dist::UpgradeReq 160 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 143 # Transaction distribution -system.membus.trans_dist::ReadExReq 115600 # Transaction distribution -system.membus.trans_dist::ReadExResp 115600 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288004 # Transaction distribution -system.membus.trans_dist::BadAddressError 255 # Transaction distribution +system.membus.trans_dist::UpgradeResp 162 # Transaction distribution +system.membus.trans_dist::ReadExReq 115651 # Transaction distribution +system.membus.trans_dist::ReadExResp 115651 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287866 # Transaction distribution +system.membus.trans_dist::BadAddressError 256 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143509 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177927 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1302846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30608832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30654400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33318656 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 161 # Total snoops (count) -system.membus.snoop_fanout::samples 840917 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 512 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177708 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1302629 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30604608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30650192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33314576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 159 # Total snoops (count) +system.membus.snoop_fanout::samples 840768 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840917 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840768 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840917 # Request fanout histogram -system.membus.reqLayer0.occupancy 11282500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840768 # Request fanout histogram +system.membus.reqLayer0.occupancy 11147000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 355534840 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 348692458 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 348500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 377985955 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 375048955 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 28782491 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 27286702 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4716700 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2358029 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1601 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1128 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1128 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4714972 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2357166 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1129 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1129 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2063159 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 879803 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1563697 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 38 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302846 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302846 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 965048 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091237 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 255 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 17168 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2894139 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214034 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7108173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61761536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142741760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204503296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421014 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5154488 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.000869 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.029472 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2062235 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 878682 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 963177 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 599628 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 39 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302904 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302904 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 964165 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091197 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 256 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 16272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891480 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214095 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7105575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123348160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142745680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266093840 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421214 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4208473 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000983 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.031334 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5150007 99.91% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4481 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4204337 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4136 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5154488 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1335525500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4208473 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1783329500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 102462 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 99462 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 679735096 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 678448171 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 746367473 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 743541954 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |