diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
9 files changed, 3729 insertions, 3715 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 0d25f966b..edbc5da0f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1001,6 +1001,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -1026,25 +1027,28 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -1073,6 +1077,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 560862c38..dcd646636 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:29:25 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 23:18:50 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 107825000 -Exiting @ tick 1901719660500 because m5_exit instruction encountered +info: Launching CPU 1 @ 110215000 +Exiting @ tick 1900727015500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 7d7f83f12..af3e1799f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897808 # Number of seconds simulated -sim_ticks 1897807508000 # Number of ticks simulated -final_tick 1897807508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.900727 # Number of seconds simulated +sim_ticks 1900727015500 # Number of ticks simulated +final_tick 1900727015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94343 # Simulator instruction rate (inst/s) -host_op_rate 94343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3156287920 # Simulator tick rate (ticks/s) -host_mem_usage 338708 # Number of bytes of host memory used -host_seconds 601.28 # Real time elapsed on the host -sim_insts 56726638 # Number of instructions simulated -sim_ops 56726638 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 852800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24659584 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 123904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 537024 # Number of bytes read from this memory -system.physmem.bytes_read::total 28824960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 852800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 123904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7794816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7794816 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385306 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8391 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450390 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121794 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121794 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449361 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12993722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1397217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 65288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15188558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449361 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 65288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 514649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4107274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4107274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4107274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12993722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 65288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 282971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19295833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450390 # Total number of read requests seen -system.physmem.writeReqs 121794 # Total number of write requests seen -system.physmem.cpureqs 577229 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28824960 # Total number of bytes read from memory -system.physmem.bytesWritten 7794816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28824960 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7794816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5032 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28516 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28018 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28103 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27811 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28047 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27949 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7700 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7581 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7841 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7706 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7677 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7592 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7617 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7323 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7475 # Track writes on a per bank basis +host_inst_rate 47037 # Simulator instruction rate (inst/s) +host_op_rate 47037 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1570523818 # Simulator tick rate (ticks/s) +host_mem_usage 354648 # Number of bytes of host memory used +host_seconds 1210.25 # Real time elapsed on the host +sim_insts 56926994 # Number of instructions simulated +sim_ops 56926994 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 854592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24596416 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 541184 # Number of bytes read from this memory +system.physmem.bytes_read::total 28767552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 854592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7730624 # Number of bytes written to this memory +system.physmem.bytes_written::total 7730624 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13353 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384319 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449493 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120791 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120791 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12940531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 284725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15135026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449613 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64952 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 514565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4067193 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4067193 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4067193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12940531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 284725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19202219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449493 # Total number of read requests seen +system.physmem.writeReqs 120791 # Total number of write requests seen +system.physmem.cpureqs 575904 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28767552 # Total number of bytes read from memory +system.physmem.bytesWritten 7730624 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28767552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7730624 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5612 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28381 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27984 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28071 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27942 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27828 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27852 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7701 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7520 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7578 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7608 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7520 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7649 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7589 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7235 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7444 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7350 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry -system.physmem.totGap 1897802972000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 1900722456000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450390 # Categorize read packet sizes +system.physmem.readPktSize::6 449493 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121794 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 319842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120791 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 319839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -138,224 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.totQLat 7744912500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15549496250 # Sum of mem lat for all requests -system.physmem.totBusLat 2251660000 # Total cycles spent in databus access -system.physmem.totBankLat 5552923750 # Total cycles spent in bank access -system.physmem.avgQLat 17198.23 # Average queueing delay per request -system.physmem.avgBankLat 12330.73 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2081 # 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Average queueing delay per request +system.physmem.avgBankLat 12336.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34528.96 # Average memory access latency -system.physmem.avgRdBW 15.19 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.19 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34459.71 # Average memory access latency +system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.07 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.07 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.90 # Average write queue length over time -system.physmem.readRowHits 422298 # Number of row buffer hits during reads -system.physmem.writeRowHits 93666 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.91 # Row buffer hit rate for writes -system.physmem.avgGap 3316770.43 # Average gap between requests -system.l2c.replacements 343496 # number of replacements -system.l2c.tagsinuse 65280.770120 # Cycle average of tags in use -system.l2c.total_refs 2576734 # Total number of references to valid blocks. -system.l2c.sampled_refs 408507 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.307686 # Average number of references to valid blocks. +system.physmem.avgWrQLen 9.46 # Average write queue length over time +system.physmem.readRowHits 421587 # Number of row buffer hits during reads +system.physmem.writeRowHits 92850 # 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number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 274 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 442 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 153309 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26446 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179755 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 850039 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 884437 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 225279 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 98347 # number of demand (read+write) hits -system.l2c.demand_hits::total 2058102 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 850039 # 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number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -534,40 +534,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120796.598870 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254784.063848 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 254784.063848 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 254215.735316 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 254215.735316 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 254215.735316 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 254215.735316 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 281558 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120743.005587 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120743.005587 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255695.512683 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255695.512683 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255116.650476 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255116.650476 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284705 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 26875 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27170 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.476577 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.478653 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12176249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8424789680 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8424789680 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8436965929 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8436965929 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8436965929 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8436965929 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12304249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12304249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8462672446 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8462672446 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8474976695 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8474976695 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8474976695 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8474976695 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -576,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202752.928379 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 202752.928379 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202184.713964 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 202184.713964 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202184.713964 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 202184.713964 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68738.821229 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68738.821229 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203664.623749 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203664.623749 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -597,35 +597,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12324830 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10383801 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 330699 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7879276 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5243296 # Number of BTB hits +system.cpu0.branchPred.lookups 12043910 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10154859 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 320144 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7755165 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5137994 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.545403 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 784421 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32635 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.252543 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 760181 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 30092 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8754095 # DTB read hits -system.cpu0.dtb.read_misses 29935 # DTB read misses -system.cpu0.dtb.read_acv 546 # DTB read access violations -system.cpu0.dtb.read_accesses 624217 # DTB read accesses -system.cpu0.dtb.write_hits 5744304 # DTB write hits -system.cpu0.dtb.write_misses 8066 # DTB write misses -system.cpu0.dtb.write_acv 350 # DTB write access violations -system.cpu0.dtb.write_accesses 207709 # DTB write accesses -system.cpu0.dtb.data_hits 14498399 # DTB hits -system.cpu0.dtb.data_misses 38001 # DTB misses -system.cpu0.dtb.data_acv 896 # DTB access violations -system.cpu0.dtb.data_accesses 831926 # DTB accesses -system.cpu0.itb.fetch_hits 984231 # ITB hits -system.cpu0.itb.fetch_misses 30400 # ITB misses -system.cpu0.itb.fetch_acv 951 # ITB acv -system.cpu0.itb.fetch_accesses 1014631 # ITB accesses +system.cpu0.dtb.read_hits 8552844 # DTB read hits +system.cpu0.dtb.read_misses 30306 # DTB read misses +system.cpu0.dtb.read_acv 545 # DTB read access violations +system.cpu0.dtb.read_accesses 625084 # DTB read accesses +system.cpu0.dtb.write_hits 5600708 # DTB write hits +system.cpu0.dtb.write_misses 7703 # DTB write misses +system.cpu0.dtb.write_acv 337 # DTB write access violations +system.cpu0.dtb.write_accesses 207517 # DTB write accesses +system.cpu0.dtb.data_hits 14153552 # DTB hits +system.cpu0.dtb.data_misses 38009 # DTB misses +system.cpu0.dtb.data_acv 882 # DTB access violations +system.cpu0.dtb.data_accesses 832601 # DTB accesses +system.cpu0.itb.fetch_hits 972187 # ITB hits +system.cpu0.itb.fetch_misses 27447 # ITB misses +system.cpu0.itb.fetch_acv 929 # ITB acv +system.cpu0.itb.fetch_accesses 999634 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,269 +638,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 101829868 # number of cpu cycles simulated +system.cpu0.numCycles 100158206 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24831231 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63164825 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12324830 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6027717 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11886034 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1687418 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36616651 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 32610 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 197530 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 292271 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 247 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7635312 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223745 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 74945500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.842810 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.180311 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24091830 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 61851140 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12043910 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5898175 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11655326 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1636923 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36054530 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195301 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 286219 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7501974 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 215877 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 73371591 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.842985 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.179628 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63059466 84.14% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 761662 1.02% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1556791 2.08% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 699013 0.93% 88.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2562383 3.42% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 515928 0.69% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 568129 0.76% 93.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 822428 1.10% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4399700 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 61716265 84.11% 84.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 747527 1.02% 85.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1537071 2.09% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 679895 0.93% 88.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2532643 3.45% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 504962 0.69% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 557623 0.76% 93.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 776174 1.06% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4319431 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74945500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121034 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.620298 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26048767 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36112585 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10811010 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 918999 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1054138 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 507624 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35116 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62016567 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105227 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1054138 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27056479 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14636567 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17989986 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10129953 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4078375 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58716570 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6669 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 641571 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1425002 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39326634 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71486416 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71104766 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 381650 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34557314 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4769312 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1434958 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 208601 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11111126 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9162338 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6008284 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124943 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 741369 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52108127 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1785217 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 50965376 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88359 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5842472 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2979590 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1208696 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 74945500 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.680033 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329236 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 73371591 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120249 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.617534 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25319035 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 35526581 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10596329 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 906729 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1022916 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 497694 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33826 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 60727079 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 100309 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1022916 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 26298028 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14528907 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17589039 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9932796 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3999903 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 57523389 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6753 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 634761 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1396221 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 38578819 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 70143462 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69780146 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 363316 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33936686 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4642125 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1392017 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201999 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10851427 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8946001 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5847624 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1117431 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 730012 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 51082073 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1726481 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49977399 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 73178 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5678222 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2880000 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1168367 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 73371591 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.681155 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.330222 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52296103 69.78% 69.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10307056 13.75% 83.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4639666 6.19% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3056082 4.08% 93.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2432821 3.25% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1212271 1.62% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 643524 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 306857 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51120 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 51161805 69.73% 69.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10104192 13.77% 83.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4556124 6.21% 89.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2996769 4.08% 93.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2381620 3.25% 97.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1186935 1.62% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 631731 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 300209 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52206 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74945500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 73371591 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 83315 12.44% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 310574 46.36% 58.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 276009 41.20% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82861 12.68% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 300856 46.05% 58.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 269656 41.27% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35160159 68.99% 69.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56163 0.11% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9109271 17.87% 87.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5812211 11.40% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 806271 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34556272 69.14% 69.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54837 0.11% 69.26% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15268 0.03% 69.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8895592 17.80% 87.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5666859 11.34% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 782918 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 50965376 # Type of FU issued -system.cpu0.iq.rate 0.500495 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 669898 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 177086282 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59482873 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 49950097 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 548226 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 265331 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 258806 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51344519 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 286981 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 543841 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49977399 # Type of FU issued +system.cpu0.iq.rate 0.498985 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 653373 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013073 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 173532405 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 58247054 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48998129 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 520534 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 252057 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 245907 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50354702 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 272296 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 532613 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1097645 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3519 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12633 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 446832 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1057319 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3456 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12575 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 434127 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18414 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 123451 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18424 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 121082 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1054138 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10442164 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 794127 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57094083 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 608812 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9162338 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6008284 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1572405 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 581948 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5528 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12633 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164589 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 346313 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 510902 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50577895 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8807105 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 387480 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1022916 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10363943 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 778495 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 55942043 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 586758 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8946001 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5847624 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1520655 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 566622 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4762 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12575 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160322 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 334940 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 495262 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49600607 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8605587 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 376791 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3200739 # number of nop insts executed -system.cpu0.iew.exec_refs 14572965 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8058105 # Number of branches executed -system.cpu0.iew.exec_stores 5765860 # Number of stores executed -system.cpu0.iew.exec_rate 0.496690 # Inst execution rate -system.cpu0.iew.wb_sent 50296670 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50208903 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25061095 # num instructions producing a value -system.cpu0.iew.wb_consumers 33769433 # num instructions consuming a value +system.cpu0.iew.exec_nop 3133489 # number of nop insts executed +system.cpu0.iew.exec_refs 14227227 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7905275 # Number of branches executed +system.cpu0.iew.exec_stores 5621640 # Number of stores executed +system.cpu0.iew.exec_rate 0.495223 # Inst execution rate +system.cpu0.iew.wb_sent 49330113 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 49244036 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24627791 # num instructions producing a value +system.cpu0.iew.wb_consumers 33147398 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.493067 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742124 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.491663 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742978 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6306622 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 576521 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 477545 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 73891362 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.686006 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.603918 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6114712 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 558114 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 462555 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 72348675 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.687235 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.603400 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 54863146 74.25% 74.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7931478 10.73% 84.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4331360 5.86% 90.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2351860 3.18% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1314304 1.78% 95.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 548181 0.74% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466916 0.63% 97.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 432440 0.59% 97.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1651677 2.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 53652549 74.16% 74.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7790867 10.77% 84.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4280150 5.92% 90.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2308289 3.19% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1285405 1.78% 95.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 537706 0.74% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 453758 0.63% 97.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 427812 0.59% 97.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1612139 2.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 73891362 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50689891 # Number of instructions committed -system.cpu0.commit.committedOps 50689891 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 72348675 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49720528 # Number of instructions committed +system.cpu0.commit.committedOps 49720528 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13626145 # Number of memory references committed -system.cpu0.commit.loads 8064693 # Number of loads committed -system.cpu0.commit.membars 196335 # Number of memory barriers committed -system.cpu0.commit.branches 7657959 # Number of branches committed -system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46940801 # Number of committed integer instructions. -system.cpu0.commit.function_calls 646411 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1651677 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13302179 # Number of memory references committed +system.cpu0.commit.loads 7888682 # Number of loads committed +system.cpu0.commit.membars 189617 # Number of memory barriers committed +system.cpu0.commit.branches 7516247 # Number of branches committed +system.cpu0.commit.fp_insts 243820 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46057183 # Number of committed integer instructions. +system.cpu0.commit.function_calls 629253 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1612139 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129041756 # The number of ROB reads -system.cpu0.rob.rob_writes 115048006 # The number of ROB writes -system.cpu0.timesIdled 1051806 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26884368 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693778600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47771172 # Number of Instructions Simulated -system.cpu0.committedOps 47771172 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47771172 # Number of Instructions Simulated -system.cpu0.cpi 2.131618 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.131618 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.469127 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.469127 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66565111 # number of integer regfile reads -system.cpu0.int_regfile_writes 36349916 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127030 # number of floating regfile reads -system.cpu0.fp_regfile_writes 128672 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1690077 # number of misc regfile reads -system.cpu0.misc_regfile_writes 805917 # number of misc regfile writes +system.cpu0.rob.rob_reads 126376352 # The number of ROB reads +system.cpu0.rob.rob_writes 112693596 # The number of ROB writes +system.cpu0.timesIdled 1033507 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26786615 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3701289214 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46865102 # Number of Instructions Simulated +system.cpu0.committedOps 46865102 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 46865102 # Number of Instructions Simulated +system.cpu0.cpi 2.137160 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.137160 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.467911 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.467911 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65365755 # number of integer regfile reads +system.cpu0.int_regfile_writes 35683177 # number of integer regfile writes +system.cpu0.fp_regfile_reads 120752 # number of floating regfile reads +system.cpu0.fp_regfile_writes 122064 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1632145 # number of misc regfile reads +system.cpu0.misc_regfile_writes 781535 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,245 +932,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 862820 # number of replacements -system.cpu0.icache.tagsinuse 510.307143 # Cycle average of tags in use -system.cpu0.icache.total_refs 6727960 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 863332 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.793016 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.307143 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996694 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996694 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6727960 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6727960 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6727960 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6727960 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6727960 # number of overall hits -system.cpu0.icache.overall_hits::total 6727960 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 907351 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 907351 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 907351 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 907351 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 907351 # number of overall misses -system.cpu0.icache.overall_misses::total 907351 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12784635489 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12784635489 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12784635489 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12784635489 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12784635489 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12784635489 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7635311 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7635311 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7635311 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7635311 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7635311 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7635311 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118836 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118836 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118836 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118836 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118836 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118836 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14090.066015 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14090.066015 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14090.066015 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14090.066015 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5023 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 178 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.219101 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.replacements 828572 # number of replacements +system.cpu0.icache.tagsinuse 510.309366 # Cycle average of tags in use +system.cpu0.icache.total_refs 6631345 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 829084 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.998399 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20510250000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.309366 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996698 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996698 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6631345 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6631345 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6631345 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6631345 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6631345 # number of overall hits +system.cpu0.icache.overall_hits::total 6631345 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 870628 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 870628 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 870628 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 870628 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 870628 # number of overall misses +system.cpu0.icache.overall_misses::total 870628 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12335909994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12335909994 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12335909994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12335909994 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12335909994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12335909994 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7501973 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7501973 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7501973 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7501973 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7501973 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7501973 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116053 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116053 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116053 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116053 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116053 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116053 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14168.979167 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14168.979167 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14168.979167 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14168.979167 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2773 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1246 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.124138 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 623 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43874 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43874 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43874 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43874 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43874 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43874 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863477 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 863477 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 863477 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 863477 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 863477 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 863477 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10532261990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10532261990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10532261990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10532261990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10532261990 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10532261990 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113090 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113090 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113090 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12197.501485 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12197.501485 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12197.501485 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41361 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 41361 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41361 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 41361 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41361 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 41361 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 829267 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 829267 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 829267 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 829267 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 829267 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 829267 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10145672495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10145672495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10145672495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10145672495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10145672495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10145672495 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110540 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.110540 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.110540 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.506492 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1272509 # number of replacements -system.cpu0.dcache.tagsinuse 505.757504 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10329025 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1273021 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.113790 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.757504 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987808 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987808 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6350853 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6350853 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3621976 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3621976 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160250 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160250 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184435 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 184435 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9972829 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9972829 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9972829 # number of overall hits -system.cpu0.dcache.overall_hits::total 9972829 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1585015 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1585015 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1737486 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1737486 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2991 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2991 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3322501 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3322501 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3322501 # number of overall misses -system.cpu0.dcache.overall_misses::total 3322501 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34267378500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34267378500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66512674680 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 66512674680 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293615500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 293615500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21928500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 21928500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 100780053180 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 100780053180 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 100780053180 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 100780053180 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935868 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7935868 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359462 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5359462 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180668 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 180668 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187426 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187426 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13295330 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13295330 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13295330 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13295330 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199728 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199728 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324190 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324190 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113014 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113014 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015958 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015958 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249900 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249900 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249900 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249900 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21619.592559 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21619.592559 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38280.984526 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38280.984526 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14380.228230 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14380.228230 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7331.494483 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7331.494483 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30332.587764 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30332.587764 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30332.587764 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30332.587764 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2151725 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2274 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48206 # number of cycles access was blocked +system.cpu0.dcache.replacements 1248443 # number of replacements +system.cpu0.dcache.tagsinuse 505.648747 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10075338 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1248955 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.067014 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.648747 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987595 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987595 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6210455 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6210455 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3519332 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3519332 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154524 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 154524 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 177828 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 177828 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9729787 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9729787 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9729787 # number of overall hits +system.cpu0.dcache.overall_hits::total 9729787 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1542913 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1542913 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1697969 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1697969 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19729 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19729 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3731 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3731 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3240882 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3240882 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3240882 # number of overall misses +system.cpu0.dcache.overall_misses::total 3240882 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 33525948000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 33525948000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65021398230 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 65021398230 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 277810500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 277810500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 27308500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 27308500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 98547346230 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 98547346230 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 98547346230 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 98547346230 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7753368 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7753368 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5217301 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5217301 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 174253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 174253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181559 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 181559 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12970669 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12970669 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12970669 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12970669 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198999 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.198999 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.325450 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.325450 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113220 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113220 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.020550 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.020550 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249862 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249862 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249862 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249862 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21728.994441 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21728.994441 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.630938 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.630938 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14081.326981 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14081.326981 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7319.351380 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7319.351380 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30407.569986 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30407.569986 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2105320 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1192 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 47301 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.636041 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 324.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.508996 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 170.285714 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 748436 # number of writebacks -system.cpu0.dcache.writebacks::total 748436 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585810 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 585810 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465270 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1465270 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4533 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4533 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2051080 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2051080 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2051080 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2051080 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999205 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 999205 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272216 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272216 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15885 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15885 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2991 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2991 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271421 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1271421 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271421 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1271421 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21496696000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21496696000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9690926222 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9690926222 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183269000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183269000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15946500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15946500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31187622222 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31187622222 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31187622222 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31187622222 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1452303000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1452303000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128092999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128092999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3580395999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3580395999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125910 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125910 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087924 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087924 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015958 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015958 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095629 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095629 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095629 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095629 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21513.799471 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21513.799471 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35600.134533 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35600.134533 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.236387 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.236387 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5331.494483 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5331.494483 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24529.736588 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24529.736588 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24529.736588 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24529.736588 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 729881 # number of writebacks +system.cpu0.dcache.writebacks::total 729881 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558235 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 558235 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432207 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1432207 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4308 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4308 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990442 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1990442 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990442 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1990442 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984678 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 984678 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265762 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 265762 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15421 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15421 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3731 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3731 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250440 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1250440 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250440 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1250440 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21285796500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21285796500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9471560262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9471560262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170594000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170594000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19846500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19846500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30757356762 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30757356762 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30757356762 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30757356762 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454223000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454223000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2157391999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2157391999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3611614999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3611614999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050939 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050939 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020550 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020550 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096405 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096405 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21617.012363 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21617.012363 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35639.257162 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35639.257162 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.447312 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.447312 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5319.351380 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5319.351380 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1178,35 +1178,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2647984 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2186587 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 77884 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1531761 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 883024 # Number of BTB hits +system.cpu1.branchPred.lookups 2951549 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2437718 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 83271 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1841355 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 993285 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.647636 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 183996 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8305 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 53.943156 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 204052 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 9178 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1962214 # DTB read hits -system.cpu1.dtb.read_misses 10693 # DTB read misses +system.cpu1.dtb.read_hits 2175312 # DTB read hits +system.cpu1.dtb.read_misses 10933 # DTB read misses system.cpu1.dtb.read_acv 25 # DTB read access violations -system.cpu1.dtb.read_accesses 324562 # DTB read accesses -system.cpu1.dtb.write_hits 1265832 # DTB write hits -system.cpu1.dtb.write_misses 2093 # DTB write misses -system.cpu1.dtb.write_acv 66 # DTB write access violations -system.cpu1.dtb.write_accesses 133005 # DTB write accesses -system.cpu1.dtb.data_hits 3228046 # DTB hits -system.cpu1.dtb.data_misses 12786 # DTB misses -system.cpu1.dtb.data_acv 91 # DTB access violations -system.cpu1.dtb.data_accesses 457567 # DTB accesses -system.cpu1.itb.fetch_hits 437198 # ITB hits -system.cpu1.itb.fetch_misses 6975 # ITB misses -system.cpu1.itb.fetch_acv 228 # ITB acv -system.cpu1.itb.fetch_accesses 444173 # ITB accesses +system.cpu1.dtb.read_accesses 324345 # DTB read accesses +system.cpu1.dtb.write_hits 1433020 # DTB write hits +system.cpu1.dtb.write_misses 2283 # DTB write misses +system.cpu1.dtb.write_acv 64 # DTB write access violations +system.cpu1.dtb.write_accesses 133154 # DTB write accesses +system.cpu1.dtb.data_hits 3608332 # DTB hits +system.cpu1.dtb.data_misses 13216 # DTB misses +system.cpu1.dtb.data_acv 89 # DTB access violations +system.cpu1.dtb.data_accesses 457499 # DTB accesses +system.cpu1.itb.fetch_hits 457840 # ITB hits +system.cpu1.itb.fetch_misses 7553 # ITB misses +system.cpu1.itb.fetch_acv 250 # ITB acv +system.cpu1.itb.fetch_accesses 465393 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1219,508 +1219,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16140506 # number of cpu cycles simulated +system.cpu1.numCycles 18134862 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6118318 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12482084 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2647984 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1067020 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2239129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 408271 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6344159 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65784 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 57491 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1512128 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 52849 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15112669 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.825935 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.199937 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7058023 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13901788 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2951549 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1197337 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2488361 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 434606 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 7030666 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 27606 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 66549 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 53385 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1664870 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 56635 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 17000314 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.817737 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.192147 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12873540 85.18% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 143819 0.95% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 241770 1.60% 87.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 180451 1.19% 88.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 309857 2.05% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 119919 0.79% 91.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 135082 0.89% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 201991 1.34% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 906240 6.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 14511953 85.36% 85.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 164183 0.97% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 263479 1.55% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 196070 1.15% 89.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 340293 2.00% 91.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 131013 0.77% 91.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 146759 0.86% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 246866 1.45% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 999698 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15112669 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164058 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.773339 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6050197 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6601549 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2093593 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 113312 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 254017 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 116024 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7481 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12238533 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22436 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 254017 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6259861 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 497059 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5456265 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1994881 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 650584 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11345893 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 56627 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 159750 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7468114 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13547421 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13404114 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 143307 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6384399 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1083715 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 455985 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 44016 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2004753 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2075172 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1340696 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 190596 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 106471 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9962736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 502412 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9694977 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29943 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1444595 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 720781 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 360981 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15112669 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.641513 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.316207 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 17000314 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.162756 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.766578 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6933279 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7344422 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2325932 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 129039 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 267641 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 130064 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8172 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 13645823 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 24424 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 267641 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7167565 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 532442 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6090489 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2219281 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 722894 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12655848 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 62249 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 176645 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 8292237 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 15046679 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 14871812 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 174867 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7154777 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1137460 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 507049 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 51410 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2247669 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2296294 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1513309 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 213499 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 120116 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11096018 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 565266 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10828805 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 31328 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1532737 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 753738 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 401627 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 17000314 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.636977 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.310793 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10849099 71.79% 71.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1954888 12.94% 84.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 839816 5.56% 90.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 558366 3.69% 93.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 473326 3.13% 97.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 218082 1.44% 98.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 140204 0.93% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 70683 0.47% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8205 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 12224627 71.91% 71.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2204627 12.97% 84.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 929274 5.47% 90.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 621491 3.66% 94.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 537457 3.16% 97.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 242471 1.43% 98.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 153482 0.90% 99.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 76998 0.45% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 9887 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15112669 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 17000314 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3691 1.86% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 106885 53.95% 55.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 87531 44.18% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3882 1.79% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 115382 53.28% 55.07% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 97306 44.93% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6046898 62.37% 62.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16423 0.17% 62.58% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2053041 21.18% 83.88% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1289229 13.30% 97.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 273248 2.82% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6757278 62.40% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17931 0.17% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2277505 21.03% 83.75% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1457876 13.46% 97.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 301445 2.78% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9694977 # Type of FU issued -system.cpu1.iq.rate 0.600661 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 198107 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020434 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 34523477 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11810363 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9424990 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 207196 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 101110 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 98065 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9781516 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 108042 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94596 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10828805 # Type of FU issued +system.cpu1.iq.rate 0.597126 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 216570 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019999 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 38654254 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 13073033 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10523817 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 251568 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 122847 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 119196 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10910865 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 130984 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 103558 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 286791 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 870 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1822 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 126158 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 299992 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 506 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1941 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 130288 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 10101 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 384 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 9585 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 254017 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 327186 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 41525 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10980256 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 148232 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2075172 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1340696 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 454941 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 34335 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2140 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1822 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 35734 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 100242 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 135976 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9604840 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1980291 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 90137 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 267641 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 350754 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 52140 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 12262013 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 164906 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2296294 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1513309 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 509197 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 44334 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2198 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1941 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 37737 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 111746 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 149483 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10726014 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2194881 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 102791 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 515108 # number of nop insts executed -system.cpu1.iew.exec_refs 3254225 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1434575 # Number of branches executed -system.cpu1.iew.exec_stores 1273934 # Number of stores executed -system.cpu1.iew.exec_rate 0.595077 # Inst execution rate -system.cpu1.iew.wb_sent 9552134 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9523055 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4457844 # num instructions producing a value -system.cpu1.iew.wb_consumers 6254214 # num instructions consuming a value +system.cpu1.iew.exec_nop 600729 # number of nop insts executed +system.cpu1.iew.exec_refs 3637088 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1609931 # Number of branches executed +system.cpu1.iew.exec_stores 1442207 # Number of stores executed +system.cpu1.iew.exec_rate 0.591458 # Inst execution rate +system.cpu1.iew.wb_sent 10671299 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 10643013 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4954529 # num instructions producing a value +system.cpu1.iew.wb_consumers 6965334 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.590010 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712774 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.586881 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.711312 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1499365 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 141431 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 128632 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14858652 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.633306 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577285 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1577214 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 163639 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 139875 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16732673 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633048 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.579888 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11337498 76.30% 76.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1644581 11.07% 87.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 614314 4.13% 91.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 371520 2.50% 94.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 264064 1.78% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 106187 0.71% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 110282 0.74% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 108223 0.73% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 301983 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12788613 76.43% 76.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1829501 10.93% 87.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 688548 4.11% 91.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 419965 2.51% 93.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 300741 1.80% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 117837 0.70% 96.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 119533 0.71% 97.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 126738 0.76% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 341197 2.04% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14858652 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9410077 # Number of instructions committed -system.cpu1.commit.committedOps 9410077 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16732673 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10592581 # Number of instructions committed +system.cpu1.commit.committedOps 10592581 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3002919 # Number of memory references committed -system.cpu1.commit.loads 1788381 # Number of loads committed -system.cpu1.commit.membars 45067 # Number of memory barriers committed -system.cpu1.commit.branches 1346773 # Number of branches committed -system.cpu1.commit.fp_insts 96765 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8720568 # Number of committed integer instructions. -system.cpu1.commit.function_calls 150616 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 301983 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3379323 # Number of memory references committed +system.cpu1.commit.loads 1996302 # Number of loads committed +system.cpu1.commit.membars 53397 # Number of memory barriers committed +system.cpu1.commit.branches 1516852 # Number of branches committed +system.cpu1.commit.fp_insts 117937 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9798554 # Number of committed integer instructions. +system.cpu1.commit.function_calls 169964 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 341197 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25374737 # The number of ROB reads -system.cpu1.rob.rob_writes 22071443 # The number of ROB writes -system.cpu1.timesIdled 132837 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1027837 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3778857265 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8955466 # Number of Instructions Simulated -system.cpu1.committedOps 8955466 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8955466 # Number of Instructions Simulated -system.cpu1.cpi 1.802308 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.802308 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.554844 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.554844 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12383422 # number of integer regfile reads -system.cpu1.int_regfile_writes 6777735 # number of integer regfile writes -system.cpu1.fp_regfile_reads 53544 # number of floating regfile reads -system.cpu1.fp_regfile_writes 53234 # number of floating regfile writes -system.cpu1.misc_regfile_reads 526951 # number of misc regfile reads -system.cpu1.misc_regfile_writes 221547 # number of misc regfile writes -system.cpu1.icache.replacements 226688 # number of replacements -system.cpu1.icache.tagsinuse 470.806939 # Cycle average of tags in use -system.cpu1.icache.total_refs 1276285 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 227200 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.617452 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874198606000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.806939 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919545 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919545 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1276285 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1276285 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1276285 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1276285 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1276285 # number of overall hits -system.cpu1.icache.overall_hits::total 1276285 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 235843 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 235843 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 235843 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 235843 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 235843 # number of overall misses -system.cpu1.icache.overall_misses::total 235843 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3268518999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3268518999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3268518999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3268518999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3268518999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3268518999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1512128 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1512128 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1512128 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1512128 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1512128 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1512128 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155968 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.155968 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155968 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.155968 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155968 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.155968 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13858.876452 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13858.876452 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13858.876452 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13858.876452 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked +system.cpu1.rob.rob_reads 28468767 # The number of ROB reads +system.cpu1.rob.rob_writes 24605693 # The number of ROB writes +system.cpu1.timesIdled 153691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1134548 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782736336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 10061892 # Number of Instructions Simulated +system.cpu1.committedOps 10061892 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 10061892 # Number of Instructions Simulated +system.cpu1.cpi 1.802331 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.802331 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554837 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554837 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13798288 # number of integer regfile reads +system.cpu1.int_regfile_writes 7546279 # number of integer regfile writes +system.cpu1.fp_regfile_reads 63929 # number of floating regfile reads +system.cpu1.fp_regfile_writes 63981 # number of floating regfile writes +system.cpu1.misc_regfile_reads 608468 # number of misc regfile reads +system.cpu1.misc_regfile_writes 251084 # number of misc regfile writes +system.cpu1.icache.replacements 263438 # number of replacements +system.cpu1.icache.tagsinuse 470.047000 # Cycle average of tags in use +system.cpu1.icache.total_refs 1391700 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 263950 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.272590 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1875178456000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.047000 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.918061 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.918061 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1391700 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1391700 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1391700 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1391700 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1391700 # number of overall hits +system.cpu1.icache.overall_hits::total 1391700 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 273170 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 273170 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 273170 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 273170 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 273170 # number of overall misses +system.cpu1.icache.overall_misses::total 273170 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3762343999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3762343999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3762343999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3762343999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3762343999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3762343999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1664870 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1664870 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1664870 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1664870 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1664870 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1664870 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164079 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.164079 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164079 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.164079 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.164079 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.164079 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13772.903317 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13772.903317 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13772.903317 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13772.903317 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.153846 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 42.857143 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8582 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8582 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8582 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8582 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8582 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8582 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 227261 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 227261 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 227261 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 227261 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 227261 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 227261 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711595499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711595499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711595499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2711595499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711595499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2711595499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150292 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.150292 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150292 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3130972999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3130972999 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3130972999 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158586 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.158586 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.158586 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.623233 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 108752 # number of replacements -system.cpu1.dcache.tagsinuse 491.542258 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2641634 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 109154 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.200982 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39074075000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.542258 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.960043 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.960043 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1618348 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1618348 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 952576 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 952576 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33975 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 33975 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 32610 # 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number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35757 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3000198 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3000198 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3000198 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3000198 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114460 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.114460 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187687 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187687 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137252 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137252 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088011 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088011 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143082 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.143082 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143082 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.143082 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15183.144580 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15183.144580 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34273.114714 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34273.114714 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10453.191489 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10453.191489 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7198.125199 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7198.125199 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24970.848882 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24970.848882 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24970.848882 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24970.848882 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 239004 # number of cycles access was blocked +system.cpu1.dcache.replacements 126485 # number of replacements +system.cpu1.dcache.tagsinuse 490.826755 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2951833 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 126890 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 23.262929 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 37142562000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 490.826755 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.958646 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.958646 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1783497 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1783497 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1082553 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1082553 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 39938 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 39938 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 38621 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 38621 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2866050 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2866050 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2866050 # number of overall hits +system.cpu1.dcache.overall_hits::total 2866050 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 242860 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 242860 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 251463 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 251463 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 6629 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6629 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3956 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3956 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 494323 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 494323 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 494323 # number of overall misses +system.cpu1.dcache.overall_misses::total 494323 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3676780500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3676780500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8111413586 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8111413586 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 67692000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 67692000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 29045500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 29045500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11788194086 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11788194086 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11788194086 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11788194086 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2026357 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2026357 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1334016 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1334016 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46567 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46567 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 42577 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 42577 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3360373 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3360373 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3360373 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3360373 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.119851 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.119851 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188501 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.188501 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142354 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142354 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092914 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092914 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.147104 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.147104 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.147104 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.147104 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15139.506300 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15139.506300 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32256.887041 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32256.887041 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10211.494946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10211.494946 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.138524 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.138524 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23847.148698 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23847.148698 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 244071 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3894 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4071 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.377504 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 59.953574 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 72044 # number of writebacks -system.cpu1.dcache.writebacks::total 72044 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129793 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 129793 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180819 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 180819 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 604 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 604 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 310612 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 310612 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 310612 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 310612 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79386 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 79386 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39276 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 39276 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4801 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4801 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3147 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3147 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 118662 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 118662 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 118662 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 118662 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 971821000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 971821000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1116428485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1116428485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39070500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39070500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16358500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16358500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088249485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2088249485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088249485 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2088249485 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30977500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30977500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647178500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647178500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678156000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678156000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043439 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043439 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033493 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033493 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121915 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121915 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088011 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088011 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039551 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039551 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039551 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039551 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.717683 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12241.717683 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28425.208397 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28425.208397 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8137.992085 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8137.992085 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5198.125199 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5198.125199 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17598.300088 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17598.300088 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17598.300088 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17598.300088 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 84853 # number of writebacks +system.cpu1.dcache.writebacks::total 84853 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150731 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 150731 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205632 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 205632 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 643 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 643 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 356363 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 356363 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 356363 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 356363 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92129 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 92129 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45831 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 45831 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5986 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5986 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3956 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3956 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 137960 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 137960 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 137960 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 137960 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1123159500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1123159500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1210930487 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1210930487 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47601500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47601500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21133500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21133500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2334089987 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2334089987 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2334089987 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2334089987 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30974500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30974500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675233500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675233500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045465 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045465 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034356 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034356 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128546 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128546 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092914 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092914 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.041055 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.041055 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12191.161306 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12191.161306 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26421.646637 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26421.646637 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7952.138323 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.138323 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.138524 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.138524 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1729,32 +1729,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6549 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 181634 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64148 40.44% 40.44% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.21% 41.74% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92227 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158624 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63158 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.50% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 62964 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128371 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862438042500 98.14% 98.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62559000 0.00% 98.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567042000 0.03% 98.17% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 94587500 0.00% 98.17% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34644439500 1.83% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897806670500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984567 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6612 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 175930 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 61741 40.36% 40.36% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 135 0.09% 40.45% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1928 1.26% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 255 0.17% 41.87% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 88920 58.13% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 152979 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 60877 49.17% 49.17% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 135 0.11% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.56% 50.83% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 255 0.21% 51.04% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 60624 48.96% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 123819 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865666624000 98.16% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63262500 0.00% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 564029000 0.03% 98.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 124022000 0.01% 98.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34308226500 1.81% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900726164000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.986006 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682707 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809279 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681781 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809386 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1786,60 +1786,60 @@ system.cpu0.kern.syscall::144 1 0.50% 99.01% # nu system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 297 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151888 91.03% 93.33% # number of callpals executed -system.cpu0.kern.callpal::rdps 6165 3.69% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4486 2.69% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 166848 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches +system.cpu0.kern.callpal::wripir 359 0.22% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.23% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3342 2.07% 2.30% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.33% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed +system.cpu0.kern.callpal::swpipl 146235 90.79% 93.12% # number of callpals executed +system.cpu0.kern.callpal::rdps 6169 3.83% 96.95% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.95% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.95% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 96.96% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu0.kern.callpal::rti 4427 2.75% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.21% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 161075 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6928 # number of protection mode switches system.cpu0.kern.mode_switch::user 1259 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1258 system.cpu0.kern.mode_good::user 1259 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.180023 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181582 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.305202 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895901736500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1904926000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307439 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1898815475500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1910680500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3470 # number of times the context was actually changed +system.cpu0.kern.swap_context 3343 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2462 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 58111 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18212 36.94% 36.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 3.90% 40.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28864 58.55% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49296 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17825 47.44% 47.44% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 5.12% 52.56% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17528 46.65% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37573 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872585348000 98.69% 98.69% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531683000 0.03% 98.71% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 134630500 0.01% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24248440000 1.28% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897500101500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978750 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2522 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 64668 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 20885 37.61% 37.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1927 3.47% 41.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 359 0.65% 41.72% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 32365 58.28% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 55536 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 20372 47.74% 47.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1927 4.52% 52.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 359 0.84% 53.10% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 20014 46.90% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 42672 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1875014442000 98.66% 98.66% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532441000 0.03% 98.69% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 162321000 0.01% 98.70% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24727641000 1.30% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900436845000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975437 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.607262 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.762192 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.618384 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.768366 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1863,36 +1863,36 @@ system.cpu1.kern.syscall::132 3 2.42% 99.19% # nu system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 194 0.38% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43980 85.81% 88.44% # number of callpals executed -system.cpu1.kern.callpal::rdps 2592 5.06% 93.50% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed -system.cpu1.kern.callpal::rti 3095 6.04% 99.56% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 255 0.44% 0.44% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1393 2.41% 2.86% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.87% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.88% # number of callpals executed +system.cpu1.kern.callpal::swpipl 49964 86.52% 89.41% # number of callpals executed +system.cpu1.kern.callpal::rdps 2595 4.49% 93.90% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.90% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.91% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.91% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.91% # number of callpals executed +system.cpu1.kern.callpal::rti 3286 5.69% 99.61% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.32% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 51254 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches -system.cpu1.kern.mode_switch::user 489 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 710 -system.cpu1.kern.mode_good::user 489 -system.cpu1.kern.mode_good::idle 221 -system.cpu1.kern.mode_switch_good::kernel 0.498596 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 57746 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1619 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2559 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 771 +system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_good::idle 283 +system.cpu1.kern.mode_switch_good::kernel 0.476220 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090722 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.326512 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4824136000 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 831285000 0.04% 0.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1891834463500 99.70% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1141 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.110590 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.330476 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5766448000 0.30% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 831527500 0.04% 0.35% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893827791500 99.65% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1394 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index a041cd935..46893c808 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -12,15 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/projects/pd/randd/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/projects/pd/randd/dist/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -520,7 +520,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -540,7 +540,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -615,6 +615,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true @@ -646,7 +647,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 80fb6a8f2..e4e5656be 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 10:45:16 -gem5 started Feb 13 2013 13:46:08 -gem5 executing on u200540-lin +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 23:18:16 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1854310111000 because m5_exit instruction encountered +Exiting @ tick 1854315933000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 7557c7dd3..f7cc8bd0e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854310 # Number of seconds simulated -sim_ticks 1854310449000 # Number of ticks simulated -final_tick 1854310449000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854316 # Number of seconds simulated +sim_ticks 1854315933000 # Number of ticks simulated +final_tick 1854315933000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91767 # Simulator instruction rate (inst/s) -host_op_rate 91767 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3212612251 # Simulator tick rate (ticks/s) -host_mem_usage 333588 # Number of bytes of host memory used -host_seconds 577.20 # Real time elapsed on the host -sim_insts 52967561 # Number of instructions simulated -sim_ops 52967561 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875392 # Number of bytes read from this memory +host_inst_rate 49330 # Simulator instruction rate (inst/s) +host_op_rate 49330 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1727408560 # Simulator tick rate (ticks/s) +host_mem_usage 351576 # Number of bytes of host memory used +host_seconds 1073.47 # Real time elapsed on the host +sim_insts 52953842 # Number of instructions simulated +sim_ops 52953842 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28492160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7502272 # Number of bytes written to this memory -system.physmem.bytes_written::total 7502272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388678 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7502848 # Number of bytes written to this memory +system.physmem.bytes_written::total 7502848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445190 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117223 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117223 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13414901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430371 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15365367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520094 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520094 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13414901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19411222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445190 # Total number of read requests seen -system.physmem.writeReqs 117223 # Total number of write requests seen -system.physmem.cpureqs 562598 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28492160 # Total number of bytes read from memory -system.physmem.bytesWritten 7502272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28492160 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7502272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27959 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27788 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28082 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7347 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7509 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7384 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7205 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis +system.physmem.num_reads::total 445253 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117232 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117232 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13416864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15367496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4046154 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4046154 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4046154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13416864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19413650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445253 # Total number of read requests seen +system.physmem.writeReqs 117232 # Total number of write requests seen +system.physmem.cpureqs 562681 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28496192 # Total number of bytes read from memory +system.physmem.bytesWritten 7502848 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28496192 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7502848 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 180 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27757 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27571 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27335 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28084 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27816 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27970 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27741 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27965 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27782 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27722 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7549 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7292 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6981 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7370 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7331 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7642 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7197 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854305000000 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854310455000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445190 # Categorize read packet sizes +system.physmem.readPktSize::6 445253 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117223 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117232 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -128,46 +128,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5079 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see -system.physmem.totQLat 7465727500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15177783750 # Sum of mem lat for all requests -system.physmem.totBusLat 2225655000 # Total cycles spent in databus access -system.physmem.totBankLat 5486401250 # Total cycles spent in bank access -system.physmem.avgQLat 16771.98 # Average queueing delay per request -system.physmem.avgBankLat 12325.36 # Average bank access latency per request +system.physmem.wrQLenPdf::15 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see +system.physmem.totQLat 7494847250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15211767250 # Sum of mem lat for all requests +system.physmem.totBusLat 2225940000 # Total cycles spent in databus access +system.physmem.totBankLat 5490980000 # Total cycles spent in bank access +system.physmem.avgQLat 16835.24 # Average queueing delay per request +system.physmem.avgBankLat 12334.07 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34097.34 # Average memory access latency +system.physmem.avgMemAccLat 34169.31 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -175,21 +175,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.50 # Average write queue length over time -system.physmem.readRowHits 417731 # Number of row buffer hits during reads -system.physmem.writeRowHits 91366 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes -system.physmem.avgGap 3297052.17 # Average gap between requests +system.physmem.avgWrQLen 12.10 # Average write queue length over time +system.physmem.readRowHits 417708 # Number of row buffer hits during reads +system.physmem.writeRowHits 91270 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.85 # Row buffer hit rate for writes +system.physmem.avgGap 3296639.83 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265060 # Cycle average of tags in use +system.iocache.tagsinuse 1.265086 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265060 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704475467000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265086 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079068 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079068 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10634247416 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10634247416 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10655175414 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10655175414 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10655175414 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10655175414 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10643328423 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10643328423 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10664256421 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10664256421 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10664256421 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10664256421 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255926.247016 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255926.247016 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255366.696561 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255366.696561 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255366.696561 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255366.696561 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 283342 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256144.792621 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256144.792621 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255584.336034 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255584.336034 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255584.336034 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255584.336034 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27068 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27214 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.467785 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.438010 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472247190 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8472247190 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8484178439 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8484178439 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8484178439 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8484178439 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8481334185 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8481334185 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8493265434 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8493265434 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8493265434 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8493265434 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203895.051742 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203895.051742 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203335.612678 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203335.612678 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203335.612678 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203335.612678 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204113.741456 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204113.741456 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203553.395662 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203553.395662 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203553.395662 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203553.395662 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -285,35 +285,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13849744 # Number of BP lookups -system.cpu.branchPred.condPredicted 11622401 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399564 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9420297 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5813323 # Number of BTB hits +system.cpu.branchPred.lookups 13854129 # Number of BP lookups +system.cpu.branchPred.condPredicted 11621858 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 400402 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9160821 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5815827 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.710613 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 901783 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38632 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.485871 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906747 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38946 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9912266 # DTB read hits -system.cpu.dtb.read_misses 41544 # DTB read misses -system.cpu.dtb.read_acv 542 # DTB read access violations -system.cpu.dtb.read_accesses 940163 # DTB read accesses -system.cpu.dtb.write_hits 6601788 # DTB write hits -system.cpu.dtb.write_misses 10570 # DTB write misses -system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 337668 # DTB write accesses -system.cpu.dtb.data_hits 16514054 # DTB hits -system.cpu.dtb.data_misses 52114 # DTB misses -system.cpu.dtb.data_acv 952 # DTB access violations -system.cpu.dtb.data_accesses 1277831 # DTB accesses -system.cpu.itb.fetch_hits 1306011 # ITB hits -system.cpu.itb.fetch_misses 36868 # ITB misses -system.cpu.itb.fetch_acv 1103 # ITB acv -system.cpu.itb.fetch_accesses 1342879 # ITB accesses +system.cpu.dtb.read_hits 9920210 # DTB read hits +system.cpu.dtb.read_misses 41076 # DTB read misses +system.cpu.dtb.read_acv 544 # DTB read access violations +system.cpu.dtb.read_accesses 941527 # DTB read accesses +system.cpu.dtb.write_hits 6593814 # DTB write hits +system.cpu.dtb.write_misses 10775 # DTB write misses +system.cpu.dtb.write_acv 404 # DTB write access violations +system.cpu.dtb.write_accesses 338229 # DTB write accesses +system.cpu.dtb.data_hits 16514024 # DTB hits +system.cpu.dtb.data_misses 51851 # DTB misses +system.cpu.dtb.data_acv 948 # DTB access violations +system.cpu.dtb.data_accesses 1279756 # DTB accesses +system.cpu.itb.fetch_hits 1305070 # ITB hits +system.cpu.itb.fetch_misses 36981 # ITB misses +system.cpu.itb.fetch_acv 1089 # ITB acv +system.cpu.itb.fetch_accesses 1342051 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,134 +326,134 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108629038 # number of cpu cycles simulated +system.cpu.numCycles 108723981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28026689 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70680176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13849744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6715106 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13246427 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1984359 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37388108 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32353 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254081 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 294447 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 699 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8549154 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266665 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80527554 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.221537 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28071835 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70691782 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13854129 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6722574 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13248795 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1991444 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37396273 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32851 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253900 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 295773 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 814 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8551942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266251 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80590196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.220882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67281127 83.55% 83.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 855303 1.06% 84.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1700571 2.11% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 822573 1.02% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2750497 3.42% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 561265 0.70% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645561 0.80% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1010923 1.26% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4899734 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67341401 83.56% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 854251 1.06% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1698632 2.11% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 828031 1.03% 87.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2750245 3.41% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 562298 0.70% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 643304 0.80% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1012392 1.26% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4899642 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80527554 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127496 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.650656 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29153725 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37057832 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12110647 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962931 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1242418 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586230 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42729 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69379302 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129899 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1242418 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30276016 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13626490 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19778343 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11345486 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4258799 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65628358 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6970 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 508418 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1479478 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43831634 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79654682 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79176161 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 478521 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38170118 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5661508 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682525 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240085 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12113982 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10427074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6890989 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1312659 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 851378 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58169067 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2051551 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56810875 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 88738 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6892578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503311 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1390624 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80527554 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.366898 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80590196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127425 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650195 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29205934 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37061149 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12112258 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963051 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1247803 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585584 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42566 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69386312 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128816 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1247803 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30327018 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13624252 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19779589 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11347768 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4263764 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65637148 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6817 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 509709 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1485643 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43822331 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79670452 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79191261 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479191 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38158982 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5663341 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1681975 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239504 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12131366 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10436836 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6902083 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1326454 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 859310 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58185317 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050283 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56802944 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 107134 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6922426 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3549333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389358 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80590196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.704837 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365985 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55885936 69.40% 69.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10804988 13.42% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5163321 6.41% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3374568 4.19% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2652291 3.29% 96.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461239 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 754842 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331822 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 98547 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55946315 69.42% 69.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10805415 13.41% 82.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5162410 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3384715 4.20% 93.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2645600 3.28% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461420 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 757318 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 330868 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96135 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80527554 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80590196 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91181 11.49% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373750 47.11% 58.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 328508 41.40% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91816 11.60% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373288 47.16% 58.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326368 41.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38738406 68.19% 68.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38732288 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61693 0.11% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued @@ -481,114 +481,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10344574 18.21% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6680654 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949005 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10350848 18.22% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6672590 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948996 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56810875 # Type of FU issued -system.cpu.iq.rate 0.522981 # Inst issue rate -system.cpu.iq.fu_busy_cnt 793439 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013966 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194338715 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66791274 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55577661 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692765 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 335658 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327829 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57234972 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 601138 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56802944 # Type of FU issued +system.cpu.iq.rate 0.522451 # Inst issue rate +system.cpu.iq.fu_busy_cnt 791472 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013934 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194402098 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66835363 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55566146 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692591 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327919 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57225685 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 601434 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1337046 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 514312 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1348949 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4999 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14153 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 526604 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17961 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 173725 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17963 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 174400 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1242418 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9954083 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684701 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63749782 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 676077 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10427074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6890989 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1807007 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18311 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 203273 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412234 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 615507 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56340822 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9981988 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 470052 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1247803 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9948703 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63760053 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 677795 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10436836 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6902083 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805728 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512612 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18477 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14153 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 203761 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412011 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615772 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56335729 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9989502 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467214 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3529164 # number of nop insts executed -system.cpu.iew.exec_refs 16609586 # number of memory reference insts executed -system.cpu.iew.exec_branches 8925674 # Number of branches executed -system.cpu.iew.exec_stores 6627598 # Number of stores executed -system.cpu.iew.exec_rate 0.518653 # Inst execution rate -system.cpu.iew.wb_sent 56019458 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55905490 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27772636 # num instructions producing a value -system.cpu.iew.wb_consumers 37602554 # num instructions consuming a value +system.cpu.iew.exec_nop 3524453 # number of nop insts executed +system.cpu.iew.exec_refs 16609334 # number of memory reference insts executed +system.cpu.iew.exec_branches 8926219 # Number of branches executed +system.cpu.iew.exec_stores 6619832 # Number of stores executed +system.cpu.iew.exec_rate 0.518154 # Inst execution rate +system.cpu.iew.wb_sent 56008573 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55894065 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27763400 # num instructions producing a value +system.cpu.iew.wb_consumers 37619407 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.514646 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738584 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514091 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738007 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7474791 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660927 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568232 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79285136 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.708301 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.637990 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7499464 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660925 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 569249 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79342393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.707610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.636795 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58523209 73.81% 73.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8600768 10.85% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4599944 5.80% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2533685 3.20% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1517149 1.91% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 606925 0.77% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 524667 0.66% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 525488 0.66% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1853301 2.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58576225 73.83% 73.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8604152 10.84% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4604262 5.80% 90.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2532350 3.19% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516866 1.91% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 607587 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 525202 0.66% 97.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 528895 0.67% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1846854 2.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79285136 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56157758 # Number of instructions committed -system.cpu.commit.committedOps 56157758 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79342393 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56143434 # Number of instructions committed +system.cpu.commit.committedOps 56143434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15466705 # Number of memory references committed -system.cpu.commit.loads 9090028 # Number of loads committed -system.cpu.commit.membars 226335 # Number of memory barriers committed -system.cpu.commit.branches 8438960 # Number of branches committed +system.cpu.commit.refs 15463366 # Number of memory references committed +system.cpu.commit.loads 9087887 # Number of loads committed +system.cpu.commit.membars 226338 # Number of memory barriers committed +system.cpu.commit.branches 8437404 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52008025 # Number of committed integer instructions. -system.cpu.commit.function_calls 740393 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1853301 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 51994306 # Number of committed integer instructions. +system.cpu.commit.function_calls 740223 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1846854 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140814788 # The number of ROB reads -system.cpu.rob.rob_writes 128509305 # The number of ROB writes -system.cpu.timesIdled 1177982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28101484 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599985419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52967561 # Number of Instructions Simulated -system.cpu.committedOps 52967561 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52967561 # Number of Instructions Simulated -system.cpu.cpi 2.050860 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.050860 # CPI: Total CPI of All Threads -system.cpu.ipc 0.487600 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.487600 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73882509 # number of integer regfile reads -system.cpu.int_regfile_writes 40314112 # number of integer regfile writes -system.cpu.fp_regfile_reads 165977 # number of floating regfile reads -system.cpu.fp_regfile_writes 167436 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987247 # number of misc regfile reads -system.cpu.misc_regfile_writes 938923 # number of misc regfile writes +system.cpu.rob.rob_reads 140888897 # The number of ROB reads +system.cpu.rob.rob_writes 128535372 # The number of ROB writes +system.cpu.timesIdled 1178030 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28133785 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599901445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52953842 # Number of Instructions Simulated +system.cpu.committedOps 52953842 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52953842 # Number of Instructions Simulated +system.cpu.cpi 2.053184 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.053184 # CPI: Total CPI of All Threads +system.cpu.ipc 0.487048 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.487048 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73863718 # number of integer regfile reads +system.cpu.int_regfile_writes 40309148 # number of integer regfile writes +system.cpu.fp_regfile_reads 166055 # number of floating regfile reads +system.cpu.fp_regfile_writes 167445 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987577 # number of misc regfile reads +system.cpu.misc_regfile_writes 938916 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -620,193 +620,193 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1008504 # number of replacements -system.cpu.icache.tagsinuse 510.288693 # Cycle average of tags in use -system.cpu.icache.total_refs 7484267 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1009012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.417421 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.288693 # Average occupied blocks per requestor +system.cpu.icache.replacements 1008056 # number of replacements +system.cpu.icache.tagsinuse 510.288662 # Cycle average of tags in use +system.cpu.icache.total_refs 7486559 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1008564 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.422989 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20267924000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.288662 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996658 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996658 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7484268 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7484268 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7484268 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7484268 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7484268 # number of overall hits -system.cpu.icache.overall_hits::total 7484268 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064885 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064885 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064885 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064885 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064885 # number of overall misses -system.cpu.icache.overall_misses::total 1064885 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14670837493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14670837493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14670837493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14670837493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14670837493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14670837493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8549153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8549153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8549153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8549153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8549153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8549153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124560 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124560 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124560 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124560 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124560 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124560 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.921915 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13776.921915 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.921915 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13776.921915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.921915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13776.921915 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5769 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1606 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.935294 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 803 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 7486560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7486560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7486560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7486560 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14692786493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14692786493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8551940 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8551940 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8551940 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8551940 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8551940 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8551940 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13791.122879 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13791.122879 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13791.122879 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13791.122879 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13791.122879 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13791.122879 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4755 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1956 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 32.793103 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 489 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55656 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55656 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55656 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55656 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55656 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55656 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009229 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009229 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009229 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009229 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009229 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009229 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12029446495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12029446495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12029446495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12029446495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12029446495 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6262852352 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6262852352 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 862398247 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14865162878 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15727561125 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 862398247 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14865162878 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15727561125 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333774000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333774000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882495000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882495000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216269000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216269000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014945 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248891 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136989 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.597015 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.597015 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277849 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167794 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014945 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277849 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167794 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57207.180564 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.571153 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32764.368900 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14238.400000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14238.400000 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53980.388764 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53980.388764 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56304.596151 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38110.121392 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38788.411743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56304.596151 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38110.121392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38788.411743 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54255.772680 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54255.772680 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57207.180564 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38191.303521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.335206 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57207.180564 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38191.303521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.335206 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -896,161 +896,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1400618 # number of replacements -system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use -system.cpu.dcache.total_refs 11803573 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401130 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.424324 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1400274 # number of replacements +system.cpu.dcache.tagsinuse 511.995157 # Cycle average of tags in use +system.cpu.dcache.total_refs 11811900 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1400786 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.432337 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21808000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995157 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7198104 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7198104 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203343 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203343 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186395 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186395 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7207099 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7207099 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203008 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203008 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186038 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186038 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11401447 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11401447 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11401447 # number of overall hits -system.cpu.dcache.overall_hits::total 11401447 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802656 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802656 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1943125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1943125 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22671 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22671 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3745781 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745781 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3745781 # number of overall misses -system.cpu.dcache.overall_misses::total 3745781 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33855022500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33855022500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64910918483 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64910918483 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306639500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306639500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 64000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 64000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 98765940983 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 98765940983 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 98765940983 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 98765940983 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9000760 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9000760 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6146468 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6146468 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209066 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209066 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15147228 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15147228 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15147228 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15147228 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200278 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316137 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316137 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108439 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108439 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247292 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247292 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247292 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247292 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18780.633965 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18780.633965 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33405.426045 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33405.426045 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13525.627454 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13525.627454 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26367.249175 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26367.249175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26367.249175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26367.249175 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2192171 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95789 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.885415 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked +system.cpu.dcache.demand_hits::cpu.data 11410107 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11410107 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11410107 # number of overall hits +system.cpu.dcache.overall_hits::total 11410107 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1800868 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1800868 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1942264 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1942264 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3743132 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3743132 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3743132 # number of overall misses +system.cpu.dcache.overall_misses::total 3743132 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33858803000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33858803000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 65085084522 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 65085084522 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304812500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 304812500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 37500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 37500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98943887522 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98943887522 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98943887522 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98943887522 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9007967 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9007967 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6145272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6145272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208781 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208781 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215507 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215507 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15153239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15153239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15153239 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15153239 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199919 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199919 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316058 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316058 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108932 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108932 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247019 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247019 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247019 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247019 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18801.379668 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18801.379668 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33509.906234 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33509.906234 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13402.475487 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13402.475487 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26433.448653 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26433.448653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26433.448653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26433.448653 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2202746 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 567 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95919 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.964647 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840363 # number of writebacks -system.cpu.dcache.writebacks::total 840363 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719064 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 719064 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642999 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642999 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5119 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5119 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2362063 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2362063 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2362063 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2362063 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083592 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083592 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300126 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300126 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17552 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17552 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383718 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383718 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383718 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383718 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21332679000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21332679000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9855100772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9855100772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200264000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200264000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 56000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187779772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31187779772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187779772 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31187779772 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423903500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423903500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997763498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997763498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421666998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421666998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048829 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048829 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091351 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091351 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091351 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091351 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19687.003042 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19687.003042 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32836.544558 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32836.544558 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11409.753874 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11409.753874 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22539.115464 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22539.115464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22539.115464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22539.115464 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840029 # number of writebacks +system.cpu.dcache.writebacks::total 840029 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717621 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717621 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642056 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642056 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5266 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5266 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2359677 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2359677 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2359677 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2359677 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083247 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083247 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300208 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300208 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17477 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17477 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383455 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383455 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383455 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383455 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21329073000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21329073000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9889442761 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9889442761 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199091500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199091500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31218515761 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31218515761 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31218515761 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31218515761 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423851000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423851000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997662998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997662998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421513998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421513998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083710 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083710 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091298 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091298 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091298 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091298 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19689.944214 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19689.944214 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32941.969438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32941.969438 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11391.628998 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11391.628998 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22565.617068 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22565.617068 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22565.617068 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22565.617068 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1059,28 +1059,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211000 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182231 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818337876500 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63843000 0.00% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 549015500 0.03% 98.09% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35358867000 1.91% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854309602000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1818345164500 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63914000 0.00% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 557987500 0.03% 98.09% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35348021500 1.91% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854315087500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815438 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1119,7 +1119,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175116 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1128,20 +1128,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191960 # number of callpals executed +system.cpu.kern.callpal::total 191959 # number of callpals executed system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326723 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394549 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29457658500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2706866000 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822145069500 98.27% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29469027500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2713167500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822132884500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index d353d9284..ad99994ae 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus phy boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/projects/pd/randd/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/projects/pd/randd/dist/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -581,7 +581,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -601,7 +601,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -698,6 +698,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true @@ -729,7 +730,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index c03321be6..9227d5948 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:29:38 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 23:27:13 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second @@ -18,204 +18,207 @@ info: Entering event queue @ 1000000000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 2000000000. Starting simulation... +info: Entering event queue @ 2000003000. Starting simulation... switching cpus -info: Entering event queue @ 2000001000. Starting simulation... +info: Entering event queue @ 2000005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3000001000. Starting simulation... -info: Entering event queue @ 3000043000. Starting simulation... +info: Entering event queue @ 3000005500. Starting simulation... switching cpus -info: Entering event queue @ 3000047500. Starting simulation... +info: Entering event queue @ 3000041000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4000047500. Starting simulation... +info: Entering event queue @ 4000041000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5000047500. Starting simulation... +info: Entering event queue @ 5000041000. Starting simulation... +info: Entering event queue @ 5000053000. Starting simulation... switching cpus -info: Entering event queue @ 5000048000. Starting simulation... +info: Entering event queue @ 5000056500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000048000. Starting simulation... -info: Entering event queue @ 7452589500. Starting simulation... -info: Entering event queue @ 7452657000. Starting simulation... +info: Entering event queue @ 6000056500. Starting simulation... +info: Entering event queue @ 7458944500. Starting simulation... +info: Entering event queue @ 7459012000. Starting simulation... switching cpus -info: Entering event queue @ 7452661500. Starting simulation... +info: Entering event queue @ 7459016500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 8452661500. Starting simulation... +info: Entering event queue @ 8459016500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 9452661500. Starting simulation... -info: Entering event queue @ 9452675500. Starting simulation... +info: Entering event queue @ 9459016500. Starting simulation... switching cpus -info: Entering event queue @ 9452679000. Starting simulation... +info: Entering event queue @ 9459024000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 10452679000. Starting simulation... +info: Entering event queue @ 10459024000. Starting simulation... switching cpus -info: Entering event queue @ 10452682000. Starting simulation... +info: Entering event queue @ 10459031500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 11452682000. Starting simulation... +info: Entering event queue @ 11459031500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 12452682000. Starting simulation... -info: Entering event queue @ 12452693500. Starting simulation... +info: Entering event queue @ 12459031500. Starting simulation... +info: Entering event queue @ 12459047000. Starting simulation... switching cpus -info: Entering event queue @ 12452696000. Starting simulation... +info: Entering event queue @ 12459242750. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 13452696000. Starting simulation... +info: Entering event queue @ 13459242750. Starting simulation... +info: Entering event queue @ 13459250250. Starting simulation... +info: Entering event queue @ 13459254000. Starting simulation... switching cpus -info: Entering event queue @ 13452709500. Starting simulation... +info: Entering event queue @ 13459258500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 14452709500. Starting simulation... +info: Entering event queue @ 14459258500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 15452709500. Starting simulation... -info: Entering event queue @ 15452713500. Starting simulation... +info: Entering event queue @ 15459258500. Starting simulation... switching cpus -info: Entering event queue @ 15452714500. Starting simulation... +info: Entering event queue @ 15459266000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 16452714500. Starting simulation... +info: Entering event queue @ 16459266000. Starting simulation... switching cpus -info: Entering event queue @ 16452717000. Starting simulation... +info: Entering event queue @ 16459273500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 17452717000. Starting simulation... +info: Entering event queue @ 17459273500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 18452717000. Starting simulation... -info: Entering event queue @ 18452728500. Starting simulation... +info: Entering event queue @ 18459273500. Starting simulation... +info: Entering event queue @ 18459284000. Starting simulation... switching cpus -info: Entering event queue @ 18452732000. Starting simulation... +info: Entering event queue @ 18459287500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 19452732000. Starting simulation... -info: Entering event queue @ 19452741000. Starting simulation... +info: Entering event queue @ 19459287500. Starting simulation... switching cpus -info: Entering event queue @ 19452745500. Starting simulation... +info: Entering event queue @ 19459295000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 20452745500. Starting simulation... +info: Entering event queue @ 20459295000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 21452745500. Starting simulation... +info: Entering event queue @ 21459295000. Starting simulation... switching cpus -info: Entering event queue @ 21452746000. Starting simulation... +info: Entering event queue @ 21459296000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 22452746000. Starting simulation... +info: Entering event queue @ 22459296000. Starting simulation... switching cpus -info: Entering event queue @ 22452748000. Starting simulation... +info: Entering event queue @ 22459303500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 23452748000. Starting simulation... +info: Entering event queue @ 23459303500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 24452748000. Starting simulation... +info: Entering event queue @ 24459303500. Starting simulation... switching cpus -info: Entering event queue @ 24452750000. Starting simulation... +info: Entering event queue @ 24459311000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 25452750000. Starting simulation... -info: Entering event queue @ 25452773000. Starting simulation... +info: Entering event queue @ 25459311000. Starting simulation... +info: Entering event queue @ 25459330000. Starting simulation... +info: Entering event queue @ 25459339500. Starting simulation... +info: Entering event queue @ 25459344000. Starting simulation... switching cpus -info: Entering event queue @ 25452778500. Starting simulation... +info: Entering event queue @ 25459345000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 26452778500. Starting simulation... +info: Entering event queue @ 26459345000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 27452778500. Starting simulation... -info: Entering event queue @ 27452782500. Starting simulation... +info: Entering event queue @ 27459345000. Starting simulation... +info: Entering event queue @ 27459352500. Starting simulation... switching cpus -info: Entering event queue @ 27452786000. Starting simulation... +info: Entering event queue @ 27459355500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 28452786000. Starting simulation... -info: Entering event queue @ 28452802500. Starting simulation... +info: Entering event queue @ 28459355500. Starting simulation... +info: Entering event queue @ 28459377000. Starting simulation... switching cpus -info: Entering event queue @ 28452808000. Starting simulation... +info: Entering event queue @ 28459573000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 29452808000. Starting simulation... +info: Entering event queue @ 29459573000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 30452808000. Starting simulation... +info: Entering event queue @ 30459573000. Starting simulation... switching cpus -info: Entering event queue @ 30452820500. Starting simulation... +info: Entering event queue @ 30459580500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 31452820500. Starting simulation... +info: Entering event queue @ 31459580500. Starting simulation... +info: Entering event queue @ 31459590000. Starting simulation... switching cpus -info: Entering event queue @ 31452823500. Starting simulation... +info: Entering event queue @ 31459594500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 32452823500. Starting simulation... +info: Entering event queue @ 32459594500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 33452823500. Starting simulation... +info: Entering event queue @ 33459594500. Starting simulation... switching cpus -info: Entering event queue @ 33452824500. Starting simulation... +info: Entering event queue @ 33459602000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 34452824500. Starting simulation... +info: Entering event queue @ 34459602000. Starting simulation... switching cpus -info: Entering event queue @ 34452827500. Starting simulation... +info: Entering event queue @ 34459605000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 35452827500. Starting simulation... +info: Entering event queue @ 35459605000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 36452827500. Starting simulation... +info: Entering event queue @ 36459605000. Starting simulation... switching cpus -info: Entering event queue @ 36452828500. Starting simulation... +info: Entering event queue @ 36459612500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 37452828500. Starting simulation... +info: Entering event queue @ 37459612500. Starting simulation... switching cpus -info: Entering event queue @ 37452831500. Starting simulation... +info: Entering event queue @ 37459615500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 38452831500. Starting simulation... +info: Entering event queue @ 38459615500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 39452831500. Starting simulation... +info: Entering event queue @ 39459615500. Starting simulation... switching cpus -info: Entering event queue @ 39452832500. Starting simulation... +info: Entering event queue @ 39459623000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 40452832500. Starting simulation... +info: Entering event queue @ 40459623000. Starting simulation... switching cpus -info: Entering event queue @ 40452835500. Starting simulation... +info: Entering event queue @ 40459626000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 41452835500. Starting simulation... +info: Entering event queue @ 41459626000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 42452835500. Starting simulation... +info: Entering event queue @ 42459626000. Starting simulation... switching cpus -info: Entering event queue @ 42452836500. Starting simulation... +info: Entering event queue @ 42459633500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 43452836500. Starting simulation... +info: Entering event queue @ 43459633500. Starting simulation... switching cpus info: Entering event queue @ 43945335500. Starting simulation... Switching CPUs... @@ -1088,18 +1091,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 304757835500. Starting simulation... switching cpus -info: Entering event queue @ 304758051500. Starting simulation... +info: Entering event queue @ 304757908000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 305758051500. Starting simulation... +info: Entering event queue @ 305757908000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 306758051500. Starting simulation... +info: Entering event queue @ 306757908000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 307758051500. Starting simulation... +info: Entering event queue @ 307757908000. Starting simulation... switching cpus info: Entering event queue @ 308593773000. Starting simulation... Switching CPUs... @@ -1968,10 +1971,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 568406273000. Starting simulation... switching cpus -info: Entering event queue @ 568406301000. Starting simulation... +info: Entering event queue @ 568406377000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 569406301000. Starting simulation... +info: Entering event queue @ 569406377000. Starting simulation... switching cpus info: Entering event queue @ 570312523000. Starting simulation... Switching CPUs... @@ -2156,18 +2159,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 624093773500. Starting simulation... switching cpus -info: Entering event queue @ 624218766000. Starting simulation... +info: Entering event queue @ 624218753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 625218766000. Starting simulation... +info: Entering event queue @ 625218753000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 626218766000. Starting simulation... +info: Entering event queue @ 626218753000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 627218766000. Starting simulation... +info: Entering event queue @ 627218753000. Starting simulation... switching cpus info: Entering event queue @ 627929709000. Starting simulation... Switching CPUs... @@ -2529,10 +2532,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 735398460500. Starting simulation... switching cpus -info: Entering event queue @ 735398461500. Starting simulation... +info: Entering event queue @ 735398468000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 736398461500. Starting simulation... +info: Entering event queue @ 736398468000. Starting simulation... switching cpus info: Entering event queue @ 737304710500. Starting simulation... Switching CPUs... @@ -2881,10 +2884,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 840867210500. Starting simulation... switching cpus -info: Entering event queue @ 840867211500. Starting simulation... +info: Entering event queue @ 840867218000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 841867211500. Starting simulation... +info: Entering event queue @ 841867218000. Starting simulation... switching cpus info: Entering event queue @ 842773460500. Starting simulation... Switching CPUs... @@ -3233,10 +3236,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 946335960500. Starting simulation... switching cpus -info: Entering event queue @ 946335961500. Starting simulation... +info: Entering event queue @ 946335968000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 947335961500. Starting simulation... +info: Entering event queue @ 947335968000. Starting simulation... switching cpus info: Entering event queue @ 948242210500. Starting simulation... Switching CPUs... @@ -3936,49 +3939,49 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1157273460500. Starting simulation... switching cpus -info: Entering event queue @ 1157273461000. Starting simulation... +info: Entering event queue @ 1157273468000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1158273461000. Starting simulation... +info: Entering event queue @ 1158273468000. Starting simulation... switching cpus -info: Entering event queue @ 1159361004000. Starting simulation... +info: Entering event queue @ 1159362057000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1160361004000. Starting simulation... +info: Entering event queue @ 1160362057000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1161361004000. Starting simulation... +info: Entering event queue @ 1161362057000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1162361004000. Starting simulation... +info: Entering event queue @ 1162362057000. Starting simulation... switching cpus -info: Entering event queue @ 1162361007000. Starting simulation... +info: Entering event queue @ 1162362060000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1163361007000. Starting simulation... +info: Entering event queue @ 1163362060000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1164361007000. Starting simulation... +info: Entering event queue @ 1164362060000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1165361007000. Starting simulation... +info: Entering event queue @ 1165362060000. Starting simulation... switching cpus -info: Entering event queue @ 1165361010000. Starting simulation... +info: Entering event queue @ 1165362063000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1166361010000. Starting simulation... +info: Entering event queue @ 1166362063000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1167361010000. Starting simulation... +info: Entering event queue @ 1167362063000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1168361010000. Starting simulation... +info: Entering event queue @ 1168362063000. Starting simulation... switching cpus info: Entering event queue @ 1168945335500. Starting simulation... Switching CPUs... @@ -5731,10 +5734,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1694382835500. Starting simulation... switching cpus -info: Entering event queue @ 1694382836500. Starting simulation... +info: Entering event queue @ 1694382843000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1695382836500. Starting simulation... +info: Entering event queue @ 1695382843000. Starting simulation... switching cpus info: Entering event queue @ 1696289085500. Starting simulation... Switching CPUs... @@ -5771,10 +5774,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1706101585500. Starting simulation... switching cpus -info: Entering event queue @ 1706101586500. Starting simulation... +info: Entering event queue @ 1706101593000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1707101586500. Starting simulation... +info: Entering event queue @ 1707101593000. Starting simulation... switching cpus info: Entering event queue @ 1708007835500. Starting simulation... Switching CPUs... @@ -5900,11 +5903,12 @@ switching cpus info: Entering event queue @ 1744164085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -switching cpus info: Entering event queue @ 1745164085500. Starting simulation... +switching cpus +info: Entering event queue @ 1745164093000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1746164085500. Starting simulation... +info: Entering event queue @ 1746164093000. Starting simulation... switching cpus info: Entering event queue @ 1747070335500. Starting simulation... Switching CPUs... @@ -5980,10 +5984,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1768601585500. Starting simulation... switching cpus -info: Entering event queue @ 1768601735500. Starting simulation... +info: Entering event queue @ 1768601593000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1769601735500. Starting simulation... +info: Entering event queue @ 1769601593000. Starting simulation... switching cpus info: Entering event queue @ 1770507835500. Starting simulation... Switching CPUs... @@ -6011,18 +6015,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 1777414085500. Starting simulation... switching cpus -info: Entering event queue @ 1777414674000. Starting simulation... +info: Entering event queue @ 1777415067000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1778414674000. Starting simulation... +info: Entering event queue @ 1778415067000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1779414674000. Starting simulation... +info: Entering event queue @ 1779415067000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1780414674000. Starting simulation... +info: Entering event queue @ 1780415067000. Starting simulation... switching cpus info: Entering event queue @ 1781250023000. Starting simulation... Switching CPUs... @@ -6033,10 +6037,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1783250023000. Starting simulation... switching cpus -info: Entering event queue @ 1783250024000. Starting simulation... +info: Entering event queue @ 1783250030500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1784250024000. Starting simulation... +info: Entering event queue @ 1784250030500. Starting simulation... switching cpus info: Entering event queue @ 1785156273000. Starting simulation... Switching CPUs... @@ -6073,10 +6077,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1794968773000. Starting simulation... switching cpus -info: Entering event queue @ 1794968774000. Starting simulation... +info: Entering event queue @ 1794968780500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1795968774000. Starting simulation... +info: Entering event queue @ 1795968780500. Starting simulation... switching cpus info: Entering event queue @ 1796875023000. Starting simulation... Switching CPUs... @@ -6113,10 +6117,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1806687523000. Starting simulation... switching cpus -info: Entering event queue @ 1806687524000. Starting simulation... +info: Entering event queue @ 1806687530500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1807687524000. Starting simulation... +info: Entering event queue @ 1807687530500. Starting simulation... switching cpus info: Entering event queue @ 1808593773000. Starting simulation... Switching CPUs... @@ -6153,37 +6157,37 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1818406273000. Starting simulation... switching cpus -info: Entering event queue @ 1818406274000. Starting simulation... +info: Entering event queue @ 1818406280500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1819406274000. Starting simulation... +info: Entering event queue @ 1819406280500. Starting simulation... switching cpus -info: Entering event queue @ 1819406403500. Starting simulation... +info: Entering event queue @ 1819406919000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1820406403500. Starting simulation... +info: Entering event queue @ 1820406919000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1821406403500. Starting simulation... +info: Entering event queue @ 1821406919000. Starting simulation... switching cpus -info: Entering event queue @ 1821406404500. Starting simulation... +info: Entering event queue @ 1821406926500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1822406404500. Starting simulation... +info: Entering event queue @ 1822406926500. Starting simulation... switching cpus -info: Entering event queue @ 1822406407500. Starting simulation... +info: Entering event queue @ 1822406934000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1823406407500. Starting simulation... +info: Entering event queue @ 1823406934000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1824406407500. Starting simulation... +info: Entering event queue @ 1824406934000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1825406407500. Starting simulation... +info: Entering event queue @ 1825406934000. Starting simulation... switching cpus info: Entering event queue @ 1826171898000. Starting simulation... Switching CPUs... @@ -6197,21 +6201,22 @@ info: Entering event queue @ 1828171898000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 1829171898000. Starting simulation... -info: Entering event queue @ 1829171913500. Starting simulation... +info: Entering event queue @ 1829171905500. Starting simulation... +info: Entering event queue @ 1829171910500. Starting simulation... switching cpus -info: Entering event queue @ 1829171918000. Starting simulation... +info: Entering event queue @ 1829171915000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1830171918000. Starting simulation... +info: Entering event queue @ 1830171915000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1831171918000. Starting simulation... +info: Entering event queue @ 1831171915000. Starting simulation... switching cpus -info: Entering event queue @ 1831171920000. Starting simulation... +info: Entering event queue @ 1831171922500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1832171920000. Starting simulation... +info: Entering event queue @ 1832171922500. Starting simulation... switching cpus info: Entering event queue @ 1833007835500. Starting simulation... Switching CPUs... @@ -6234,16 +6239,16 @@ info: Entering event queue @ 1837914085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1838914085500. Starting simulation... -info: Entering event queue @ 1838914092000. Starting simulation... +info: Entering event queue @ 1838914097000. Starting simulation... switching cpus -info: Entering event queue @ 1838914095500. Starting simulation... +info: Entering event queue @ 1838914100500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1839914095500. Starting simulation... -info: Entering event queue @ 1839914105000. Starting simulation... +info: Entering event queue @ 1839914100500. Starting simulation... +info: Entering event queue @ 1839914110000. Starting simulation... switching cpus -info: Entering event queue @ 1839914109500. Starting simulation... +info: Entering event queue @ 1839914114500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1840914109500. Starting simulation... +info: Entering event queue @ 1840914114500. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 65a9d1fb5..044f27d13 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841686 # Number of seconds simulated -sim_ticks 1841685557500 # Number of ticks simulated -final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841723 # Number of seconds simulated +sim_ticks 1841722715000 # Number of ticks simulated +final_tick 1841722715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 257826 # Simulator instruction rate (inst/s) -host_op_rate 257826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6831790357 # Simulator tick rate (ticks/s) -host_mem_usage 316032 # Number of bytes of host memory used -host_seconds 269.58 # Real time elapsed on the host -sim_insts 69503534 # Number of instructions simulated -sim_ops 69503534 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19348096 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2814720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2705088 # Number of bytes read from this memory -system.physmem.bytes_read::total 28439424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7476992 # Number of bytes written to this memory -system.physmem.bytes_written::total 7476992 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302314 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4608 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42267 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444366 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116828 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116828 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10505646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1528339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 160132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1468811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15442063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 160132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4059864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4059864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4059864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10505646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1528339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 160132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1468811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109963 # Total number of read requests seen -system.physmem.writeReqs 45515 # Total number of write requests seen -system.physmem.cpureqs 155519 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7037632 # Total number of bytes read from memory -system.physmem.bytesWritten 2912960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2912960 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 40 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6833 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7049 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7191 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6826 # Track reads on a per bank basis +host_inst_rate 105391 # Simulator instruction rate (inst/s) +host_op_rate 105391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2775370642 # Simulator tick rate (ticks/s) +host_mem_usage 350548 # Number of bytes of host memory used +host_seconds 663.60 # Real time elapsed on the host +sim_insts 69936964 # Number of instructions simulated +sim_ops 69936964 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19361152 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2812480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2695680 # Number of bytes read from this memory +system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7466432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7466432 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302518 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 43945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116663 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116663 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10512523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1440147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1527092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1463673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15442516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499081 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10512523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1440147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1527092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1463673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19496564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109804 # Total number of read requests seen +system.physmem.writeReqs 45341 # Total number of write requests seen +system.physmem.cpureqs 155197 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7027456 # Total number of bytes read from memory +system.physmem.bytesWritten 2901824 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7027456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2901824 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6917 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6836 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6845 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2979 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2790 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2684 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2595 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2752 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3044 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2867 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2811 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 6842 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2936 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2758 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2772 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840673470000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840710411000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109963 # Categorize read packet sizes +system.physmem.readPktSize::6 109804 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 45515 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 80954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 45341 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 80889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1047 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,46 +148,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.totQLat 2376402250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4386836000 # Sum of mem lat for all requests -system.physmem.totBusLat 549785000 # Total cycles spent in databus access -system.physmem.totBankLat 1460648750 # Total cycles spent in bank access -system.physmem.avgQLat 21612.11 # Average queueing delay per request -system.physmem.avgBankLat 13283.82 # Average bank access latency per request +system.physmem.wrQLenPdf::0 1251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.totQLat 2345988500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4348949750 # Sum of mem lat for all requests +system.physmem.totBusLat 548995000 # Total cycles spent in databus access +system.physmem.totBankLat 1453966250 # Total cycles spent in bank access +system.physmem.avgQLat 21366.21 # Average queueing delay per request +system.physmem.avgBankLat 13242.07 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39895.92 # Average memory access latency +system.physmem.avgMemAccLat 39608.28 # Average memory access latency system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s @@ -195,195 +195,195 @@ system.physmem.avgConsumedWrBW 1.58 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.16 # Average write queue length over time -system.physmem.readRowHits 99744 # Number of row buffer hits during reads -system.physmem.writeRowHits 34338 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.44 # Row buffer hit rate for writes -system.physmem.avgGap 11838803.37 # Average gap between requests -system.l2c.replacements 337431 # number of replacements -system.l2c.tagsinuse 65421.769821 # Cycle average of tags in use -system.l2c.total_refs 2476371 # Total number of references to valid blocks. -system.l2c.sampled_refs 402593 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.151053 # Average number of references to valid blocks. +system.physmem.avgWrQLen 0.17 # Average write queue length over time +system.physmem.readRowHits 99788 # Number of row buffer hits during reads +system.physmem.writeRowHits 34189 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.40 # Row buffer hit rate for writes +system.physmem.avgGap 11864452.04 # Average gap between requests +system.l2c.replacements 337462 # number of replacements +system.l2c.tagsinuse 65423.385083 # Cycle average of tags in use +system.l2c.total_refs 2475374 # Total number of references to valid blocks. +system.l2c.sampled_refs 402624 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.148103 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54783.846469 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2311.752265 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2671.563738 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 585.881665 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 667.174389 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2255.430098 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2146.121197 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.835935 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.035275 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040765 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.008940 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.010180 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.034415 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032747 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998257 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 514621 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491109 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83687 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 298608 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 242406 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1757156 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836280 # number of Writeback hits -system.l2c.Writeback_hits::total 836280 # number of Writeback hits +system.l2c.occ_blocks::writebacks 54864.603018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2279.979000 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2628.690447 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 619.088006 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 659.286821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2246.098023 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 2125.639768 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.837167 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.034790 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.040111 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.009447 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.010060 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.034273 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.032435 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998282 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 516841 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 491603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 126887 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83607 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 295482 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 241937 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1756357 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 836151 # number of Writeback hits +system.l2c.Writeback_hits::total 836151 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92033 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27042 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186915 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 514621 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 583142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 126725 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 110729 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 298608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 310246 # number of demand (read+write) hits -system.l2c.demand_hits::total 1944071 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 514621 # number of overall hits -system.l2c.overall_hits::cpu0.data 583142 # number of overall hits -system.l2c.overall_hits::cpu1.inst 126725 # number of overall hits -system.l2c.overall_hits::cpu1.data 110729 # number of overall hits -system.l2c.overall_hits::cpu2.inst 298608 # number of overall hits -system.l2c.overall_hits::cpu2.data 310246 # number of overall hits -system.l2c.overall_hits::total 1944071 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7410 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 225248 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2345 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 23010 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4608 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 24959 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287580 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 92117 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 27417 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67376 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186910 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 516841 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 583720 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 126887 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 111024 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 295482 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 309313 # number of demand (read+write) hits +system.l2c.demand_hits::total 1943267 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 516841 # number of overall hits +system.l2c.overall_hits::cpu0.data 583720 # number of overall hits +system.l2c.overall_hits::cpu1.inst 126887 # number of overall hits +system.l2c.overall_hits::cpu1.data 111024 # number of overall hits +system.l2c.overall_hits::cpu2.inst 295482 # number of overall hits +system.l2c.overall_hits::cpu2.data 309313 # number of overall hits +system.l2c.overall_hits::total 1943267 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7386 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 225256 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2379 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 23009 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4597 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 24998 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287625 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 10 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77341 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21020 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 17409 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115770 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7410 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 302589 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2345 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 44030 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4608 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 42368 # number of demand (read+write) misses -system.l2c.demand_misses::total 403350 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7410 # number of overall misses -system.l2c.overall_misses::cpu0.data 302589 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2345 # number of overall misses -system.l2c.overall_misses::cpu1.data 44030 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4608 # number of overall misses -system.l2c.overall_misses::cpu2.data 42368 # number of overall misses -system.l2c.overall_misses::total 403350 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 151883500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1053888000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 310106500 # 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number of cycles access was blocked -system.iocache.blocked::no_mshrs 11151 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10981 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.406331 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.414807 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -562,12 +562,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 16837 system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433481639 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3433481639 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3439070888 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3439070888 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3439070888 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3439070888 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3410139151 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3410139151 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3415728400 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3415728400 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3415728400 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3415728400 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses @@ -578,12 +578,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204763.933624 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204763.933624 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204256.749302 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 204256.749302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204256.749302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 204256.749302 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203371.848223 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203371.848223 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -601,22 +601,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4874109 # DTB read hits -system.cpu0.dtb.read_misses 5989 # DTB read misses -system.cpu0.dtb.read_acv 118 # DTB read access violations -system.cpu0.dtb.read_accesses 427176 # DTB read accesses -system.cpu0.dtb.write_hits 3500725 # DTB write hits +system.cpu0.dtb.read_hits 4882466 # DTB read hits +system.cpu0.dtb.read_misses 6004 # DTB read misses +system.cpu0.dtb.read_acv 119 # DTB read access violations +system.cpu0.dtb.read_accesses 427336 # DTB read accesses +system.cpu0.dtb.write_hits 3509197 # DTB write hits system.cpu0.dtb.write_misses 661 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162885 # DTB write accesses -system.cpu0.dtb.data_hits 8374834 # DTB hits -system.cpu0.dtb.data_misses 6650 # DTB misses -system.cpu0.dtb.data_acv 200 # DTB access violations -system.cpu0.dtb.data_accesses 590061 # DTB accesses -system.cpu0.itb.fetch_hits 2743092 # ITB hits -system.cpu0.itb.fetch_misses 2995 # ITB misses -system.cpu0.itb.fetch_acv 98 # ITB acv -system.cpu0.itb.fetch_accesses 2746087 # ITB accesses +system.cpu0.dtb.write_accesses 162892 # DTB write accesses +system.cpu0.dtb.data_hits 8391663 # DTB hits +system.cpu0.dtb.data_misses 6665 # DTB misses +system.cpu0.dtb.data_acv 201 # DTB access violations +system.cpu0.dtb.data_accesses 590228 # DTB accesses +system.cpu0.itb.fetch_hits 2746663 # ITB hits +system.cpu0.itb.fetch_misses 2999 # ITB misses +system.cpu0.itb.fetch_acv 99 # ITB acv +system.cpu0.itb.fetch_accesses 2749662 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -629,51 +629,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928539725 # number of cpu cycles simulated +system.cpu0.numCycles 928532780 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32518253 # Number of instructions committed -system.cpu0.committedOps 32518253 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30397519 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 168035 # Number of float alu accesses -system.cpu0.num_func_calls 808172 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4307008 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30397519 # number of integer instructions -system.cpu0.num_fp_insts 168035 # number of float instructions -system.cpu0.num_int_register_reads 42396693 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22221610 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86774 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88345 # number of times the floating registers were written -system.cpu0.num_mem_refs 8404498 # number of memory refs -system.cpu0.num_load_insts 4895120 # Number of load instructions -system.cpu0.num_store_insts 3509378 # Number of store instructions -system.cpu0.num_idle_cycles 214025441196.436279 # Number of idle cycles -system.cpu0.num_busy_cycles -213096901471.436279 # Number of busy cycles -system.cpu0.not_idle_fraction -229.496806 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.496806 # Percentage of idle cycles +system.cpu0.committedInsts 33005928 # Number of instructions committed +system.cpu0.committedOps 33005928 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30880412 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 168592 # Number of float alu accesses +system.cpu0.num_func_calls 809679 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4456286 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30880412 # number of integer instructions +system.cpu0.num_fp_insts 168592 # number of float instructions +system.cpu0.num_int_register_reads 43182890 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22546428 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87049 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88627 # number of times the floating registers were written +system.cpu0.num_mem_refs 8421419 # number of memory refs +system.cpu0.num_load_insts 4903545 # Number of load instructions +system.cpu0.num_store_insts 3517874 # Number of store instructions +system.cpu0.num_idle_cycles 214028071508.499786 # Number of idle cycles +system.cpu0.num_busy_cycles -213099538728.499786 # Number of busy cycles +system.cpu0.not_idle_fraction -229.501363 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.501363 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211357 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818586321500 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38755000 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363405500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22696319000 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841684801000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818570193000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39079500 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365062500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22747610500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841721945500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694792 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -709,10 +709,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -721,21 +721,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192213 # number of callpals executed +system.cpu0.kern.callpal::total 192207 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1739 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391349 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29734416500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2561211500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809389169500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29799200000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2569954000 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809352787000 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -767,372 +767,372 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 953667 # number of replacements -system.cpu0.icache.tagsinuse 511.197543 # Cycle average of tags in use -system.cpu0.icache.total_refs 42031546 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 954178 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 44.050005 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10246755000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 255.638706 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 78.351576 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 177.207261 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.499294 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.153030 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.346108 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998433 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32003051 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7743805 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2284690 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42031546 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32003051 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7743805 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2284690 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42031546 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32003051 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7743805 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2284690 # number of overall hits -system.cpu0.icache.overall_hits::total 42031546 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 522052 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129070 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 320206 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 971328 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 522052 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129070 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 320206 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 971328 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 522052 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129070 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 320206 # number of overall misses -system.cpu0.icache.overall_misses::total 971328 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813664500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4475771482 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6289435982 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1813664500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4475771482 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6289435982 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1813664500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4475771482 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6289435982 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32525103 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7872875 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2604896 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43002874 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32525103 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7872875 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2604896 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43002874 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32525103 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7872875 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2604896 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43002874 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016051 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016394 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122925 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022588 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016051 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016394 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122925 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022588 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016051 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016394 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122925 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022588 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14051.789727 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.787680 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6475.089755 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6475.089755 # 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number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7863333 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2598185 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43474312 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015880 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016439 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121888 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015880 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016439 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121888 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022317 # 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average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25.226509 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 428.285714 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 836280 # number of writebacks -system.cpu0.dcache.writebacks::total 836280 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285653 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 285653 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 476174 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 476174 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1502 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1502 # 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number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3274865000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6450558124 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9725423124 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3274865000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6450558124 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9725423124 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287731500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 345150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 632882000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357324500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 421745500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 779070000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645056000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 766896000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411952000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086890 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088411 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041068 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.052979 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045452 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021633 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102047 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.100173 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038166 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3265053500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6431550131 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9696603631 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3265053500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6431550131 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9696603631 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287785000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353197500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 640982500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356424500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429964000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786388500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644209500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 783161500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1427371000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088596 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041028 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053275 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045350 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021584 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103106 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099737 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037983 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033138 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033138 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18905.735666 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.836989 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17137.858645 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27029.939871 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25222.004775 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25874.946454 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11389.420885 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12742.713206 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12359.824539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18852.210686 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.245651 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17122.374280 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26792.657480 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25265.269090 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25822.119015 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11164.634146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12701.800655 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12260.503112 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1147,22 +1147,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1221793 # DTB read hits -system.cpu1.dtb.read_misses 1550 # DTB read misses -system.cpu1.dtb.read_acv 45 # DTB read access violations -system.cpu1.dtb.read_accesses 143987 # DTB read accesses -system.cpu1.dtb.write_hits 928954 # DTB write hits -system.cpu1.dtb.write_misses 206 # DTB write misses +system.cpu1.dtb.read_hits 1221293 # DTB read hits +system.cpu1.dtb.read_misses 1489 # DTB read misses +system.cpu1.dtb.read_acv 40 # DTB read access violations +system.cpu1.dtb.read_accesses 143781 # DTB read accesses +system.cpu1.dtb.write_hits 930282 # DTB write hits +system.cpu1.dtb.write_misses 202 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 60098 # DTB write accesses -system.cpu1.dtb.data_hits 2150747 # DTB hits -system.cpu1.dtb.data_misses 1756 # DTB misses -system.cpu1.dtb.data_acv 69 # DTB access violations -system.cpu1.dtb.data_accesses 204085 # DTB accesses -system.cpu1.itb.fetch_hits 875028 # ITB hits -system.cpu1.itb.fetch_misses 772 # ITB misses -system.cpu1.itb.fetch_acv 46 # ITB acv -system.cpu1.itb.fetch_accesses 875800 # ITB accesses +system.cpu1.dtb.write_accesses 59266 # DTB write accesses +system.cpu1.dtb.data_hits 2151575 # DTB hits +system.cpu1.dtb.data_misses 1691 # DTB misses +system.cpu1.dtb.data_acv 64 # DTB access violations +system.cpu1.dtb.data_accesses 203047 # DTB accesses +system.cpu1.itb.fetch_hits 872259 # ITB hits +system.cpu1.itb.fetch_misses 756 # ITB misses +system.cpu1.itb.fetch_acv 43 # ITB acv +system.cpu1.itb.fetch_accesses 873015 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1175,28 +1175,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953543873 # number of cpu cycles simulated +system.cpu1.numCycles 953618286 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7871049 # Number of instructions committed -system.cpu1.committedOps 7871049 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7322486 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45486 # Number of float alu accesses -system.cpu1.num_func_calls 212361 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 961543 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7322486 # number of integer instructions -system.cpu1.num_fp_insts 45486 # number of float instructions -system.cpu1.num_int_register_reads 10177666 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5328829 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24537 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24857 # number of times the floating registers were written -system.cpu1.num_mem_refs 2158619 # number of memory refs -system.cpu1.num_load_insts 1227197 # Number of load instructions -system.cpu1.num_store_insts 931422 # Number of store instructions -system.cpu1.num_idle_cycles -1678612352.135852 # Number of idle cycles -system.cpu1.num_busy_cycles 2632156225.135852 # Number of busy cycles -system.cpu1.not_idle_fraction 2.760393 # Percentage of non-idle cycles -system.cpu1.idle_fraction -1.760393 # Percentage of idle cycles +system.cpu1.committedInsts 7861577 # Number of instructions committed +system.cpu1.committedOps 7861577 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7312995 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45507 # Number of float alu accesses +system.cpu1.num_func_calls 212083 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 960021 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7312995 # number of integer instructions +system.cpu1.num_fp_insts 45507 # number of float instructions +system.cpu1.num_int_register_reads 10166941 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5319886 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24589 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24824 # number of times the floating registers were written +system.cpu1.num_mem_refs 2159267 # number of memory refs +system.cpu1.num_load_insts 1226545 # Number of load instructions +system.cpu1.num_store_insts 932722 # Number of store instructions +system.cpu1.num_idle_cycles -1640970508.007204 # Number of idle cycles +system.cpu1.num_busy_cycles 2594588794.007204 # Number of busy cycles +system.cpu1.not_idle_fraction 2.720783 # Percentage of non-idle cycles +system.cpu1.idle_fraction -1.720783 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1214,35 +1214,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8388883 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7698653 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129790 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6809522 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5746337 # Number of BTB hits +system.cpu2.branchPred.lookups 8378030 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7687664 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 128422 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6832370 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5743236 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.386790 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 285994 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15305 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.059206 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 286145 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15066 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3222753 # DTB read hits -system.cpu2.dtb.read_misses 11767 # DTB read misses -system.cpu2.dtb.read_acv 114 # DTB read access violations -system.cpu2.dtb.read_accesses 216394 # DTB read accesses -system.cpu2.dtb.write_hits 1997746 # DTB write hits -system.cpu2.dtb.write_misses 2597 # DTB write misses -system.cpu2.dtb.write_acv 133 # DTB write access violations -system.cpu2.dtb.write_accesses 81219 # DTB write accesses -system.cpu2.dtb.data_hits 5220499 # DTB hits -system.cpu2.dtb.data_misses 14364 # DTB misses -system.cpu2.dtb.data_acv 247 # DTB access violations -system.cpu2.dtb.data_accesses 297613 # DTB accesses -system.cpu2.itb.fetch_hits 371919 # ITB hits -system.cpu2.itb.fetch_misses 5650 # ITB misses -system.cpu2.itb.fetch_acv 270 # ITB acv -system.cpu2.itb.fetch_accesses 377569 # ITB accesses +system.cpu2.dtb.read_hits 3213070 # DTB read hits +system.cpu2.dtb.read_misses 11858 # DTB read misses +system.cpu2.dtb.read_acv 125 # DTB read access violations +system.cpu2.dtb.read_accesses 216838 # DTB read accesses +system.cpu2.dtb.write_hits 1985729 # DTB write hits +system.cpu2.dtb.write_misses 2626 # DTB write misses +system.cpu2.dtb.write_acv 132 # DTB write access violations +system.cpu2.dtb.write_accesses 82100 # DTB write accesses +system.cpu2.dtb.data_hits 5198799 # DTB hits +system.cpu2.dtb.data_misses 14484 # DTB misses +system.cpu2.dtb.data_acv 257 # DTB access violations +system.cpu2.dtb.data_accesses 298938 # DTB accesses +system.cpu2.itb.fetch_hits 371799 # ITB hits +system.cpu2.itb.fetch_misses 5527 # ITB misses +system.cpu2.itb.fetch_acv 268 # ITB acv +system.cpu2.itb.fetch_accesses 377326 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1255,270 +1255,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30487191 # number of cpu cycles simulated +system.cpu2.numCycles 30456501 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8524791 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34873991 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8388883 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6032331 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8111828 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 622665 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9676306 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1940 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 62420 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 80561 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2604903 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90729 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26874751 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.297649 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.309099 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8496671 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34814108 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8378030 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6029381 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8102862 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 619747 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9664951 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63044 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 81651 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2598193 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 89272 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26826827 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.297735 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.308224 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18762923 69.82% 69.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 273694 1.02% 70.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 440641 1.64% 72.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4237897 15.77% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 736346 2.74% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 166761 0.62% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 196079 0.73% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433619 1.61% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1626791 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18723965 69.80% 69.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 272177 1.01% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 439981 1.64% 72.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4242616 15.81% 88.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 731901 2.73% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 167093 0.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 195068 0.73% 92.34% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 431564 1.61% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1622462 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26874751 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.275161 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.143890 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8657787 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9768162 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7515953 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293497 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 393434 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 168963 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12933 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34472576 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40526 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 393434 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9012684 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2836795 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5769605 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7372565 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1243759 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33316352 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2373 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234595 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 408588 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22366948 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41510379 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41345500 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 164879 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20534540 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1832408 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 504738 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 60071 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3686935 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3385510 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2088081 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 373278 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 254690 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30792200 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 629969 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30337437 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 32004 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2187587 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1093629 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 444846 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26874751 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.128845 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565283 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26826827 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.275082 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.143076 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8629429 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9759568 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7506924 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293586 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 391402 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168327 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12875 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34412678 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40383 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 391402 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8983257 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2851254 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5747978 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7364591 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1242431 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33259666 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2378 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 235537 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 408509 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22329491 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41447748 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41283919 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 163829 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20504321 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1825170 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 503302 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59735 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3683278 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3372566 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2079103 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 375078 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 254621 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30740575 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 627044 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30281796 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 33788 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2178999 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1098942 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 442743 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26826827 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.128788 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.564676 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15311841 56.97% 56.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3103500 11.55% 68.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1551808 5.77% 74.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5059769 18.83% 93.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 912287 3.39% 96.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 489619 1.82% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286015 1.06% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141615 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18297 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15280016 56.96% 56.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3100114 11.56% 68.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1550183 5.78% 74.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5057659 18.85% 93.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 908873 3.39% 96.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 486444 1.81% 98.35% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 282646 1.05% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 142385 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18507 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26874751 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26826827 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34821 13.89% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 112497 44.88% 58.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103352 41.23% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34417 13.83% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 111473 44.80% 58.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 102914 41.36% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24640378 81.22% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20252 0.07% 81.30% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8482 0.03% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3354206 11.06% 92.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2020424 6.66% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 290023 0.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24609882 81.27% 81.28% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20276 0.07% 81.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8461 0.03% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3342059 11.04% 92.41% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2007965 6.63% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 289481 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30337437 # Type of FU issued -system.cpu2.iq.rate 0.995088 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 250670 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008263 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87595744 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33498169 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29934734 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 236555 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 115613 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112132 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30462481 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123178 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 189585 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30281796 # Type of FU issued +system.cpu2.iq.rate 0.994264 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 248804 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008216 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87438155 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33435914 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29882334 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234856 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114775 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 111304 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30405901 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122251 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 189317 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 417411 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 964 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4105 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 161809 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 413545 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 931 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4171 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 163357 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4731 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 22958 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4715 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 24094 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 393434 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2055085 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 212014 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32707784 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224122 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3385510 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2088081 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 559310 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 150319 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2295 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4105 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66873 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 130024 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196897 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30173481 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3242841 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 163956 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 391402 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2071748 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 210417 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32647605 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 226082 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3372566 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2079103 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 556688 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 148464 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2072 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4171 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 65897 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 129325 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30121577 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3233216 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 160219 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1285615 # number of nop insts executed -system.cpu2.iew.exec_refs 5247672 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6797242 # Number of branches executed -system.cpu2.iew.exec_stores 2004831 # Number of stores executed -system.cpu2.iew.exec_rate 0.989710 # Inst execution rate -system.cpu2.iew.wb_sent 30079535 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30046866 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17352028 # num instructions producing a value -system.cpu2.iew.wb_consumers 20589621 # num instructions consuming a value +system.cpu2.iew.exec_nop 1279986 # number of nop insts executed +system.cpu2.iew.exec_refs 5226048 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6791959 # Number of branches executed +system.cpu2.iew.exec_stores 1992832 # Number of stores executed +system.cpu2.iew.exec_rate 0.989003 # Inst execution rate +system.cpu2.iew.wb_sent 30026869 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29993638 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17325737 # num instructions producing a value +system.cpu2.iew.wb_consumers 20548779 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.985557 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842756 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.984802 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.843152 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2372790 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 185123 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182681 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26481317 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.143824 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.850690 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2362249 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 184301 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 181159 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26435425 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.143965 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.849596 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16366667 61.80% 61.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2324205 8.78% 70.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1216165 4.59% 75.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4790733 18.09% 93.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 501931 1.90% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186373 0.70% 95.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 179761 0.68% 96.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180772 0.68% 97.23% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 734710 2.77% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16333385 61.79% 61.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2318132 8.77% 70.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1214509 4.59% 75.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4793021 18.13% 93.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 499893 1.89% 95.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185577 0.70% 95.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 178746 0.68% 96.55% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 182246 0.69% 97.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 729916 2.76% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26481317 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30289973 # Number of instructions committed -system.cpu2.commit.committedOps 30289973 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26435425 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30241196 # Number of instructions committed +system.cpu2.commit.committedOps 30241196 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4894371 # Number of memory references committed -system.cpu2.commit.loads 2968099 # Number of loads committed -system.cpu2.commit.membars 65019 # Number of memory barriers committed -system.cpu2.commit.branches 6647353 # Number of branches committed -system.cpu2.commit.fp_insts 110870 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28830509 # Number of committed integer instructions. -system.cpu2.commit.function_calls 231619 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 734710 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4874767 # Number of memory references committed +system.cpu2.commit.loads 2959021 # Number of loads committed +system.cpu2.commit.membars 64729 # Number of memory barriers committed +system.cpu2.commit.branches 6642526 # Number of branches committed +system.cpu2.commit.fp_insts 110158 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28786790 # Number of committed integer instructions. +system.cpu2.commit.function_calls 230913 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 729916 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58337288 # The number of ROB reads -system.cpu2.rob.rob_writes 65718838 # The number of ROB writes -system.cpu2.timesIdled 243105 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3612440 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745337726 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29114232 # Number of Instructions Simulated -system.cpu2.committedOps 29114232 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29114232 # Number of Instructions Simulated -system.cpu2.cpi 1.047158 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.047158 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.954966 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.954966 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39679960 # number of integer regfile reads -system.cpu2.int_regfile_writes 21237504 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68414 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68689 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4591435 # number of misc regfile reads -system.cpu2.misc_regfile_writes 259923 # number of misc regfile writes +system.cpu2.rob.rob_reads 58235962 # The number of ROB reads +system.cpu2.rob.rob_writes 65598028 # The number of ROB writes +system.cpu2.timesIdled 242236 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3629674 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745367915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29069459 # Number of Instructions Simulated +system.cpu2.committedOps 29069459 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29069459 # Number of Instructions Simulated +system.cpu2.cpi 1.047715 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.047715 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.954458 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.954458 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39608389 # number of integer regfile reads +system.cpu2.int_regfile_writes 21201849 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67944 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68330 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4592802 # number of misc regfile reads +system.cpu2.misc_regfile_writes 258987 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |