diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt | 1411 |
1 files changed, 715 insertions, 696 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 9af3017c0..2bd7abaa8 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.887184 # Number of seconds simulated -sim_ticks 1887184463000 # Number of ticks simulated -final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.887179 # Number of seconds simulated +sim_ticks 1887179292000 # Number of ticks simulated +final_tick 1887179292000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 272052 # Simulator instruction rate (inst/s) -host_op_rate 272052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9147074399 # Simulator tick rate (ticks/s) -host_mem_usage 373996 # Number of bytes of host memory used -host_seconds 206.32 # Real time elapsed on the host -sim_insts 56128524 # Number of instructions simulated -sim_ops 56128524 # Number of ops (including micro ops) simulated +host_inst_rate 271909 # Simulator instruction rate (inst/s) +host_op_rate 271909 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9140545464 # Simulator tick rate (ticks/s) +host_mem_usage 373988 # Number of bytes of host memory used +host_seconds 206.46 # Real time elapsed on the host +sim_insts 56138893 # Number of instructions simulated +sim_ops 56138893 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1052544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858944 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7558400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7558400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25912448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7556224 # Number of bytes written to this memory +system.physmem.bytes_written::total 7556224 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388421 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404899 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118100 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118100 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 557631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13173182 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118066 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118066 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 557734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13172540 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13731321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4005120 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4005120 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4005120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13173182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13730782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4003978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4003978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4003978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13172540 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404899 # Number of read requests accepted -system.physmem.writeReqs 159652 # Number of write requests accepted -system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 8555840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25937 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 159 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25492 # Per bank write bursts -system.physmem.perBankRdBursts::1 25732 # Per bank write bursts -system.physmem.perBankRdBursts::2 25844 # Per bank write bursts -system.physmem.perBankRdBursts::3 25788 # Per bank write bursts -system.physmem.perBankRdBursts::4 25096 # Per bank write bursts -system.physmem.perBankRdBursts::5 25019 # Per bank write bursts -system.physmem.perBankRdBursts::6 24724 # Per bank write bursts -system.physmem.perBankRdBursts::7 24556 # Per bank write bursts -system.physmem.perBankRdBursts::8 25196 # Per bank write bursts -system.physmem.perBankRdBursts::9 25300 # Per bank write bursts -system.physmem.perBankRdBursts::10 25394 # Per bank write bursts -system.physmem.perBankRdBursts::11 24993 # Per bank write bursts +system.physmem.bw_total::total 17734760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404882 # Number of read requests accepted +system.physmem.writeReqs 159618 # Number of write requests accepted +system.physmem.readBursts 404882 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159618 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25905920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 8528320 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25912448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10215552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26335 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25487 # Per bank write bursts +system.physmem.perBankRdBursts::1 25681 # Per bank write bursts +system.physmem.perBankRdBursts::2 25706 # Per bank write bursts +system.physmem.perBankRdBursts::3 25753 # Per bank write bursts +system.physmem.perBankRdBursts::4 25164 # Per bank write bursts +system.physmem.perBankRdBursts::5 25107 # Per bank write bursts +system.physmem.perBankRdBursts::6 24789 # Per bank write bursts +system.physmem.perBankRdBursts::7 24544 # Per bank write bursts +system.physmem.perBankRdBursts::8 25200 # Per bank write bursts +system.physmem.perBankRdBursts::9 25299 # Per bank write bursts +system.physmem.perBankRdBursts::10 25393 # Per bank write bursts +system.physmem.perBankRdBursts::11 24991 # Per bank write bursts system.physmem.perBankRdBursts::12 24525 # Per bank write bursts system.physmem.perBankRdBursts::13 25570 # Per bank write bursts system.physmem.perBankRdBursts::14 25834 # Per bank write bursts -system.physmem.perBankRdBursts::15 25739 # Per bank write bursts -system.physmem.perBankWrBursts::0 8904 # Per bank write bursts -system.physmem.perBankWrBursts::1 8550 # Per bank write bursts -system.physmem.perBankWrBursts::2 9134 # Per bank write bursts -system.physmem.perBankWrBursts::3 8817 # Per bank write bursts -system.physmem.perBankWrBursts::4 8179 # Per bank write bursts -system.physmem.perBankWrBursts::5 8016 # Per bank write bursts -system.physmem.perBankWrBursts::6 7555 # Per bank write bursts -system.physmem.perBankWrBursts::7 7380 # Per bank write bursts -system.physmem.perBankWrBursts::8 8271 # Per bank write bursts -system.physmem.perBankWrBursts::9 7751 # Per bank write bursts -system.physmem.perBankWrBursts::10 8147 # Per bank write bursts -system.physmem.perBankWrBursts::11 7871 # Per bank write bursts -system.physmem.perBankWrBursts::12 8181 # Per bank write bursts -system.physmem.perBankWrBursts::13 9046 # Per bank write bursts -system.physmem.perBankWrBursts::14 9003 # Per bank write bursts -system.physmem.perBankWrBursts::15 8880 # Per bank write bursts +system.physmem.perBankRdBursts::15 25737 # Per bank write bursts +system.physmem.perBankWrBursts::0 8901 # Per bank write bursts +system.physmem.perBankWrBursts::1 8465 # Per bank write bursts +system.physmem.perBankWrBursts::2 9022 # Per bank write bursts +system.physmem.perBankWrBursts::3 8725 # Per bank write bursts +system.physmem.perBankWrBursts::4 8062 # Per bank write bursts +system.physmem.perBankWrBursts::5 8096 # Per bank write bursts +system.physmem.perBankWrBursts::6 7614 # Per bank write bursts +system.physmem.perBankWrBursts::7 7482 # Per bank write bursts +system.physmem.perBankWrBursts::8 8269 # Per bank write bursts +system.physmem.perBankWrBursts::9 7671 # Per bank write bursts +system.physmem.perBankWrBursts::10 8104 # Per bank write bursts +system.physmem.perBankWrBursts::11 7830 # Per bank write bursts +system.physmem.perBankWrBursts::12 8200 # Per bank write bursts +system.physmem.perBankWrBursts::13 9100 # Per bank write bursts +system.physmem.perBankWrBursts::14 8920 # Per bank write bursts +system.physmem.perBankWrBursts::15 8794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 48 # Number of times write queue was full causing retry -system.physmem.totGap 1887175688500 # Total gap between requests +system.physmem.numWrRetry 50 # Number of times write queue was full causing retry +system.physmem.totGap 1887170570500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404899 # Read request sizes (log2) +system.physmem.readPktSize::6 404882 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159652 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159618 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,110 +148,129 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.921099 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 325.032687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.479352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10956 16.91% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3096 4.78% 52.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2482 3.83% 56.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1882 2.90% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1491 2.30% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1429 2.21% 64.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64763 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.696185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 324.957517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.417041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14664 22.64% 22.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11016 17.01% 39.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5432 8.39% 48.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3093 4.78% 52.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2464 3.80% 56.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1908 2.95% 59.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1486 2.29% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1430 2.21% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23270 35.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64763 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4906 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 82.503669 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3015.330482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4903 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.282653 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.334547 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 63.863816 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 12 0.24% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 6 0.12% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 26 0.53% 97.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 25 0.51% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 16 0.33% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 3 0.06% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 4 0.08% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 20 0.41% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 2 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 6 0.12% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 7 0.14% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 9 0.18% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 6 0.12% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads -system.physmem.totQLat 2145936500 # Total ticks spent queuing -system.physmem.totMemAccLat 9735974000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5301.20 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4906 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4906 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.161639 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.352681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 61.394400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4666 95.11% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 49 1.00% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 4 0.08% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 5 0.10% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 7 0.14% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 1 0.02% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 2 0.04% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 7 0.14% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 21 0.43% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 22 0.45% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 9 0.18% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 10 0.20% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.06% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.04% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.06% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.06% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 19 0.39% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 9 0.18% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 5 0.10% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 13 0.26% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 3 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 5 0.10% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 8 0.16% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 3 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::816-831 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4906 # Writes before turning the bus around for reads +system.physmem.totQLat 2145475500 # Total ticks spent queuing +system.physmem.totMemAccLat 9735100500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5300.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24051.20 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24050.35 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -259,71 +278,71 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing -system.physmem.readRowHits 363622 # Number of row buffer hits during reads -system.physmem.writeRowHits 110075 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes -system.physmem.avgGap 3342790.44 # Average gap between requests +system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing +system.physmem.readRowHits 363650 # Number of row buffer hits during reads +system.physmem.writeRowHits 109622 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.25 # Row buffer hit rate for writes +system.physmem.avgGap 3343083.38 # Average gap between requests system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 238979160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130395375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 431146800 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 239016960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130416000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577401800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 430058160 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60577818750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1079167773000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1265384883765 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.517324 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1795079851716 # Time in different power states +system.physmem_0.actBackEnergy 60604997490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1079143932000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1265387035290 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.518464 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1795039940480 # Time in different power states system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29080199534 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29120110770 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250833240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136863375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 435132000 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579882200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 433434240 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61600331205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1078270840500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1265535111000 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.596923 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1793587329216 # Time in different power states +system.physmem_1.actBackEnergy 61665698520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1078213500750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1265541051285 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.600071 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1793490285480 # Time in different power states system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30572735784 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30669779520 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15007833 # Number of BP lookups -system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9968116 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits +system.cpu.branchPred.lookups 15009390 # Number of BP lookups +system.cpu.branchPred.condPredicted 13017239 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 373223 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9937559 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5199343 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.204960 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.320122 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 808599 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32086 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9242504 # DTB read hits -system.cpu.dtb.read_misses 17824 # DTB read misses +system.cpu.dtb.read_hits 9244571 # DTB read hits +system.cpu.dtb.read_misses 17796 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766347 # DTB read accesses -system.cpu.dtb.write_hits 6386002 # DTB write hits -system.cpu.dtb.write_misses 2322 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298454 # DTB write accesses -system.cpu.dtb.data_hits 15628506 # DTB hits -system.cpu.dtb.data_misses 20146 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064801 # DTB accesses -system.cpu.itb.fetch_hits 4019475 # ITB hits -system.cpu.itb.fetch_misses 6849 # ITB misses -system.cpu.itb.fetch_acv 693 # ITB acv -system.cpu.itb.fetch_accesses 4026324 # ITB accesses +system.cpu.dtb.read_accesses 766653 # DTB read accesses +system.cpu.dtb.write_hits 6387559 # DTB write hits +system.cpu.dtb.write_misses 2314 # DTB write misses +system.cpu.dtb.write_acv 160 # DTB write access violations +system.cpu.dtb.write_accesses 298430 # DTB write accesses +system.cpu.dtb.data_hits 15632130 # DTB hits +system.cpu.dtb.data_misses 20110 # DTB misses +system.cpu.dtb.data_acv 371 # DTB access violations +system.cpu.dtb.data_accesses 1065083 # DTB accesses +system.cpu.itb.fetch_hits 4016391 # ITB hits +system.cpu.itb.fetch_misses 6902 # ITB misses +system.cpu.itb.fetch_acv 656 # ITB acv +system.cpu.itb.fetch_accesses 4023293 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -336,39 +355,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 180833533 # number of cpu cycles simulated +system.cpu.numCycles 180739367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56128524 # Number of instructions committed -system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2493054 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593535393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.221776 # CPI: cycles per instruction -system.cpu.ipc 0.310388 # IPC: instructions per cycle +system.cpu.committedInsts 56138893 # Number of instructions committed +system.cpu.committedOps 56138893 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2514465 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5513 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593619217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.219504 # CPI: cycles per instruction +system.cpu.ipc 0.310607 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211474 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105866 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182688 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1834551053500 97.21% 97.21% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51875765500 2.75% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1834553179500 97.21% 97.21% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80704500 0.00% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 676355500 0.04% 97.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51868058000 2.75% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1887178297500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693547 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814930 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -404,40 +423,40 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4170 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175546 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175529 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192427 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches +system.cpu.kern.callpal::total 192412 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5872 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 system.cpu.kern.mode_good::user 1739 -system.cpu.kern.mode_good::idle 167 -system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 168 +system.cpu.kern.mode_switch_good::kernel 0.324762 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36591863000 1.94% 1.94% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4134622500 0.22% 2.16% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1846456980000 97.84% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4171 # number of times the context was actually changed -system.cpu.tickCycles 84552243 # Number of cycles that the object actually ticked -system.cpu.idleCycles 96281290 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395323 # number of replacements +system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393074 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36563872500 1.94% 1.94% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4128201000 0.22% 2.16% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1846486214000 97.84% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4173 # number of times the context was actually changed +system.cpu.tickCycles 84425844 # Number of cycles that the object actually ticked +system.cpu.idleCycles 96313523 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395605 # number of replacements system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13774277 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395835 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.868127 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13777018 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1396117 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.868097 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy @@ -447,72 +466,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63660728 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63660728 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7815432 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815432 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13392427 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13392427 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13392427 # number of overall hits -system.cpu.dcache.overall_hits::total 13392427 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201537 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201537 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1774786 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1774786 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1774786 # number of overall misses -system.cpu.dcache.overall_misses::total 1774786 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999736250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32999736250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461890056 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22461890056 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55461626306 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55461626306 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55461626306 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55461626306 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9016969 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9016969 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15167213 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15167213 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15167213 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15167213 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.602630 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.602630 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39183.478830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39183.478830 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31249.754227 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31249.754227 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63673578 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63673578 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7816852 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816852 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5578390 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5578390 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182745 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182745 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198996 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198996 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13395242 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13395242 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13395242 # number of overall hits +system.cpu.dcache.overall_hits::total 13395242 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201883 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201883 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573228 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573228 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17271 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17271 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1775111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1775111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1775111 # number of overall misses +system.cpu.dcache.overall_misses::total 1775111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33009196500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33009196500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22459728804 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22459728804 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231661750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 231661750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55468925304 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55468925304 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55468925304 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55468925304 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9018735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9018735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151618 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151618 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200016 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200016 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198996 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198996 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15170353 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15170353 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15170353 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15170353 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133265 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133265 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093183 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093183 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086348 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086348 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117012 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117012 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117012 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117012 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.567267 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.567267 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39181.143985 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39181.143985 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.337386 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.337386 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31248.144653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31248.144653 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -521,129 +540,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838171 # number of writebacks -system.cpu.dcache.writebacks::total 838171 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127108 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268996 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 268996 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838424 # number of writebacks +system.cpu.dcache.writebacks::total 838424 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127263 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127263 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268960 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 268960 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 396104 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074429 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17194 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378682 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378682 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378682 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378682 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 396223 # 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number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378888 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237642841 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237642841 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893212500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893212500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229479000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229479000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383426 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383426 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141939 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141939 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67924.470932 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.485912 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.733584 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.130387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.130387 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192823.448773 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192823.448773 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196820.095644 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196820.095644 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195146.474107 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195146.474107 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1115769250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16346505000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17462274250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 421016 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 421016 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7497021141 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7497021141 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1115769250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843526141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24959295391 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1115769250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843526141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24959295391 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336297500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336297500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892281000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892281000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3228578500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3228578500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249288 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113145 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141946 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141946 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67840.290022 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60055.935603 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60499.503698 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23389.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23389.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64262.751719 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64262.751719 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192827.922078 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192827.922078 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196723.256056 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196723.256056 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195092.059943 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195092.059943 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2558467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558434 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558177 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558144 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304274 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304274 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6582650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236451804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2918365 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6582355 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93385664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143064988 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236450652 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41986 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3752130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011131 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104915 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3752110 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011132 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104918 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3710365 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41765 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3710343 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41767 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3752130 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2698163499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3752110 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698405000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2193277408 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2192449154 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194687409 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2195119407 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -970,23 +989,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242092694 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242104189 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024001 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.302259 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.302269 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1729989085000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.302259 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081391 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081391 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729988196000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.302269 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081392 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081392 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1002,8 +1021,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775999311 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8775999311 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8768796805 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8768796805 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles @@ -1026,17 +1045,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211205.220230 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211205.220230 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211031.883062 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211031.883062 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73059 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 73108 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10002 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9982 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.304439 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.323983 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1052,8 +1071,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6615295311 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6615295311 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6608090807 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6608090807 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles @@ -1068,59 +1087,59 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159205.220230 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159205.220230 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159031.834978 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159031.834978 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295757 # Transaction distribution -system.membus.trans_dist::ReadResp 295741 # Transaction distribution +system.membus.trans_dist::ReadReq 295738 # Transaction distribution +system.membus.trans_dist::ReadResp 295722 # Transaction distribution system.membus.trans_dist::WriteReq 9619 # Transaction distribution system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118100 # Transaction distribution +system.membus.trans_dist::Writeback 118066 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 161 # Transaction distribution -system.membus.trans_dist::UpgradeResp 161 # Transaction distribution -system.membus.trans_dist::ReadExReq 116519 # Transaction distribution -system.membus.trans_dist::ReadExResp 116519 # Transaction distribution +system.membus.trans_dist::UpgradeReq 159 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159 # Transaction distribution +system.membus.trans_dist::ReadExReq 116521 # Transaction distribution +system.membus.trans_dist::ReadExResp 116521 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886949 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886877 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920079 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920007 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044883 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044811 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855260 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36172316 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 581756 # Request fanout histogram +system.membus.snoop_fanout::samples 581705 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581756 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581705 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581756 # Request fanout histogram -system.membus.reqLayer0.occupancy 30242500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 581705 # Request fanout histogram +system.membus.reqLayer0.occupancy 29342000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1230317312 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1229889311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160772841 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160670093 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 42495999 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |