diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 4685 insertions, 4718 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index c02ff892c..fcaff51da 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906049 # Number of seconds simulated -sim_ticks 1906048606500 # Number of ticks simulated -final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906052 # Number of seconds simulated +sim_ticks 1906052165500 # Number of ticks simulated +final_tick 1906052165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 268534 # Simulator instruction rate (inst/s) -host_op_rate 268534 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9116285517 # Simulator tick rate (ticks/s) -host_mem_usage 332204 # Number of bytes of host memory used -host_seconds 209.08 # Real time elapsed on the host -sim_insts 56145568 # Number of instructions simulated -sim_ops 56145568 # Number of ops (including micro ops) simulated +host_inst_rate 263346 # Simulator instruction rate (inst/s) +host_op_rate 263346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8940174363 # Simulator tick rate (ticks/s) +host_mem_usage 335264 # Number of bytes of host memory used +host_seconds 213.20 # Real time elapsed on the host +sim_insts 56145499 # Number of instructions simulated +sim_ops 56145499 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858688 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25904384 # Number of bytes read from this memory +system.physmem.bytes_read::total 25904320 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1044672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1044672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7563136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7563136 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7563072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7563072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 16323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388417 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404756 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118174 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118174 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 548083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13042035 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404755 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118173 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 548082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13041977 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13590621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3967966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3967966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3967966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13042035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13590562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 548082 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 548082 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3967925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3967925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3967925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 548082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13041977 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17558587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404756 # Number of read requests accepted -system.physmem.writeReqs 118174 # Number of write requests accepted -system.physmem.readBursts 404756 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118174 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25897280 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17558487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404755 # Number of read requests accepted +system.physmem.writeReqs 118173 # Number of write requests accepted +system.physmem.readBursts 404755 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25897216 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7561536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25904384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7563136 # Total written bytes from the system interface side +system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25904320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7563072 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303809 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25477 # Per bank write bursts system.physmem.perBankRdBursts::1 25704 # Per bank write bursts system.physmem.perBankRdBursts::2 25816 # Per bank write bursts -system.physmem.perBankRdBursts::3 25780 # Per bank write bursts +system.physmem.perBankRdBursts::3 25781 # Per bank write bursts system.physmem.perBankRdBursts::4 25083 # Per bank write bursts -system.physmem.perBankRdBursts::5 25011 # Per bank write bursts +system.physmem.perBankRdBursts::5 25010 # Per bank write bursts system.physmem.perBankRdBursts::6 24709 # Per bank write bursts system.physmem.perBankRdBursts::7 24576 # Per bank write bursts -system.physmem.perBankRdBursts::8 25197 # Per bank write bursts +system.physmem.perBankRdBursts::8 25196 # Per bank write bursts system.physmem.perBankRdBursts::9 25297 # Per bank write bursts system.physmem.perBankRdBursts::10 25389 # Per bank write bursts system.physmem.perBankRdBursts::11 25021 # Per bank write bursts -system.physmem.perBankRdBursts::12 24535 # Per bank write bursts +system.physmem.perBankRdBursts::12 24534 # Per bank write bursts system.physmem.perBankRdBursts::13 25530 # Per bank write bursts system.physmem.perBankRdBursts::14 25795 # Per bank write bursts -system.physmem.perBankRdBursts::15 25725 # Per bank write bursts +system.physmem.perBankRdBursts::15 25726 # Per bank write bursts system.physmem.perBankWrBursts::0 7822 # Per bank write bursts system.physmem.perBankWrBursts::1 7672 # Per bank write bursts system.physmem.perBankWrBursts::2 8075 # Per bank write bursts -system.physmem.perBankWrBursts::3 7744 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts system.physmem.perBankWrBursts::4 7196 # Per bank write bursts system.physmem.perBankWrBursts::5 7016 # Per bank write bursts system.physmem.perBankWrBursts::6 6702 # Per bank write bursts system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7310 # Per bank write bursts +system.physmem.perBankWrBursts::8 7309 # Per bank write bursts system.physmem.perBankWrBursts::9 6908 # Per bank write bursts -system.physmem.perBankWrBursts::10 7272 # Per bank write bursts +system.physmem.perBankWrBursts::10 7271 # Per bank write bursts system.physmem.perBankWrBursts::11 7002 # Per bank write bursts system.physmem.perBankWrBursts::12 7086 # Per bank write bursts system.physmem.perBankWrBursts::13 7981 # Per bank write bursts system.physmem.perBankWrBursts::14 7993 # Per bank write bursts -system.physmem.perBankWrBursts::15 7943 # Per bank write bursts +system.physmem.perBankWrBursts::15 7947 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1906039923500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1906043365500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404756 # Read request sizes (log2) +system.physmem.readPktSize::6 404755 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118174 # Write request sizes (log2) +system.physmem.writePktSize::6 118173 # Write request sizes (log2) system.physmem.rdQLenPdf::0 402408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -148,124 +148,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 519.546832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.268868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 407.153797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14837 23.04% 23.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11098 17.23% 40.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4944 7.68% 47.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3257 5.06% 53.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2526 3.92% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1968 3.06% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4176 6.48% 66.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1357 2.11% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20237 31.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64400 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5299 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 519.089377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 317.985274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 407.069012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14849 23.04% 23.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11122 17.25% 40.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4951 7.68% 47.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3330 5.17% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2494 3.87% 57.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1955 3.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4176 6.48% 66.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1342 2.08% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20238 31.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64457 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.462207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2902.463532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5289 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5302 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.283855 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.921998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.156721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4666 88.00% 88.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 22 0.41% 88.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 20 0.38% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 187 3.53% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 6 0.11% 92.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.47% 92.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.81% 93.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 93.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.15% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.34% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 6 0.11% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 18 0.34% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.47% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 27 0.51% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.04% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 172 3.24% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.13% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.06% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 7 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 8 0.15% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads -system.physmem.totQLat 2637486000 # Total ticks spent queuing -system.physmem.totMemAccLat 10224579750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6518.02 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.326531 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.072850 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.540172 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4687 88.57% 88.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.64% 89.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 32 0.60% 89.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 42 0.79% 90.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 211 3.99% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 8 0.15% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 13 0.25% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 25 0.47% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 188 3.55% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.06% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 3 0.06% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.09% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 11 0.21% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.17% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads +system.physmem.totQLat 2635925000 # Total ticks spent queuing +system.physmem.totMemAccLat 10223000000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6514.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25268.02 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25264.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s @@ -275,71 +263,71 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing -system.physmem.readRowHits 362820 # Number of row buffer hits during reads -system.physmem.writeRowHits 95574 # Number of row buffer hits during writes +system.physmem.avgWrQLen 26.36 # Average write queue length when enqueuing +system.physmem.readRowHits 362809 # Number of row buffer hits during reads +system.physmem.writeRowHits 95530 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes -system.physmem.avgGap 3644923.65 # Average gap between requests -system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 237573000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 129628125 # Energy for precharge commands per rank (pJ) +system.physmem.writeRowHitRate 80.84 # Row buffer hit rate for writes +system.physmem.avgGap 3644944.17 # Average gap between requests +system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238124880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 129929250 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67955758245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1084015546500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278788854350 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.912874 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1803098707000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states +system.physmem_0.writeEnergy 380084400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67910384250 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084060020000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278789321900 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.910378 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1803172860750 # Time in different power states +system.physmem_0.memoryStateTime::REF 63647220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39297448000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39230820500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249291000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136021875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68412640320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1083614781000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278871129755 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.956034 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1802432810250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states +system.physmem_1.actEnergy 249170040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135955875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579406400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385540560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68468592375 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1083570372000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278882999570 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.959521 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1802360809750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63647220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 39963358500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 40042885250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15009028 # Number of BP lookups -system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370758 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9666577 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5199223 # Number of BTB hits +system.cpu.branchPred.lookups 15006509 # Number of BP lookups +system.cpu.branchPred.condPredicted 13016597 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 371031 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9764467 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5201318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.785564 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807911 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 31459 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.267813 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807808 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31462 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9243045 # DTB read hits -system.cpu.dtb.read_misses 17179 # DTB read misses +system.cpu.dtb.read_hits 9242631 # DTB read hits +system.cpu.dtb.read_misses 17134 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 765860 # DTB read accesses -system.cpu.dtb.write_hits 6388437 # DTB write hits +system.cpu.dtb.read_accesses 765515 # DTB read accesses +system.cpu.dtb.write_hits 6388389 # DTB write hits system.cpu.dtb.write_misses 2336 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298458 # DTB write accesses -system.cpu.dtb.data_hits 15631482 # DTB hits -system.cpu.dtb.data_misses 19515 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064318 # DTB accesses -system.cpu.itb.fetch_hits 4012772 # ITB hits -system.cpu.itb.fetch_misses 6839 # ITB misses -system.cpu.itb.fetch_acv 666 # ITB acv -system.cpu.itb.fetch_accesses 4019611 # ITB accesses +system.cpu.dtb.write_acv 160 # DTB write access violations +system.cpu.dtb.write_accesses 298460 # DTB write accesses +system.cpu.dtb.data_hits 15631020 # DTB hits +system.cpu.dtb.data_misses 19470 # DTB misses +system.cpu.dtb.data_acv 371 # DTB access violations +system.cpu.dtb.data_accesses 1063975 # DTB accesses +system.cpu.itb.fetch_hits 4014011 # ITB hits +system.cpu.itb.fetch_misses 6826 # ITB misses +system.cpu.itb.fetch_acv 642 # ITB acv +system.cpu.itb.fetch_accesses 4020837 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -352,39 +340,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 221706697 # number of cpu cycles simulated +system.cpu.numCycles 221712638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56145568 # Number of instructions committed -system.cpu.committedOps 56145568 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2506376 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5532 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3590390516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.948784 # CPI: cycles per instruction -system.cpu.ipc 0.253243 # IPC: instructions per cycle +system.cpu.committedInsts 56145499 # Number of instructions committed +system.cpu.committedOps 56145499 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2504937 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5531 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3590391693 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.948894 # CPI: cycles per instruction +system.cpu.ipc 0.253235 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211538 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211539 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74805 40.93% 40.93% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105906 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182748 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105907 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182749 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837271633000 96.39% 96.39% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 67985179000 3.57% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1837274169000 96.39% 96.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 83596500 0.00% 96.40% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 707455500 0.04% 96.43% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 67985922500 3.57% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1906051143500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693436 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814860 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814855 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -423,7 +411,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175581 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175582 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -432,103 +420,103 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192472 # number of callpals executed +system.cpu.kern.callpal::total 192473 # number of callpals executed system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.324370 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324541 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392706 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 38725166000 2.03% 2.03% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4529345500 0.24% 2.27% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862796622000 97.73% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 84511215 # Number of cycles that the object actually ticked -system.cpu.idleCycles 137195482 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 84517271 # Number of cycles that the object actually ticked +system.cpu.idleCycles 137195367 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1395430 # number of replacements system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13774435 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.867732 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.867484 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63671171 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63671171 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182827 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182827 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63669791 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63669791 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576828 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576828 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182828 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199029 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199029 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13392891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13392891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13392891 # number of overall hits -system.cpu.dcache.overall_hits::total 13392891 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201631 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201631 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 575205 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 575205 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17224 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17224 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1776836 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses -system.cpu.dcache.overall_misses::total 1776836 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974912500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 46974912500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956321000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33956321000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80931233500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80931233500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80931233500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80931233500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152051 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200051 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200051 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13392545 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392545 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392545 # number of overall hits +system.cpu.dcache.overall_hits::total 13392545 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201618 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 575220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 575220 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17222 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17222 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776838 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776838 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776838 # number of overall misses +system.cpu.dcache.overall_misses::total 1776838 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46968047500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46968047500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964546500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33964546500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 234897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80932594000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80932594000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80932594000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80932594000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9017335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9017335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152048 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152048 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200050 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200050 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15169727 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15169727 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15169727 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15169727 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093498 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093498 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086098 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086098 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117130 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45547.947869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45547.947869 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 15169383 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15169383 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15169383 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15169383 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133256 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133256 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093501 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093501 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117133 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117133 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117133 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117133 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39087.336824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39087.336824 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59046.184938 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59046.184938 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13639.385669 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13639.385669 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45548.662287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45548.662287 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,84 +525,84 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838232 # number of writebacks -system.cpu.dcache.writebacks::total 838232 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127276 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127276 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270800 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270800 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838230 # number of writebacks +system.cpu.dcache.writebacks::total 838230 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127262 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127262 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270814 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 270814 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 398076 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 398076 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 398076 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 398076 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074355 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074355 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304405 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304405 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17221 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17221 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378760 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378760 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378760 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378760 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074356 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074356 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304406 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378762 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378762 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378762 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378762 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272477000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272477000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217466000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217466000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089868500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61089868500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089868500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61089868500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529366500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529366500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691875000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691875000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119139 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119139 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43812536500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43812536500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17276327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17276327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217413000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217413000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61088864000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61088864000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61088864000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61088864000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529368000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529368000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162483000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162483000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691851000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691851000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119143 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119143 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049480 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086083 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086083 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090889 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090889 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40784.835087 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40784.835087 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.765083 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.765083 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224699.553200 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224699.553200 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222966.239884 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222966.239884 # average overall mshr uncacheable latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086073 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086073 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090891 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090891 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090891 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090891 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40780.278139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40780.278139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56754.227906 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56754.227906 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12626.342993 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12626.342993 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.040664 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.040664 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.040664 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.040664 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.715316 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.715316 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224696.903574 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224696.903574 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222964.790434 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222964.790434 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1460396 # number of replacements -system.cpu.icache.tags.tagsinuse 508.105648 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18947783 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1460907 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.969876 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1460482 # number of replacements +system.cpu.icache.tags.tagsinuse 508.105568 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18950550 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1460993 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.971007 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 50119711500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.105648 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 508.105568 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -622,44 +610,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 103 system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21869952 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21869952 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18947786 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18947786 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18947786 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18947786 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18947786 # number of overall hits -system.cpu.icache.overall_hits::total 18947786 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1461083 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1461083 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1461083 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1461083 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1461083 # number of overall misses -system.cpu.icache.overall_misses::total 1461083 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009954000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21009954000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21009954000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21009954000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21009954000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21009954000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20408869 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20408869 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20408869 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20408869 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20408869 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20408869 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071591 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071591 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071591 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071591 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071591 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071591 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.712857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14379.712857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14379.712857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14379.712857 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21872887 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21872887 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18950553 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18950553 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18950553 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18950553 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18950553 # number of overall hits +system.cpu.icache.overall_hits::total 18950553 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1461167 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1461167 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1461167 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1461167 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1461167 # number of overall misses +system.cpu.icache.overall_misses::total 1461167 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009920000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21009920000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21009920000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21009920000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21009920000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21009920000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20411720 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20411720 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20411720 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20411720 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20411720 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20411720 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071585 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071585 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071585 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071585 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071585 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071585 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14378.862923 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14378.862923 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14378.862923 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14378.862923 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14378.862923 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14378.862923 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -668,147 +656,147 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1460396 # number of writebacks -system.cpu.icache.writebacks::total 1460396 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1461083 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1461083 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1461083 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1461083 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1461083 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1461083 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548871000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19548871000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548871000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19548871000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548871000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19548871000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071591 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071591 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071591 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.712857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.712857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1460482 # number of writebacks +system.cpu.icache.writebacks::total 1460482 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1461167 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1461167 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1461167 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1461167 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1461167 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1461167 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548753000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19548753000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548753000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19548753000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548753000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19548753000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071585 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071585 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071585 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13378.862923 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13378.862923 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13378.862923 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13378.862923 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13378.862923 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13378.862923 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 339568 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65260.797416 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4999517 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404730 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.352722 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 339567 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65260.796606 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4999675 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404729 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.353142 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 9687465000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251440 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150100 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 54046.207258 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.432786 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.156561 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.824680 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087347 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087348 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.083773 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.995801 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2929 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55509 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5613 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2925 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55513 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46396433 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46396433 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 838232 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 838232 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1459802 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1459802 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 46397707 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 46397707 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 838230 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 838230 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1459876 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1459876 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187755 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187755 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1444697 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1444697 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819338 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 819338 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1444697 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1007093 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2451790 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1444697 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1007093 # number of overall hits -system.cpu.l2cache.overall_hits::total 2451790 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116659 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116659 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187761 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187761 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1444783 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1444783 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819335 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 819335 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1444783 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1007096 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2451879 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1444783 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1007096 # number of overall hits +system.cpu.l2cache.overall_hits::total 2451879 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116656 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116656 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16324 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 16324 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272207 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 272207 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272208 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 272208 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 16324 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388866 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405190 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388864 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405188 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 16324 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388866 # number of overall misses -system.cpu.l2cache.overall_misses::total 405190 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 404000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 404000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837606000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14837606000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2142680000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2142680000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680454000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680454000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2142680000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48518060000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50660740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2142680000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48518060000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50660740000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 838232 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 838232 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1459802 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1459802 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1461021 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1461021 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091545 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1091545 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1461021 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1395959 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2856980 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1461021 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1395959 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2856980 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383225 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383225 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011173 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011173 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249378 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249378 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011173 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278565 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141825 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011173 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278565 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141825 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.838058 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.838058 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131259.495222 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131259.495222 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.035572 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.035572 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125029.591056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125029.591056 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 388864 # number of overall misses +system.cpu.l2cache.overall_misses::total 405188 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 397000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 397000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14841518500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14841518500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2141533000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2141533000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33675448500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33675448500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2141533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48516967000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50658500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2141533000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48516967000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50658500000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 838230 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 838230 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1459876 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1459876 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304417 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304417 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1461107 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1461107 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091543 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1091543 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1461107 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1395960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2857067 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1461107 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1395960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2857067 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809524 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383211 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383211 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011172 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011172 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249379 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249379 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011172 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278564 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141820 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011172 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278564 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141820 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23352.941176 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23352.941176 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127224.647682 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127224.647682 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131189.230581 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131189.230581 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123712.192515 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123712.192515 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131189.230581 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124765.900160 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125024.679902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131189.230581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124765.900160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125024.679902 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -817,129 +805,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76662 # number of writebacks -system.cpu.l2cache.writebacks::total 76662 # number of writebacks -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116659 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116659 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 76661 # number of writebacks +system.cpu.l2cache.writebacks::total 76661 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116656 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116656 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16324 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16324 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272207 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272207 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272208 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272208 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 16324 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388866 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405190 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388864 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405188 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 16324 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388866 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405190 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388864 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405188 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13671016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13671016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1979440000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1979440000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960462500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960462500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1979440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631478500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46610918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1979440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631478500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46610918500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442671000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442671000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494502500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494502500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011173 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249378 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249378 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141825 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1175000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1175000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13674958500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13674958500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978293000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978293000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30955575000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30955575000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978293000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44630533500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46608826500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978293000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44630533500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46608826500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442672500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442672500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494478500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494478500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383211 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383211 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011172 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249379 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249379 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141820 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141820 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69117.647059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69117.647059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117224.647682 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117224.647682 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121189.230581 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121189.230581 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113720.298448 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113720.298448 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.758869 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.758869 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213196.799667 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213196.799667 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211044.721585 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211044.721585 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1248 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5713060 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856101 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1990 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1247 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2559702 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559783 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9624 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 956425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1459802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 818923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 956411 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1460482 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 820279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461167 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4381906 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8601216 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186932672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041565 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 329974237 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 423215 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3296619 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001032 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032108 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4382756 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4220664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8603420 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186981696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041437 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 330023133 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 423201 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3296691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001034 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032145 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3293217 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3402 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3293281 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3410 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3296619 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5168164000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3296691 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5168333000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191892463 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2192017465 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105680997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105681496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -983,39 +971,39 @@ system.iobus.pkt_size_system.bridge.master::total 44381 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5419000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 784500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 786000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 186500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 186000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14813500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14810500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5936500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215092991 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215720167 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.290814 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.290842 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1748612865000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.290814 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080676 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080676 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1748612862000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.290842 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080678 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080678 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1029,14 +1017,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21944383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21944383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429292608 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5429292608 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21944383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21944383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21944383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21944383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244742784 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5244742784 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1053,19 +1041,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126846.144509 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126846.144509 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130662.606084 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130662.606084 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126846.144509 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126846.144509 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 77 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126221.187524 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126221.187524 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.833333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1079,14 +1067,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13294383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351692608 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3351692608 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13294383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13294383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13294383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13294383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165341974 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165341974 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1095,63 +1083,62 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76846.144509 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80662.606084 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80662.606084 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.848816 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.848816 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6934 # Transaction distribution system.membus.trans_dist::ReadResp 295622 # Transaction distribution system.membus.trans_dist::WriteReq 9624 # Transaction distribution system.membus.trans_dist::WriteResp 9624 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118174 # Transaction distribution -system.membus.trans_dist::CleanEvict 262081 # Transaction distribution -system.membus.trans_dist::UpgradeReq 178 # Transaction distribution -system.membus.trans_dist::UpgradeResp 178 # Transaction distribution -system.membus.trans_dist::ReadExReq 116499 # Transaction distribution -system.membus.trans_dist::ReadExResp 116499 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288704 # Transaction distribution -system.membus.trans_dist::BadAddressError 16 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118173 # Transaction distribution +system.membus.trans_dist::CleanEvict 262241 # Transaction distribution +system.membus.trans_dist::UpgradeReq 175 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 116498 # Transaction distribution +system.membus.trans_dist::ReadExResp 116498 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288705 # Transaction distribution +system.membus.trans_dist::BadAddressError 17 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148839 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181807 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265232 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44381 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854173 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854045 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33511901 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33511773 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 843925 # Request fanout histogram +system.membus.snoop_fanout::samples 843910 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843925 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843910 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843925 # Request fanout histogram -system.membus.reqLayer0.occupancy 29573500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843910 # Request fanout histogram +system.membus.reqLayer0.occupancy 29565500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319381154 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319337462 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160244574 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2159897250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 123211008..1b3e8deca 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922762 # Number of seconds simulated -sim_ticks 1922761887500 # Number of ticks simulated -final_tick 1922761887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.924156 # Number of seconds simulated +sim_ticks 1924156135000 # Number of ticks simulated +final_tick 1924156135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136693 # Simulator instruction rate (inst/s) -host_op_rate 136693 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4632993573 # Simulator tick rate (ticks/s) -host_mem_usage 339884 # Number of bytes of host memory used -host_seconds 415.02 # Real time elapsed on the host -sim_insts 56729467 # Number of instructions simulated -sim_ops 56729467 # Number of ops (including micro ops) simulated +host_inst_rate 131013 # Simulator instruction rate (inst/s) +host_op_rate 131013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4442767791 # Simulator tick rate (ticks/s) +host_mem_usage 340636 # Number of bytes of host memory used +host_seconds 433.10 # Real time elapsed on the host +sim_insts 56741431 # Number of instructions simulated +sim_ops 56741431 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 869760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24778624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 515712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 858624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24610432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 114304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 675520 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26268096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 869760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 972800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7882944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7882944 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13590 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387166 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8058 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26259840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 858624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 114304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 972928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7862976 # Number of bytes written to this memory +system.physmem.bytes_written::total 7862976 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10555 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410439 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123171 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123171 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 452349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12886996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 268214 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 410310 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122859 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122859 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 446234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12790247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 351073 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13661648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 452349 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 505939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4099803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4099803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4099803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 452349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12886996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 268214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13647458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 446234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505639 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4086454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4086454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4086454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 446234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12790247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 351073 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17761450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410439 # Number of read requests accepted -system.physmem.writeReqs 123171 # Number of write requests accepted -system.physmem.readBursts 410439 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123171 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26260800 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7881088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26268096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7882944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17733912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410310 # Number of read requests accepted +system.physmem.writeReqs 122859 # Number of write requests accepted +system.physmem.readBursts 410310 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122859 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26253184 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 7861568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26259840 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7862976 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 309493 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25497 # Per bank write bursts -system.physmem.perBankRdBursts::1 25956 # Per bank write bursts -system.physmem.perBankRdBursts::2 26004 # Per bank write bursts -system.physmem.perBankRdBursts::3 25724 # Per bank write bursts -system.physmem.perBankRdBursts::4 25504 # Per bank write bursts -system.physmem.perBankRdBursts::5 25939 # Per bank write bursts -system.physmem.perBankRdBursts::6 25634 # Per bank write bursts -system.physmem.perBankRdBursts::7 25247 # Per bank write bursts -system.physmem.perBankRdBursts::8 25446 # Per bank write bursts -system.physmem.perBankRdBursts::9 25836 # Per bank write bursts -system.physmem.perBankRdBursts::10 25660 # Per bank write bursts -system.physmem.perBankRdBursts::11 25037 # Per bank write bursts -system.physmem.perBankRdBursts::12 26054 # Per bank write bursts -system.physmem.perBankRdBursts::13 25864 # Per bank write bursts -system.physmem.perBankRdBursts::14 25329 # Per bank write bursts -system.physmem.perBankRdBursts::15 25594 # Per bank write bursts -system.physmem.perBankWrBursts::0 8072 # Per bank write bursts -system.physmem.perBankWrBursts::1 8040 # Per bank write bursts -system.physmem.perBankWrBursts::2 8032 # Per bank write bursts -system.physmem.perBankWrBursts::3 7672 # Per bank write bursts -system.physmem.perBankWrBursts::4 7388 # Per bank write bursts -system.physmem.perBankWrBursts::5 7843 # Per bank write bursts -system.physmem.perBankWrBursts::6 7702 # Per bank write bursts -system.physmem.perBankWrBursts::7 7083 # Per bank write bursts -system.physmem.perBankWrBursts::8 7329 # Per bank write bursts -system.physmem.perBankWrBursts::9 7600 # Per bank write bursts -system.physmem.perBankWrBursts::10 7538 # Per bank write bursts -system.physmem.perBankWrBursts::11 7420 # Per bank write bursts -system.physmem.perBankWrBursts::12 7961 # Per bank write bursts -system.physmem.perBankWrBursts::13 8153 # Per bank write bursts -system.physmem.perBankWrBursts::14 7615 # Per bank write bursts -system.physmem.perBankWrBursts::15 7694 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26222 # Per bank write bursts +system.physmem.perBankRdBursts::1 25818 # Per bank write bursts +system.physmem.perBankRdBursts::2 25998 # Per bank write bursts +system.physmem.perBankRdBursts::3 25425 # Per bank write bursts +system.physmem.perBankRdBursts::4 25236 # Per bank write bursts +system.physmem.perBankRdBursts::5 25660 # Per bank write bursts +system.physmem.perBankRdBursts::6 25903 # Per bank write bursts +system.physmem.perBankRdBursts::7 25509 # Per bank write bursts +system.physmem.perBankRdBursts::8 25730 # Per bank write bursts +system.physmem.perBankRdBursts::9 25899 # Per bank write bursts +system.physmem.perBankRdBursts::10 25820 # Per bank write bursts +system.physmem.perBankRdBursts::11 25243 # Per bank write bursts +system.physmem.perBankRdBursts::12 25580 # Per bank write bursts +system.physmem.perBankRdBursts::13 25319 # Per bank write bursts +system.physmem.perBankRdBursts::14 25297 # Per bank write bursts +system.physmem.perBankRdBursts::15 25547 # Per bank write bursts +system.physmem.perBankWrBursts::0 8465 # Per bank write bursts +system.physmem.perBankWrBursts::1 7798 # Per bank write bursts +system.physmem.perBankWrBursts::2 8098 # Per bank write bursts +system.physmem.perBankWrBursts::3 7477 # Per bank write bursts +system.physmem.perBankWrBursts::4 7191 # Per bank write bursts +system.physmem.perBankWrBursts::5 7211 # Per bank write bursts +system.physmem.perBankWrBursts::6 7415 # Per bank write bursts +system.physmem.perBankWrBursts::7 7062 # Per bank write bursts +system.physmem.perBankWrBursts::8 7370 # Per bank write bursts +system.physmem.perBankWrBursts::9 7621 # Per bank write bursts +system.physmem.perBankWrBursts::10 7713 # Per bank write bursts +system.physmem.perBankWrBursts::11 7334 # Per bank write bursts +system.physmem.perBankWrBursts::12 7954 # Per bank write bursts +system.physmem.perBankWrBursts::13 8039 # Per bank write bursts +system.physmem.perBankWrBursts::14 8051 # Per bank write bursts +system.physmem.perBankWrBursts::15 8038 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 14 # Number of times write queue was full causing retry -system.physmem.totGap 1922757529500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 1924155087500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410439 # Read request sizes (log2) +system.physmem.readPktSize::6 410310 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123171 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122859 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318040 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,199 +158,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 45 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 522.654583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.374945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 410.670236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14914 22.83% 22.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11338 17.36% 40.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5449 8.34% 48.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2879 4.41% 52.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2604 3.99% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1649 2.52% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3829 5.86% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1203 1.84% 67.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21459 32.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65324 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5559 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.810757 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2831.423020 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5556 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65042 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 524.503429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 321.000815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.854297 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14739 22.66% 22.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11347 17.45% 40.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5326 8.19% 48.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2916 4.48% 52.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2591 3.98% 56.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1650 2.54% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3760 5.78% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1191 1.83% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21522 33.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65042 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5512 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.419267 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2843.464031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5509 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5559 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5559 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.151826 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.921629 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.873132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4760 85.63% 85.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 185 3.33% 88.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.47% 89.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 178 3.20% 92.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 6 0.11% 92.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.31% 93.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 0.81% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 4 0.07% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.27% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.36% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.16% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 23 0.41% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.40% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 34 0.61% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 160 2.88% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.04% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.05% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 11 0.20% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5559 # Writes before turning the bus around for reads -system.physmem.totQLat 4493146250 # Total ticks spent queuing -system.physmem.totMemAccLat 12186740000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051625000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10950.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5512 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5512 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.285377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.129455 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.189692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4905 88.99% 88.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 46 0.83% 89.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 19 0.34% 90.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 46 0.83% 91.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 202 3.66% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 8 0.15% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 9 0.16% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 26 0.47% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 191 3.47% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.09% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 3 0.05% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 9 0.16% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.09% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 8 0.15% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5512 # Writes before turning the bus around for reads +system.physmem.totQLat 4435069250 # Total ticks spent queuing +system.physmem.totMemAccLat 12126431750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10811.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29700.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29561.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.48 # Average write queue length when enqueuing -system.physmem.readRowHits 369435 # Number of row buffer hits during reads -system.physmem.writeRowHits 98708 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.14 # Row buffer hit rate for writes -system.physmem.avgGap 3603301.16 # Average gap between requests -system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247227120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134895750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1602939000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 400671360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63448746300 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097999321250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289419132860 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.608398 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1826411929500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64205180000 # Time in different power states +system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing +system.physmem.readRowHits 369385 # Number of row buffer hits during reads +system.physmem.writeRowHits 98616 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.27 # Row buffer hit rate for writes +system.physmem.avgGap 3608902.78 # Average gap between requests +system.physmem.pageHitRate 87.79 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245503440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133955250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1605013800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 393446160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125676364320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63335469060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1098934930500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1290324682530 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.593273 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1827969159500 # Time in different power states +system.physmem_0.memoryStateTime::REF 64251720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32143098000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31933066750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246622320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134565750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597596000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397288800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62799950070 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1098568432500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289329787520 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.561935 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1827364757000 # Time in different power states -system.physmem_1.memoryStateTime::REF 64205180000 # Time in different power states +system.physmem_1.actEnergy 246214080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134343000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1594593000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 402537600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125676364320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62736550965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1099460297250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1290250900215 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.554927 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1828845452000 # Time in different power states +system.physmem_1.memoryStateTime::REF 64251720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31190256750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31056774250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16164803 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14134057 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 313974 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10204663 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5324382 # Number of BTB hits +system.cpu0.branchPred.lookups 15943421 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13949758 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 305064 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10079074 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5240379 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 52.175971 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 806868 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17359 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 51.992663 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 792227 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17177 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9175640 # DTB read hits -system.cpu0.dtb.read_misses 32141 # DTB read misses -system.cpu0.dtb.read_acv 535 # DTB read access violations -system.cpu0.dtb.read_accesses 683139 # DTB read accesses -system.cpu0.dtb.write_hits 5880520 # DTB write hits -system.cpu0.dtb.write_misses 7287 # DTB write misses -system.cpu0.dtb.write_acv 388 # DTB write access violations -system.cpu0.dtb.write_accesses 235457 # DTB write accesses -system.cpu0.dtb.data_hits 15056160 # DTB hits -system.cpu0.dtb.data_misses 39428 # DTB misses -system.cpu0.dtb.data_acv 923 # DTB access violations -system.cpu0.dtb.data_accesses 918596 # DTB accesses -system.cpu0.itb.fetch_hits 1432352 # ITB hits -system.cpu0.itb.fetch_misses 20066 # ITB misses -system.cpu0.itb.fetch_acv 603 # ITB acv -system.cpu0.itb.fetch_accesses 1452418 # ITB accesses +system.cpu0.dtb.read_hits 9007287 # DTB read hits +system.cpu0.dtb.read_misses 30074 # DTB read misses +system.cpu0.dtb.read_acv 538 # DTB read access violations +system.cpu0.dtb.read_accesses 622567 # DTB read accesses +system.cpu0.dtb.write_hits 5740520 # DTB write hits +system.cpu0.dtb.write_misses 6136 # DTB write misses +system.cpu0.dtb.write_acv 351 # DTB write access violations +system.cpu0.dtb.write_accesses 205436 # DTB write accesses +system.cpu0.dtb.data_hits 14747807 # DTB hits +system.cpu0.dtb.data_misses 36210 # DTB misses +system.cpu0.dtb.data_acv 889 # DTB access violations +system.cpu0.dtb.data_accesses 828003 # DTB accesses +system.cpu0.itb.fetch_hits 1373369 # ITB hits +system.cpu0.itb.fetch_misses 18540 # ITB misses +system.cpu0.itb.fetch_acv 561 # ITB acv +system.cpu0.itb.fetch_accesses 1391909 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -363,598 +351,596 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 147492353 # number of cpu cycles simulated +system.cpu0.numCycles 146208045 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26474452 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70295181 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16164803 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6131250 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 112660359 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1056864 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 660 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29689 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 929577 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 461648 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 350 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8123308 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 141085167 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.498246 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.734224 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26065681 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69138767 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 15943421 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6032606 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 111931288 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1030760 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 960 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 29091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 863166 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 466353 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7979260 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223234 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 139872418 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.494299 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.727987 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 127941692 90.68% 90.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 834789 0.59% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1813592 1.29% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 779670 0.55% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2595829 1.84% 94.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 572321 0.41% 95.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 651682 0.46% 95.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 825551 0.59% 96.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5070041 3.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 126942613 90.76% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 822727 0.59% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1793626 1.28% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 758856 0.54% 93.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2553230 1.83% 94.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559004 0.40% 95.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 640050 0.46% 95.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 814516 0.58% 96.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4987796 3.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 141085167 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.109598 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.476602 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21397283 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108970346 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8457985 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1766417 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 493135 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 516601 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35757 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61523415 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 108836 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 493135 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22231622 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 77943613 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19948481 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9304003 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11164311 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59421431 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 199471 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2023547 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 224227 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7186744 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39708144 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72284783 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72145352 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 129802 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34979364 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4728772 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1463848 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 211077 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12544775 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9257817 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6153108 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1360057 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1005705 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53010076 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1876155 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52220777 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 51551 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6501431 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2875308 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1291728 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 141085167 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.370137 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.087516 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 139872418 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109046 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.472879 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21051176 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108291493 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8312277 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1736520 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 480951 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 505721 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 34877 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 60486220 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 106478 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 480951 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21868372 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 77772833 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19641346 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9147803 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10961111 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58426169 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 200234 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2003921 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 229197 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7028864 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39061354 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71018610 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 70882139 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 127236 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34481529 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4579825 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1435923 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 207898 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12319734 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9087403 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6005193 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1334507 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 982358 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52110504 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1852436 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51364410 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 50265 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6320051 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2764098 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1275155 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 139872418 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.367223 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.083437 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 119616695 84.78% 84.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9300562 6.59% 91.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3865352 2.74% 94.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2730572 1.94% 96.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2821393 2.00% 98.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1375831 0.98% 99.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 902270 0.64% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 360488 0.26% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 112004 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 118742134 84.89% 84.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9166235 6.55% 91.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3802026 2.72% 94.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2678681 1.92% 96.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2780722 1.99% 98.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1354022 0.97% 99.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 885059 0.63% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 353584 0.25% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109955 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 141085167 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 139872418 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 182068 18.38% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 471621 47.60% 65.98% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 337015 34.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 178057 18.55% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 457973 47.71% 66.26% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 323912 33.74% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35835168 68.62% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56519 0.11% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28571 0.05% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9523186 18.24% 87.03% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5952100 11.40% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 819570 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3341 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35317882 68.76% 68.77% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56025 0.11% 68.88% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.88% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 27459 0.05% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1664 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9346041 18.20% 87.13% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5809377 11.31% 98.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 802621 1.56% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52220777 # Type of FU issued -system.cpu0.iq.rate 0.354058 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 990706 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018971 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 245998342 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61137250 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50831283 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 570635 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267757 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 262095 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52900146 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 307557 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 581308 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51364410 # Type of FU issued +system.cpu0.iq.rate 0.351310 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 959944 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018689 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 243048711 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60036028 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50017442 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 562736 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 263720 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 258274 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52017534 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 303479 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 574771 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1065241 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3900 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17685 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 500436 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1026959 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3812 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17061 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 487007 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18736 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 408207 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18708 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 390954 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 493135 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 74418027 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1058724 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58259520 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 116565 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9257817 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6153108 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1657861 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39988 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 817674 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17685 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 153306 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351909 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 505215 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51717296 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9230924 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 503480 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 480951 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 74383875 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 944737 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57300574 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 113056 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9087403 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6005193 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1637090 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39248 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 704660 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17061 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 148957 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 344315 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 493272 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50873166 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9059669 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 491244 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3373289 # number of nop insts executed -system.cpu0.iew.exec_refs 15132335 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8216790 # Number of branches executed -system.cpu0.iew.exec_stores 5901411 # Number of stores executed -system.cpu0.iew.exec_rate 0.350644 # Inst execution rate -system.cpu0.iew.wb_sent 51207379 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51093378 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26334208 # num instructions producing a value -system.cpu0.iew.wb_consumers 36473947 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.346414 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.722001 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 6824843 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 584427 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 463110 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 139880833 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.366966 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.256019 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3337634 # number of nop insts executed +system.cpu0.iew.exec_refs 14819622 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8093106 # Number of branches executed +system.cpu0.iew.exec_stores 5759953 # Number of stores executed +system.cpu0.iew.exec_rate 0.347951 # Inst execution rate +system.cpu0.iew.wb_sent 50383521 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50275716 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25952077 # num instructions producing a value +system.cpu0.iew.wb_consumers 35940166 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.343864 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.722091 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 6643709 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 577281 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 452311 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 138699255 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.364540 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.252346 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 121749360 87.04% 87.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7187615 5.14% 92.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3944064 2.82% 95.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2051216 1.47% 96.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1611429 1.15% 97.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 577022 0.41% 98.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 437359 0.31% 98.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 434985 0.31% 98.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1887783 1.35% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 120842585 87.13% 87.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7068214 5.10% 92.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3896866 2.81% 95.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2026273 1.46% 96.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1580895 1.14% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 566091 0.41% 98.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 426311 0.31% 98.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 427447 0.31% 98.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1864573 1.34% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 139880833 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51331530 # Number of instructions committed -system.cpu0.commit.committedOps 51331530 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 138699255 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50561379 # Number of instructions committed +system.cpu0.commit.committedOps 50561379 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13845248 # Number of memory references committed -system.cpu0.commit.loads 8192576 # Number of loads committed -system.cpu0.commit.membars 198790 # Number of memory barriers committed -system.cpu0.commit.branches 7761926 # Number of branches committed -system.cpu0.commit.fp_insts 259003 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47542487 # Number of committed integer instructions. -system.cpu0.commit.function_calls 656882 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2950502 5.75% 5.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33426097 65.12% 70.87% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55327 0.11% 70.97% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28109 0.05% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8391366 16.35% 87.38% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5658677 11.02% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 819569 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13578630 # Number of memory references committed +system.cpu0.commit.loads 8060444 # Number of loads committed +system.cpu0.commit.membars 196368 # Number of memory barriers committed +system.cpu0.commit.branches 7652854 # Number of branches committed +system.cpu0.commit.fp_insts 255352 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46813547 # Number of committed integer instructions. +system.cpu0.commit.function_calls 647795 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2921820 5.78% 5.78% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32972422 65.21% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54875 0.11% 71.10% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.10% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 26997 0.05% 71.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1664 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8256812 16.33% 87.49% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5524169 10.93% 98.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 802620 1.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51331530 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1887783 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 195948573 # The number of ROB reads -system.cpu0.rob.rob_writes 117511436 # The number of ROB writes -system.cpu0.timesIdled 525574 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6407186 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698031423 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48384795 # Number of Instructions Simulated -system.cpu0.committedOps 48384795 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 3.048320 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.048320 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.328050 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.328050 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67995096 # number of integer regfile reads -system.cpu0.int_regfile_writes 36974255 # number of integer regfile writes -system.cpu0.fp_regfile_reads 128760 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130249 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1711265 # number of misc regfile reads -system.cpu0.misc_regfile_writes 819270 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1282737 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.160385 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10524244 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1283249 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.201249 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 50561379 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1864573 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 193850877 # The number of ROB reads +system.cpu0.rob.rob_writes 115577492 # The number of ROB writes +system.cpu0.timesIdled 518122 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6335627 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3701455446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47642888 # Number of Instructions Simulated +system.cpu0.committedOps 47642888 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.068833 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.068833 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.325857 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.325857 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66867100 # number of integer regfile reads +system.cpu0.int_regfile_writes 36418674 # number of integer regfile writes +system.cpu0.fp_regfile_reads 126247 # number of floating regfile reads +system.cpu0.fp_regfile_writes 127860 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1687235 # number of misc regfile reads +system.cpu0.misc_regfile_writes 805033 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1264949 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.087207 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10332814 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1265389 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.165721 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.160385 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988595 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988595 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56891628 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56891628 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6483780 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6483780 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3678701 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3678701 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162607 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 162607 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187520 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 187520 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10162481 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10162481 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10162481 # number of overall hits -system.cpu0.dcache.overall_hits::total 10162481 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1594725 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1594725 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1768883 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1768883 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21044 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21044 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2856 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2856 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3363608 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3363608 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3363608 # number of overall misses -system.cpu0.dcache.overall_misses::total 3363608 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54836064000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54836064000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114300477543 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114300477543 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389087500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 389087500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45510000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 45510000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 169136541543 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 169136541543 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 169136541543 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 169136541543 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8078505 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8078505 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5447584 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5447584 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183651 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183651 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190376 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190376 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13526089 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13526089 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13526089 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13526089 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197403 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197403 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324710 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324710 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114587 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114587 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248676 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248676 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248676 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248676 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34385.906034 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34385.906034 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64617.319259 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64617.319259 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50284.260694 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50284.260694 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50284.260694 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50284.260694 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6995201 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 14546 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 119539 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 103 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.518149 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 141.223301 # average number of cycles each access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.087207 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988452 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988452 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 440 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.859375 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 55743901 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 55743901 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6363552 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6363552 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3619661 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3619661 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160076 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 160076 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184973 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 184973 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9983213 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9983213 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9983213 # number of overall hits +system.cpu0.dcache.overall_hits::total 9983213 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1569683 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1569683 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1696149 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1696149 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20607 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20607 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2893 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2893 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3265832 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3265832 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3265832 # number of overall misses +system.cpu0.dcache.overall_misses::total 3265832 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54492082500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54492082500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110535541459 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 110535541459 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385765500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 385765500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44605000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44605000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 165027623959 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 165027623959 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 165027623959 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 165027623959 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7933235 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7933235 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5315810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5315810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180683 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 180683 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187866 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187866 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13249045 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13249045 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13249045 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13249045 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197862 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197862 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.319076 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.319076 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114051 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114051 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015399 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015399 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246496 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.246496 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.246496 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.246496 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34715.342206 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34715.342206 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65168.532634 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65168.532634 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18720.119377 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18720.119377 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15418.250951 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15418.250951 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50531.571728 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50531.571728 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50531.571728 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50531.571728 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6758088 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 13420 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 113551 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 96 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.515883 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 139.791667 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 756067 # number of writebacks -system.cpu0.dcache.writebacks::total 756067 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579442 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 579442 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502906 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1502906 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5209 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5209 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082348 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2082348 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082348 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2082348 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015283 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1015283 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265977 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 265977 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15835 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15835 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2856 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2856 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281260 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1281260 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281260 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1281260 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10126 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10126 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17171 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17171 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43465523500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43465523500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18235926784 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18235926784 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 187455000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 187455000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42654000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42654000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61701450284 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61701450284 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61701450284 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 61701450284 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1562510000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1562510000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2299016000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2299016000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3861526000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3861526000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125677 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125677 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048825 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048825 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086223 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086223 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094725 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094725 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.239329 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.239329 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.044026 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.044026 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48156.853632 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48156.853632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48156.853632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48156.853632 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221789.921930 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221789.921930 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224886.494671 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224886.494671 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 742386 # number of writebacks +system.cpu0.dcache.writebacks::total 742386 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 562218 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 562218 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1439926 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1439926 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4884 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4884 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2002144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2002144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2002144 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2002144 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007465 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1007465 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256223 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256223 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15723 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15723 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2893 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2893 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263688 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1263688 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263688 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1263688 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10093 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10093 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17124 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17124 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43361344000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43361344000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17653250388 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17653250388 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186143500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186143500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41712000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41712000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61014594388 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61014594388 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61014594388 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61014594388 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1559676000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1559676000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293857500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293857500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3853533500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3853533500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126993 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126993 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048200 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048200 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087020 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087020 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095380 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095380 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095380 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095380 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43040.050027 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43040.050027 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68897.992717 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68897.992717 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.930230 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.930230 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14418.250951 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14418.250951 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48282.957809 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48282.957809 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48282.957809 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48282.957809 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221828.473901 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221828.473901 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227272.119291 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227272.119291 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225036.994861 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225036.994861 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 908501 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.069795 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7168696 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 909010 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.886267 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 894689 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.080310 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7039625 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 895201 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.863737 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 42372449500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.069795 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992324 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992324 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9032627 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9032627 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7168696 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7168696 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7168696 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7168696 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7168696 # number of overall hits -system.cpu0.icache.overall_hits::total 7168696 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 954611 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 954611 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 954611 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 954611 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 954611 # number of overall misses -system.cpu0.icache.overall_misses::total 954611 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14637521487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14637521487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14637521487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14637521487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14637521487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14637521487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8123307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8123307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8123307 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8123307 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8123307 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8123307 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117515 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117515 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117515 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117515 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117515 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117515 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15333.493420 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15333.493420 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15333.493420 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15333.493420 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15333.493420 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15333.493420 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8572 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.080310 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992344 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992344 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8874714 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8874714 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7039625 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7039625 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7039625 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7039625 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7039625 # number of overall hits +system.cpu0.icache.overall_hits::total 7039625 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 939633 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 939633 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 939633 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 939633 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 939633 # number of overall misses +system.cpu0.icache.overall_misses::total 939633 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14412797481 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14412797481 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14412797481 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14412797481 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14412797481 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14412797481 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7979258 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7979258 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7979258 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7979258 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7979258 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7979258 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117759 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117759 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117759 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117759 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117759 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117759 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15338.751918 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15338.751918 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15338.751918 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15338.751918 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15338.751918 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15338.751918 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9737 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 278 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 297 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.834532 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.784512 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 908501 # number of writebacks -system.cpu0.icache.writebacks::total 908501 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45291 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45291 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45291 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45291 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45291 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45291 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909320 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 909320 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 909320 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 909320 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 909320 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 909320 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12935759993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12935759993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12935759993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12935759993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12935759993 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12935759993 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111940 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.111940 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.111940 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14225.751103 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14225.751103 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14225.751103 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 894689 # number of writebacks +system.cpu0.icache.writebacks::total 894689 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44177 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44177 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 44177 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44177 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 44177 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44177 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895456 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 895456 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 895456 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 895456 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 895456 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 895456 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12742984487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12742984487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12742984487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12742984487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12742984487 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12742984487 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112223 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.112223 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.112223 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14230.720981 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14230.720981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14230.720981 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3578846 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3133511 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 63586 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2063930 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 845641 # Number of BTB hits +system.cpu1.branchPred.lookups 3770405 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3287478 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 72852 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2172402 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 929208 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 40.972368 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 169933 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4992 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 42.773299 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 184259 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 5155 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1885255 # DTB read hits -system.cpu1.dtb.read_misses 9531 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 285831 # DTB read accesses -system.cpu1.dtb.write_hits 1175917 # DTB write hits -system.cpu1.dtb.write_misses 2028 # DTB write misses -system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 108552 # DTB write accesses -system.cpu1.dtb.data_hits 3061172 # DTB hits -system.cpu1.dtb.data_misses 11559 # DTB misses -system.cpu1.dtb.data_acv 40 # DTB access violations -system.cpu1.dtb.data_accesses 394383 # DTB accesses -system.cpu1.itb.fetch_hits 516958 # ITB hits -system.cpu1.itb.fetch_misses 4674 # ITB misses -system.cpu1.itb.fetch_acv 66 # ITB acv -system.cpu1.itb.fetch_accesses 521632 # ITB accesses +system.cpu1.dtb.read_hits 2058998 # DTB read hits +system.cpu1.dtb.read_misses 11600 # DTB read misses +system.cpu1.dtb.read_acv 21 # DTB read access violations +system.cpu1.dtb.read_accesses 345698 # DTB read accesses +system.cpu1.dtb.write_hits 1317225 # DTB write hits +system.cpu1.dtb.write_misses 3094 # DTB write misses +system.cpu1.dtb.write_acv 53 # DTB write access violations +system.cpu1.dtb.write_accesses 138357 # DTB write accesses +system.cpu1.dtb.data_hits 3376223 # DTB hits +system.cpu1.dtb.data_misses 14694 # DTB misses +system.cpu1.dtb.data_acv 74 # DTB access violations +system.cpu1.dtb.data_accesses 484055 # DTB accesses +system.cpu1.itb.fetch_hits 573986 # ITB hits +system.cpu1.itb.fetch_misses 6844 # ITB misses +system.cpu1.itb.fetch_acv 105 # ITB acv +system.cpu1.itb.fetch_accesses 580830 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -967,564 +953,568 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 15151136 # number of cpu cycles simulated +system.cpu1.numCycles 16344557 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6180932 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13745317 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3578846 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1015574 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7699604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 257606 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 14 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 173727 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 62622 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.icacheStallCycles 6567420 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 14895137 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3770405 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1113467 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 8326976 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 284690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 333 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 274833 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 63331 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1537985 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 51060 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14270827 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.963176 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.372632 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 1681040 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 57489 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15400785 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.967167 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.371525 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11867377 83.16% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 153441 1.08% 84.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 242213 1.70% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 178756 1.25% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 307848 2.16% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 121777 0.85% 90.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 138851 0.97% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 186713 1.31% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1073851 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12783684 83.01% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 166452 1.08% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 261215 1.70% 85.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 200313 1.30% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 351067 2.28% 89.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 133990 0.87% 90.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 151147 0.98% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 199120 1.29% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1153797 7.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14270827 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.236210 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.907214 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5071818 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7138589 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1741534 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 196274 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 122611 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 106199 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6268 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11163667 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 19967 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 122611 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5211151 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 520290 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5613443 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1798962 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1004368 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10604371 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4257 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 67823 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18974 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 511038 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6965041 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12634725 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12576141 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52884 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5956129 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1008912 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 437815 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 40748 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1803693 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1932664 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1246799 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 224198 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 128085 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9340268 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 503829 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9138713 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20420 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1499424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 677663 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 370337 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14270827 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.640377 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.363961 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15400785 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.230683 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.911321 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5395420 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7755332 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1888719 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 226049 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 135264 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 116204 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7167 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12211095 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22842 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 135264 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5551383 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 663921 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5888186 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1958901 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1203128 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11612321 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4312 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 84745 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 20732 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 660077 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 7621170 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13919150 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13857621 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 55424 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6464282 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1156880 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 465120 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 44099 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2006629 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2105779 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1396456 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 250989 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 150424 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 10250493 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 528025 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10010931 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 21465 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1679970 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 786543 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 387236 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15400785 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.650027 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.374650 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10455091 73.26% 73.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1683189 11.79% 85.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 712225 4.99% 90.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 493511 3.46% 93.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 444759 3.12% 96.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 238311 1.67% 98.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 152079 1.07% 99.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 65820 0.46% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 25842 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11244282 73.01% 73.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1815288 11.79% 84.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 776099 5.04% 89.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 545502 3.54% 93.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 489702 3.18% 96.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 259974 1.69% 98.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 169251 1.10% 99.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 72741 0.47% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 27946 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14270827 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15400785 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22910 9.24% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 135436 54.62% 63.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 89607 36.14% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 26802 9.62% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 149738 53.73% 63.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 102168 36.66% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5683316 62.19% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16216 0.18% 62.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10845 0.12% 62.52% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.52% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.52% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.52% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1965659 21.51% 84.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1197875 13.11% 97.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 259525 2.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3957 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6209301 62.03% 62.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16861 0.17% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11959 0.12% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1978 0.02% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2148593 21.46% 83.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1341864 13.40% 97.24% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 276418 2.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9138713 # Type of FU issued -system.cpu1.iq.rate 0.603170 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 247953 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027132 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32611679 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11249940 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8808383 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 204947 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 97488 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 94992 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9273516 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 109632 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94173 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10010931 # Type of FU issued +system.cpu1.iq.rate 0.612493 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 278708 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027840 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 35509985 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 12361464 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9636562 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 212834 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 101438 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 98868 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10172012 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 113670 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 100974 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 262201 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 474 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4003 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 124065 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 300733 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 901 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4546 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 138575 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 65383 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 436 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 85477 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 122611 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 306675 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 177978 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10362316 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 27137 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1932664 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1246799 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 457137 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4115 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 173001 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4003 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 29001 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 94231 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 123232 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9024161 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1901420 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 114552 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 135264 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 341224 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 281245 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 11333478 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 30763 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2105779 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1396456 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 478482 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4958 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 275268 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4546 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 33466 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 102178 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 135644 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9885056 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2078095 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 125874 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 518219 # number of nop insts executed -system.cpu1.iew.exec_refs 3085060 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1341299 # Number of branches executed -system.cpu1.iew.exec_stores 1183640 # Number of stores executed -system.cpu1.iew.exec_rate 0.595610 # Inst execution rate -system.cpu1.iew.wb_sent 8932335 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8903375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4245423 # num instructions producing a value -system.cpu1.iew.wb_consumers 6036438 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.587637 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.703299 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1526496 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 133492 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 112683 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13989586 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.626917 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.604217 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 554960 # number of nop insts executed +system.cpu1.iew.exec_refs 3404439 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1465257 # Number of branches executed +system.cpu1.iew.exec_stores 1326344 # Number of stores executed +system.cpu1.iew.exec_rate 0.604792 # Inst execution rate +system.cpu1.iew.wb_sent 9770196 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9735430 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4636977 # num instructions producing a value +system.cpu1.iew.wb_consumers 6583946 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.595637 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.704285 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1707241 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 140789 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 123833 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 15089302 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633097 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.610231 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10816267 77.32% 77.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1467149 10.49% 87.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 531154 3.80% 91.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 320114 2.29% 93.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 241905 1.73% 95.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 101551 0.73% 96.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 91287 0.65% 97.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 103861 0.74% 97.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 316298 2.26% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11642359 77.16% 77.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1582874 10.49% 87.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 578528 3.83% 91.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 347459 2.30% 93.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 270616 1.79% 95.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 111368 0.74% 96.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 102382 0.68% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 112638 0.75% 97.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 341078 2.26% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13989586 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8770307 # Number of instructions committed -system.cpu1.commit.committedOps 8770307 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 15089302 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9552993 # Number of instructions committed +system.cpu1.commit.committedOps 9552993 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2793197 # Number of memory references committed -system.cpu1.commit.loads 1670463 # Number of loads committed -system.cpu1.commit.membars 42427 # Number of memory barriers committed -system.cpu1.commit.branches 1252873 # Number of branches committed -system.cpu1.commit.fp_insts 93374 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8120952 # Number of committed integer instructions. -system.cpu1.commit.function_calls 139980 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 429153 4.89% 4.89% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5216835 59.48% 64.38% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16050 0.18% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10839 0.12% 64.68% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1712890 19.53% 84.23% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1123256 12.81% 97.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 259525 2.96% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3062927 # Number of memory references committed +system.cpu1.commit.loads 1805046 # Number of loads committed +system.cpu1.commit.membars 44912 # Number of memory barriers committed +system.cpu1.commit.branches 1363215 # Number of branches committed +system.cpu1.commit.fp_insts 97092 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8861525 # Number of committed integer instructions. +system.cpu1.commit.function_calls 149395 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 458406 4.80% 4.80% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5679268 59.45% 64.25% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16577 0.17% 64.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 11953 0.13% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1978 0.02% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1849958 19.37% 83.93% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1258435 13.17% 97.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 276418 2.89% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8770307 # Class of committed instruction -system.cpu1.commit.bw_lim_events 316298 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 23885701 # The number of ROB reads -system.cpu1.rob.rob_writes 20870962 # The number of ROB writes -system.cpu1.timesIdled 125875 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 880309 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3829642661 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8344672 # Number of Instructions Simulated -system.cpu1.committedOps 8344672 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.815666 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.815666 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550762 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550762 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11618114 # number of integer regfile reads -system.cpu1.int_regfile_writes 6343189 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52190 # number of floating regfile reads -system.cpu1.fp_regfile_writes 51516 # number of floating regfile writes -system.cpu1.misc_regfile_reads 503472 # number of misc regfile reads -system.cpu1.misc_regfile_writes 210349 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 98962 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.970752 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2466427 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 99271 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.845393 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048837181500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.970752 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951115 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.951115 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 309 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.603516 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11541624 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11541624 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1517477 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1517477 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 889696 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 889696 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32286 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 32286 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29965 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 29965 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2407173 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2407173 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2407173 # number of overall hits -system.cpu1.dcache.overall_hits::total 2407173 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 186675 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 186675 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 194181 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 194181 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4996 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4996 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2988 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2988 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 380856 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 380856 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 380856 # number of overall misses -system.cpu1.dcache.overall_misses::total 380856 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2524860000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2524860000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9140210329 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9140210329 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 47601500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 47601500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47681500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 47681500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11665070329 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11665070329 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11665070329 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11665070329 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1704152 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1704152 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1083877 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1083877 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 37282 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 37282 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2788029 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2788029 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2788029 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2788029 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109541 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.109541 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179154 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.179154 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134006 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134006 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090675 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090675 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136604 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.136604 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136604 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.136604 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13525.431900 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13525.431900 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47070.569876 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 47070.569876 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9527.922338 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9527.922338 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15957.663989 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15957.663989 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30628.558639 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30628.558639 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30628.558639 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 30628.558639 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 543818 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1735 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 16052 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.878520 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 173.500000 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 9552993 # Class of committed instruction +system.cpu1.commit.bw_lim_events 341078 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 25912274 # The number of ROB reads +system.cpu1.rob.rob_writes 22828201 # The number of ROB writes +system.cpu1.timesIdled 132318 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 943772 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3831967714 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9098543 # Number of Instructions Simulated +system.cpu1.committedOps 9098543 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.796393 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.796393 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556671 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556671 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12770865 # number of integer regfile reads +system.cpu1.int_regfile_writes 6910748 # number of integer regfile writes +system.cpu1.fp_regfile_reads 54739 # number of floating regfile reads +system.cpu1.fp_regfile_writes 53934 # number of floating regfile writes +system.cpu1.misc_regfile_reads 528553 # number of misc regfile reads +system.cpu1.misc_regfile_writes 224621 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 116660 # number of replacements +system.cpu1.dcache.tags.tagsinuse 487.079416 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2668588 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 117172 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 22.774963 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048837209000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.079416 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951327 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.951327 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12701896 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12701896 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1640446 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1640446 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 950506 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 950506 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 34609 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 34609 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32422 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 32422 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2590952 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2590952 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2590952 # number of overall hits +system.cpu1.dcache.overall_hits::total 2590952 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 211694 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 211694 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 265779 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 265779 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5362 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5362 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3043 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3043 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 477473 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 477473 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 477473 # number of overall misses +system.cpu1.dcache.overall_misses::total 477473 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2807776500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2807776500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12432535778 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12432535778 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 52442500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 52442500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 46465500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 46465500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15240312278 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15240312278 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15240312278 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15240312278 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1852140 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1852140 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1216285 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1216285 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39971 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 39971 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35465 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 35465 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3068425 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3068425 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3068425 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3068425 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114297 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114297 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218517 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.218517 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134147 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134147 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085803 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085803 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.155608 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.155608 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.155608 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.155608 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13263.373076 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13263.373076 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46777.720505 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46777.720505 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9780.399105 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9780.399105 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15269.635228 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15269.635228 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31918.689178 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 31918.689178 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31918.689178 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 31918.689178 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 748281 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 2150 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 22290 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.570256 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 179.166667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 64059 # number of writebacks -system.cpu1.dcache.writebacks::total 64059 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 113306 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 113306 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 159042 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 159042 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 272348 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 272348 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 272348 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 272348 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73369 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 73369 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35139 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 35139 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4523 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4523 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2988 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2988 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 108508 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 108508 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 108508 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 108508 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2931 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2931 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3081 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3081 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 931066500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 931066500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1566203053 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1566203053 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38495000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38495000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44693500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44693500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2497269553 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2497269553 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2497269553 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2497269553 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30161500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30161500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 685230000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 685230000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 715391500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 715391500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043053 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043053 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032420 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032420 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121319 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121319 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090675 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090675 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038919 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.038919 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038919 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.038919 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12690.189317 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12690.189317 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44571.645551 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44571.645551 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8510.944064 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8510.944064 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14957.663989 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14957.663989 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23014.612314 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23014.612314 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23014.612314 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23014.612314 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201076.666667 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201076.666667 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 233787.103378 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 233787.103378 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 232194.579682 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 232194.579682 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 77506 # number of writebacks +system.cpu1.dcache.writebacks::total 77506 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 130194 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 130194 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 220941 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 220941 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 639 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 639 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 351135 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 351135 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 351135 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 351135 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 81500 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 81500 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 44838 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 44838 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4723 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4723 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3042 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3042 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 126338 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 126338 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 126338 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 126338 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2978 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2978 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3140 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3140 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1028731500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1028731500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2065280441 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2065280441 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40973500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40973500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43423500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43423500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3094011941 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3094011941 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3094011941 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3094011941 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32188500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32188500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 693701000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 693701000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 725889500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 725889500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044003 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044003 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.118161 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.118161 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085775 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085775 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041174 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.041174 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041174 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.041174 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12622.472393 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12622.472393 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46060.940296 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46060.940296 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8675.312302 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8675.312302 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14274.654832 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14274.654832 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24489.955049 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24489.955049 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24489.955049 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24489.955049 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198694.444444 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198694.444444 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232941.907320 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232941.907320 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231175 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231175 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 223833 # number of replacements -system.cpu1.icache.tags.tagsinuse 467.351638 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1306354 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 224343 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.823021 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1896743746500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.351638 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912796 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.912796 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1762389 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1762389 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1306354 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1306354 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1306354 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1306354 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1306354 # number of overall hits -system.cpu1.icache.overall_hits::total 1306354 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 231631 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 231631 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 231631 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 231631 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 231631 # number of overall misses -system.cpu1.icache.overall_misses::total 231631 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3331435000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3331435000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3331435000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3331435000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3331435000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3331435000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1537985 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1537985 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1537985 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1537985 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1537985 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1537985 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150607 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.150607 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150607 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.150607 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150607 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.150607 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14382.509250 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14382.509250 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14382.509250 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14382.509250 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14382.509250 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14382.509250 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 764 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 236774 # number of replacements +system.cpu1.icache.tags.tagsinuse 467.367156 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1435165 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 237286 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.048250 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1897657857500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.367156 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912826 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.912826 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1918394 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1918394 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1435165 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1435165 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1435165 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1435165 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1435165 # number of overall hits +system.cpu1.icache.overall_hits::total 1435165 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 245875 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 245875 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 245875 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 245875 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 245875 # number of overall misses +system.cpu1.icache.overall_misses::total 245875 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3543557000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3543557000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3543557000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3543557000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3543557000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3543557000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1681040 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1681040 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1681040 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1681040 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1681040 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1681040 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146264 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.146264 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146264 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.146264 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146264 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.146264 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14412.026436 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14412.026436 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14412.026436 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14412.026436 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14412.026436 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14412.026436 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 967 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.105263 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.574468 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 223833 # number of writebacks -system.cpu1.icache.writebacks::total 223833 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7227 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7227 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7227 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7227 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7227 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7227 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 224404 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 224404 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 224404 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 224404 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 224404 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 224404 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2997413500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2997413500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2997413500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2997413500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2997413500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2997413500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145908 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.145908 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.145908 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.219568 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.219568 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.219568 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 236774 # number of writebacks +system.cpu1.icache.writebacks::total 236774 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8521 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8521 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8521 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8521 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8521 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8521 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 237354 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 237354 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 237354 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 237354 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 237354 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 237354 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3178535500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3178535500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3178535500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3178535500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3178535500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3178535500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.141195 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.141195 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.141195 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13391.539641 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13391.539641 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13391.539641 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1538,12 +1528,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7371 # Transaction distribution -system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 54609 # Transaction distribution -system.iobus.trans_dist::WriteResp 54609 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7368 # Transaction distribution +system.iobus.trans_dist::ReadResp 7368 # Transaction distribution +system.iobus.trans_dist::WriteReq 54623 # Transaction distribution +system.iobus.trans_dist::WriteResp 54623 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1551,12 +1541,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40504 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40528 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1564,72 +1554,72 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73842 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735474 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12353500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73938 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12379500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 827500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 818500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14420500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14310000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5954500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5965001 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 87000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215061495 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215710405 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27447000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.507724 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.518954 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1726981783000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.507724 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031733 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031733 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1726981777000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.518954 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.032435 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.032435 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses -system.iocache.demand_misses::total 176 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 176 # number of overall misses -system.iocache.overall_misses::total 176 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22155383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22155383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5431231112 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5431231112 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22155383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22155383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22155383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22155383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 23088383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 23088383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246547022 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5246547022 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 23088383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 23088383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 23088383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 23088383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1638,40 +1628,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125882.857955 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125882.857955 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130709.258568 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130709.258568 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125882.857955 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125882.857955 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125882.857955 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125882.857955 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 131933.617143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 131933.617143 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126264.608731 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126264.608731 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 131933.617143 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131933.617143 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 131933.617143 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131933.617143 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.411765 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 0 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13355383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13355383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353631112 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3353631112 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13355383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13355383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13355383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13355383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14338383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14338383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167138735 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3167138735 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 14338383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14338383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 14338383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14338383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1680,199 +1670,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75882.857955 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80709.258568 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80709.258568 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 81933.617143 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76221.090080 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76221.090080 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81933.617143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81933.617143 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345304 # number of replacements -system.l2c.tags.tagsinuse 65190.216881 # Cycle average of tags in use -system.l2c.tags.total_refs 3990482 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410468 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.721786 # Average number of references to valid blocks. +system.l2c.tags.replacements 345132 # number of replacements +system.l2c.tags.tagsinuse 65190.773198 # Cycle average of tags in use +system.l2c.tags.total_refs 3987579 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410285 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.719047 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 11177481000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53120.456317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5260.305264 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6531.960119 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 208.754945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 68.740237 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.810554 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 53112.873337 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5260.284322 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6538.875697 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 210.626415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 68.113427 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.810438 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.080266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.099670 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003185 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001049 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994724 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1730 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6285 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6556 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50377 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38372212 # Number of tag accesses -system.l2c.tags.data_accesses 38372212 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 820126 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 820126 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 859282 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 859282 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 249 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 421 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 155330 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 22838 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 178168 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 895446 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 222750 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1118196 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 736882 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 66420 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 803302 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 895446 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 892212 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 222750 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 89258 # number of demand (read+write) hits -system.l2c.demand_hits::total 2099666 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 895446 # number of overall hits -system.l2c.overall_hits::cpu0.data 892212 # number of overall hits -system.l2c.overall_hits::cpu1.inst 222750 # number of overall hits -system.l2c.overall_hits::cpu1.data 89258 # number of overall hits -system.l2c.overall_hits::total 2099666 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2766 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1119 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3885 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 420 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 441 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114874 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7330 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122204 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13592 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1628 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15220 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 272976 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 829 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 273805 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 13592 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387850 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1628 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8159 # number of demand (read+write) misses -system.l2c.demand_misses::total 411229 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13592 # number of overall misses -system.l2c.overall_misses::cpu0.data 387850 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1628 # number of overall misses -system.l2c.overall_misses::cpu1.data 8159 # number of overall misses -system.l2c.overall_misses::total 411229 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 3922000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 17449000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21371000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2842500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 568500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3411000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 16040737500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1166717500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 17207455000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1817383500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 219865000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 2037248500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 33892904500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 116817000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 34009721500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1817383500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 49933642000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 219865000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1283534500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 53254425000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1817383500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 49933642000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 219865000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1283534500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 53254425000 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 820126 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 820126 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 859282 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 859282 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2938 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1368 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4306 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 471 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 466 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 937 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 270204 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 30168 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300372 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 909038 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 224378 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1133416 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1009858 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 67249 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1077107 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 909038 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1280062 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 224378 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 97417 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2510895 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 909038 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1280062 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 224378 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 97417 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2510895 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941457 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.817982 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.902229 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.891720 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.946352 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.918890 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.425138 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.242973 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.406842 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014952 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007256 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013428 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.270311 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.012327 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.254204 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014952 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.302993 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007256 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.083753 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.163778 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014952 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.302993 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007256 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.083753 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.163778 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1417.932032 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15593.386953 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5500.900901 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6767.857143 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1289.115646 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3961.672474 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139637.668228 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 159170.190996 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 140809.261563 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133709.792525 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135052.211302 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 133853.383706 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124160.748564 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140913.148372 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 124211.469842 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 133709.792525 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 128744.726054 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 135052.211302 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 157315.173428 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 129500.655353 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 133709.792525 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 128744.726054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 135052.211302 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 157315.173428 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 129500.655353 # average overall miss latency +system.l2c.tags.occ_percent::cpu0.data 0.099775 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003214 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001039 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65153 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3005 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4362 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5957 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51615 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994156 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 38355291 # Number of tag accesses +system.l2c.tags.data_accesses 38355291 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 819892 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 819892 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 858364 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 858364 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 165 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 438 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 47 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 77 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 148311 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 29871 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 178182 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 881771 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 235510 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1117281 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 728849 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 74394 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 803243 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 881771 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 877160 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 235510 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 104265 # number of demand (read+write) hits +system.l2c.demand_hits::total 2098706 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 881771 # number of overall hits +system.l2c.overall_hits::cpu0.data 877160 # number of overall hits +system.l2c.overall_hits::cpu1.inst 235510 # number of overall hits +system.l2c.overall_hits::cpu1.data 104265 # number of overall hits +system.l2c.overall_hits::total 2098706 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2745 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1129 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3874 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 421 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 438 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 859 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 112211 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9825 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122036 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 13418 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1804 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15222 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 272977 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 837 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 273814 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 13418 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 385188 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1804 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10662 # number of demand (read+write) misses +system.l2c.demand_misses::total 411072 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13418 # number of overall misses +system.l2c.overall_misses::cpu0.data 385188 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1804 # number of overall misses +system.l2c.overall_misses::cpu1.data 10662 # number of overall misses +system.l2c.overall_misses::total 411072 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 2600000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 16721000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 19321000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2754000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 393500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3147500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 15556825000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1578015500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 17134840500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1793058000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 243367000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 2036425000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 33886643500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 118714500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 34005358000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1793058000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 49443468500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 243367000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1696730000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 53176623500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1793058000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 49443468500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 243367000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1696730000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 53176623500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 819892 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 819892 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 858364 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 858364 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2910 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1402 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4312 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 468 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 468 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 936 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 260522 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 39696 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300218 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 895189 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 237314 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1132503 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1001826 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 75231 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1077057 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 895189 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1262348 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 237314 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 114927 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2509778 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 895189 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1262348 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 237314 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 114927 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2509778 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943299 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805278 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.898423 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.899573 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.935897 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.917735 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.430716 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.247506 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.406491 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014989 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007602 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013441 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.272479 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.011126 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.254224 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014989 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.305136 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007602 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.092772 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.163788 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014989 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.305136 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007602 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.092772 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.163788 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 947.176685 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14810.451727 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4987.351575 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6541.567696 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 898.401826 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3664.144354 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138639.037171 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 160612.264631 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 140408.080403 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133630.794455 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 134904.101996 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 133781.697543 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124137.357726 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141833.333333 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 124191.451131 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 133630.794455 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 128361.912884 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 134904.101996 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 159138.060401 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 129360.850411 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 133630.794455 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 128361.912884 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 134904.101996 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 159138.060401 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 129360.850411 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1881,8 +1871,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81651 # number of writebacks -system.l2c.writebacks::total 81651 # number of writebacks +system.l2c.writebacks::writebacks 81339 # number of writebacks +system.l2c.writebacks::total 81339 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 18 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 19 # number of ReadCleanReq MSHR hits @@ -1894,243 +1884,242 @@ system.l2c.overall_mshr_hits::cpu1.inst 18 # nu system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2766 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1119 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3885 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 420 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 441 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114874 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7330 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122204 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13591 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1610 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 15201 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272976 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 829 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 273805 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13591 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387850 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1610 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8159 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 411210 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13591 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387850 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1610 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8159 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 411210 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10126 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2931 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 13057 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17171 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3081 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 20252 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 198395000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 80293500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 278688500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29951500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 31656500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 61608000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14891997500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1093417500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 15985415000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1681342000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 201578500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1882920500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31173009000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 108527000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 31281536000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1681342000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 46065006500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 201578500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1201944500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 49149871500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1681342000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 46065006500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 201578500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1201944500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 49149871500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1474387500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28274500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1502662000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2182363000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 649671500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2832034500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3656750500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 677946000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4334696500 # number of overall MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2745 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1129 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3874 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 421 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 438 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 859 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 112211 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9825 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122036 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13417 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1786 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 15203 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272977 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 837 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 273814 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13417 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 385188 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1786 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10662 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411053 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13417 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 385188 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1786 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10662 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411053 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7193 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10093 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2978 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 13071 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17124 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3140 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 20264 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 189141000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 77954000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 267095000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 28855000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 30191500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 59046500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14434715000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1479761518 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 15914476518 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1658755004 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 223319004 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1882074008 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31166738507 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 110342008 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 31277080515 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1658755004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 45601453507 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 223319004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1590103526 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 49073631041 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1658755004 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 45601453507 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 223319004 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1590103526 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 49073631041 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1471729000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 30152500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1501881500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2177586500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 657605500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2835192000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3649315500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 687758000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4337073500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941457 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817982 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.902229 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.891720 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.946352 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.918890 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425138 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.242973 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.406842 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013412 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270311 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012327 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254204 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.302993 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.083753 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.163770 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.302993 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.083753 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.163770 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71726.319595 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71754.691689 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129637.668228 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.261563 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123868.199461 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114196.885440 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114247.497306 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118770.159856 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 119524.990881 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118770.159856 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 119524.990881 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209281.405252 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208848.088951 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212960.835129 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214037.946869 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943299 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.805278 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.898423 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.899573 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935897 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.917735 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430716 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.247506 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.406491 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013424 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.272479 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254224 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305136 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.092772 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305136 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.092772 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68903.825137 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69046.944198 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68945.534331 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68539.192399 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68930.365297 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68738.649593 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128639.037171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150611.859338 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130408.047773 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123796.224956 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114173.496328 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131830.356033 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114227.470162 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118387.523773 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 149137.453198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119385.166976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118387.523773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 149137.453198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119385.166976 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209320.011378 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186126.543210 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208797.650494 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215752.154959 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220821.188717 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216907.046133 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213111.159776 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219031.210191 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214028.498816 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 296301 # Transaction distribution -system.membus.trans_dist::WriteReq 13057 # Transaction distribution -system.membus.trans_dist::WriteResp 13057 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123171 # Transaction distribution -system.membus.trans_dist::CleanEvict 262771 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10335 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5768 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5173 # Transaction distribution -system.membus.trans_dist::ReadExReq 122191 # Transaction distribution -system.membus.trans_dist::ReadExResp 121777 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289182 # Transaction distribution +system.membus.trans_dist::ReadReq 7193 # Transaction distribution +system.membus.trans_dist::ReadResp 296309 # Transaction distribution +system.membus.trans_dist::WriteReq 13071 # Transaction distribution +system.membus.trans_dist::WriteResp 13071 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122859 # Transaction distribution +system.membus.trans_dist::CleanEvict 263080 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10389 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5858 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 122048 # Transaction distribution +system.membus.trans_dist::ReadExResp 121637 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289192 # Transaction distribution system.membus.trans_dist::BadAddressError 76 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40504 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187227 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40528 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181775 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1227883 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1352711 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73842 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31492800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31566642 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1222455 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1305892 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73938 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31464576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31538514 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34224882 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 11791 # Total snoops (count) -system.membus.snoop_fanout::samples 875399 # Request fanout histogram +system.membus.pkt_size::total 34196754 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11972 # Total snoops (count) +system.membus.snoop_fanout::samples 875257 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 875399 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875257 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 875399 # Request fanout histogram -system.membus.reqLayer0.occupancy 36670000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875257 # Request fanout histogram +system.membus.reqLayer0.occupancy 36588499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1357207403 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1355446474 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 98500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 101000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2187691105 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2176763250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69834733 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 924363 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 5063738 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2531809 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 339719 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1340 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5062297 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2530952 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 339931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1332 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1264 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2239104 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13057 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13057 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 943311 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 859282 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 775827 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10329 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5844 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16173 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301707 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301707 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1133724 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1098277 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2238586 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13071 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13071 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 942766 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1131462 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 825685 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10428 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5935 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16363 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301553 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301553 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1132810 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1098675 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 76 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2546826 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3860959 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 579596 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 310532 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7297913 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 104800384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130368640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22732288 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10357298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 268258610 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 462469 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2998699 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.119628 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.324813 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2685333 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3847367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 711442 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373868 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7618010 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114552128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128359012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30341632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12338926 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 285591698 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462928 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2998059 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.119755 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.324954 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2640250 88.05% 88.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 358173 11.94% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 274 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2639295 88.03% 88.03% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 358495 11.96% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 268 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2998699 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4501023919 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2998059 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4499211916 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 295885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1365634171 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1344759827 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1954807358 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1928238108 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 338746615 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 358125739 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 168528157 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 195506142 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2164,161 +2153,170 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184433 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65060 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1928 1.20% 41.78% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93335 58.10% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 160640 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64056 49.21% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1928 1.48% 50.79% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63870 49.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130171 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865608787500 97.03% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63996500 0.00% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 577908500 0.03% 97.06% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 88293000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56422061000 2.93% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1922761046500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6521 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 181676 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64229 40.40% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.49% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1930 1.21% 41.70% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 188 0.12% 41.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92486 58.18% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158964 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63227 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1930 1.50% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63039 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128515 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866746585000 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63847000 0.00% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 578525000 0.03% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 89345000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56353429000 2.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1923831731000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984400 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684309 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810327 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed -system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 228 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.681606 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808453 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.65% 3.65% # number of syscalls executed +system.cpu0.kern.syscall::3 16 8.33% 11.98% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.08% 14.06% # number of syscalls executed +system.cpu0.kern.syscall::6 28 14.58% 28.65% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.52% 29.17% # number of syscalls executed +system.cpu0.kern.syscall::17 8 4.17% 33.33% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.65% 36.98% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.08% 39.06% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.52% 39.58% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.56% 41.15% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.12% 44.27% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.04% 45.31% # number of syscalls executed +system.cpu0.kern.syscall::45 31 16.15% 61.46% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.56% 63.02% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.17% 67.19% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.69% 71.88% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.52% 72.40% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.12% 75.52% # number of syscalls executed +system.cpu0.kern.syscall::71 21 10.94% 86.46% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.56% 88.02% # number of syscalls executed +system.cpu0.kern.syscall::74 5 2.60% 90.62% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.52% 91.15% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.04% 92.19% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.65% 95.83% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.04% 96.88% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.04% 97.92% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.52% 98.44% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.52% 98.96% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.04% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 192 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wripir 288 0.17% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3530 2.09% 2.26% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 153808 90.93% 93.22% # number of callpals executed -system.cpu0.kern.callpal::rdps 6346 3.75% 96.97% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rti 4586 2.71% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169154 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7135 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1348 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3442 2.06% 2.23% # number of callpals executed +system.cpu0.kern.callpal::tbi 49 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 152297 91.02% 93.29% # number of callpals executed +system.cpu0.kern.callpal::rdps 6331 3.78% 97.07% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.07% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.07% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.08% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.08% # number of callpals executed +system.cpu0.kern.callpal::rti 4417 2.64% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 330 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 167317 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6879 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1175 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1347 -system.cpu0.kern.mode_good::user 1348 +system.cpu0.kern.mode_good::kernel 1175 +system.cpu0.kern.mode_good::user 1175 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.188788 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170810 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.317694 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1920558467500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2202571000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.291780 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1921452590000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2041385500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3531 # number of times the context was actually changed +system.cpu0.kern.swap_context 3443 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 55289 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17293 36.54% 36.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1926 4.07% 40.61% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27821 58.79% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 47324 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16920 47.31% 47.31% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1926 5.39% 52.69% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.79% 53.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16636 46.51% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35766 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1875921374000 97.58% 97.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 562894500 0.03% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 139598000 0.01% 97.62% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45773010000 2.38% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1922396876500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978431 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2563 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58062 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18132 36.97% 36.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1928 3.93% 40.90% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 288 0.59% 41.49% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28696 58.51% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49044 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17757 47.43% 47.43% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1928 5.15% 52.57% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 288 0.77% 53.34% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17469 46.66% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37442 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1877611262500 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 563601000 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141411000 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45839038500 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1924155313000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979318 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.597966 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.755769 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed -system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed -system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 98 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.608761 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.763437 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.75% 0.75% # number of syscalls executed +system.cpu1.kern.syscall::3 14 10.45% 11.19% # number of syscalls executed +system.cpu1.kern.syscall::6 14 10.45% 21.64% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.75% 22.39% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.22% 27.61% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.24% 29.85% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.49% 31.34% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.24% 33.58% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.24% 35.82% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.73% 39.55% # number of syscalls executed +system.cpu1.kern.syscall::45 23 17.16% 56.72% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.24% 58.96% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.49% 60.45% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.75% 61.19% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.75% 61.94% # number of syscalls executed +system.cpu1.kern.syscall::71 33 24.63% 86.57% # number of syscalls executed +system.cpu1.kern.syscall::74 11 8.21% 94.78% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.75% 95.52% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.49% 97.01% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.24% 99.25% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.75% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 134 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1060 2.16% 2.55% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 42140 86.06% 88.63% # number of callpals executed -system.cpu1.kern.callpal::rdps 2415 4.93% 93.56% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.58% # number of callpals executed -system.cpu1.kern.callpal::rti 2973 6.07% 99.65% # number of callpals executed -system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1149 2.26% 2.64% # number of callpals executed +system.cpu1.kern.callpal::tbi 4 0.01% 2.64% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.66% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43675 85.89% 88.55% # number of callpals executed +system.cpu1.kern.callpal::rdps 2435 4.79% 93.34% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.34% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.35% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.35% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.35% # number of callpals executed +system.cpu1.kern.callpal::rti 3152 6.20% 99.55% # number of callpals executed +system.cpu1.kern.callpal::callsys 185 0.36% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 41 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48967 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1257 # number of protection mode switches -system.cpu1.kern.mode_switch::user 391 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2415 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 600 -system.cpu1.kern.mode_good::user 391 -system.cpu1.kern.mode_good::idle 209 -system.cpu1.kern.mode_switch_good::kernel 0.477327 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 50850 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1515 # number of protection mode switches +system.cpu1.kern.mode_switch::user 561 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2424 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 773 +system.cpu1.kern.mode_good::user 561 +system.cpu1.kern.mode_good::idle 212 +system.cpu1.kern.mode_switch_good::kernel 0.510231 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086542 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.295348 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4412319000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 702202000 0.04% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1916962357500 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1061 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.087459 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.343556 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4865757000 0.25% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 846470000 0.04% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1918443078000 99.70% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1150 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index f6eb98841..28bcd517c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.875760 # Number of seconds simulated -sim_ticks 1875760362000 # Number of ticks simulated -final_tick 1875760362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.875758 # Number of seconds simulated +sim_ticks 1875758115500 # Number of ticks simulated +final_tick 1875758115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137394 # Simulator instruction rate (inst/s) -host_op_rate 137394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4864266040 # Simulator tick rate (ticks/s) -host_mem_usage 335280 # Number of bytes of host memory used -host_seconds 385.62 # Real time elapsed on the host -sim_insts 52982087 # Number of instructions simulated -sim_ops 52982087 # Number of ops (including micro ops) simulated +host_inst_rate 136821 # Simulator instruction rate (inst/s) +host_op_rate 136821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4844017901 # Simulator tick rate (ticks/s) +host_mem_usage 335520 # Number of bytes of host memory used +host_seconds 387.23 # Real time elapsed on the host +sim_insts 52981544 # Number of instructions simulated +sim_ops 52981544 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881024 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25840256 # Number of bytes read from this memory +system.physmem.bytes_read::total 25840192 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7524736 # Number of bytes written to this memory -system.physmem.bytes_written::total 7524736 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388766 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117574 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117574 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 510837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13264534 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403753 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 510838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13264516 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13775883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 510837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 510837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4011566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4011566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4011566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 510837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13264534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13775866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 510838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 510838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4011639 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4011639 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4011639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 510838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13264516 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403754 # Number of read requests accepted -system.physmem.writeReqs 117574 # Number of write requests accepted -system.physmem.readBursts 403754 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117574 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25832192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 7523264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25840256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7524736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17787505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403753 # Number of read requests accepted +system.physmem.writeReqs 117576 # Number of write requests accepted +system.physmem.readBursts 403753 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117576 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25832384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25840192 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7524864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303613 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25610 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25611 # Per bank write bursts system.physmem.perBankRdBursts::1 25424 # Per bank write bursts -system.physmem.perBankRdBursts::2 25555 # Per bank write bursts -system.physmem.perBankRdBursts::3 25501 # Per bank write bursts +system.physmem.perBankRdBursts::2 25556 # Per bank write bursts +system.physmem.perBankRdBursts::3 25503 # Per bank write bursts system.physmem.perBankRdBursts::4 25379 # Per bank write bursts -system.physmem.perBankRdBursts::5 24724 # Per bank write bursts +system.physmem.perBankRdBursts::5 24725 # Per bank write bursts system.physmem.perBankRdBursts::6 24941 # Per bank write bursts -system.physmem.perBankRdBursts::7 25082 # Per bank write bursts +system.physmem.perBankRdBursts::7 25083 # Per bank write bursts system.physmem.perBankRdBursts::8 24938 # Per bank write bursts -system.physmem.perBankRdBursts::9 25020 # Per bank write bursts -system.physmem.perBankRdBursts::10 25562 # Per bank write bursts +system.physmem.perBankRdBursts::9 25019 # Per bank write bursts +system.physmem.perBankRdBursts::10 25561 # Per bank write bursts system.physmem.perBankRdBursts::11 24881 # Per bank write bursts -system.physmem.perBankRdBursts::12 24459 # Per bank write bursts -system.physmem.perBankRdBursts::13 25275 # Per bank write bursts +system.physmem.perBankRdBursts::12 24458 # Per bank write bursts +system.physmem.perBankRdBursts::13 25273 # Per bank write bursts system.physmem.perBankRdBursts::14 25708 # Per bank write bursts -system.physmem.perBankRdBursts::15 25569 # Per bank write bursts -system.physmem.perBankWrBursts::0 7930 # Per bank write bursts +system.physmem.perBankRdBursts::15 25571 # Per bank write bursts +system.physmem.perBankWrBursts::0 7931 # Per bank write bursts system.physmem.perBankWrBursts::1 7523 # Per bank write bursts system.physmem.perBankWrBursts::2 7959 # Per bank write bursts -system.physmem.perBankWrBursts::3 7525 # Per bank write bursts +system.physmem.perBankWrBursts::3 7526 # Per bank write bursts system.physmem.perBankWrBursts::4 7322 # Per bank write bursts -system.physmem.perBankWrBursts::5 6662 # Per bank write bursts +system.physmem.perBankWrBursts::5 6664 # Per bank write bursts system.physmem.perBankWrBursts::6 6770 # Per bank write bursts -system.physmem.perBankWrBursts::7 6719 # Per bank write bursts +system.physmem.perBankWrBursts::7 6720 # Per bank write bursts system.physmem.perBankWrBursts::8 7147 # Per bank write bursts system.physmem.perBankWrBursts::9 6703 # Per bank write bursts -system.physmem.perBankWrBursts::10 7409 # Per bank write bursts -system.physmem.perBankWrBursts::11 6974 # Per bank write bursts -system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::10 7408 # Per bank write bursts +system.physmem.perBankWrBursts::11 6973 # Per bank write bursts +system.physmem.perBankWrBursts::12 7144 # Per bank write bursts system.physmem.perBankWrBursts::13 7893 # Per bank write bursts system.physmem.perBankWrBursts::14 8063 # Per bank write bursts system.physmem.perBankWrBursts::15 7807 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 1875755162500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 1875752798500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403754 # Read request sizes (log2) +system.physmem.readPktSize::6 403753 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117574 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 35937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23972 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117576 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 35859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24058 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -148,126 +148,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.255177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 330.514254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 411.900658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13736 22.08% 22.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10542 16.95% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4957 7.97% 47.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2726 4.38% 51.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2468 3.97% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1593 2.56% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3731 6.00% 63.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1159 1.86% 65.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21288 34.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62200 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5203 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.574092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2240.859569 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5198 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62096 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 537.164648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.293750 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 411.963299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13665 22.01% 22.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10559 17.00% 39.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4854 7.82% 46.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2778 4.47% 51.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2418 3.89% 55.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1622 2.61% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3711 5.98% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1214 1.96% 65.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21275 34.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62096 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.619423 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2241.505208 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5195 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5203 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5203 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.592927 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.087485 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.896632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4449 85.51% 85.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 153 2.94% 88.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.29% 88.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 183 3.52% 92.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7 0.13% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.40% 92.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 39 0.75% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.02% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.19% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.33% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.12% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.15% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 19 0.37% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.52% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 31 0.60% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 162 3.11% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.13% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.08% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.08% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.08% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 10 0.19% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5203 # Writes before turning the bus around for reads -system.physmem.totQLat 4177261250 # Total ticks spent queuing -system.physmem.totMemAccLat 11745286250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10349.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5200 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.606346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.258970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.077519 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4603 88.52% 88.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 36 0.69% 89.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 24 0.46% 89.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 35 0.67% 90.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 205 3.94% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.21% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 15 0.29% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 35 0.67% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 175 3.37% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.12% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 7 0.13% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 2 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 11 0.21% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 6 0.12% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.08% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.13% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::344-351 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5200 # Writes before turning the bus around for reads +system.physmem.totQLat 4180311250 # Total ticks spent queuing +system.physmem.totMemAccLat 11748392500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10356.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29099.29 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29106.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s @@ -276,72 +266,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing -system.physmem.readRowHits 363742 # Number of row buffer hits during reads -system.physmem.writeRowHits 95236 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.00 # Row buffer hit rate for writes -system.physmem.avgGap 3598032.64 # Average gap between requests -system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 232485120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126852000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577284800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378496800 # Energy for write commands per rank (pJ) +system.physmem.avgRdQLen 2.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing +system.physmem.readRowHits 363824 # Number of row buffer hits during reads +system.physmem.writeRowHits 95264 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes +system.physmem.avgGap 3598021.21 # Average gap between requests +system.physmem.pageHitRate 88.08 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232326360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126765375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577331600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378529200 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61464969315 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1071536113500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1257831356895 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.573520 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1782393910500 # Time in different power states +system.physmem_0.actBackEnergy 61450630965 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1071548691000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1257829429860 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.572492 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1782417296500 # Time in different power states system.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30725132000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30701746000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 237746880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129723000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1570966800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383233680 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 237119400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129380625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1570990200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383214240 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61443954270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1071554556000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1257835335990 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.575636 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1782423204750 # Time in different power states +system.physmem_1.actBackEnergy 61460167635 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1071540333750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1257836361210 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.576183 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1782399409250 # Time in different power states system.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30695851500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30719647000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17943792 # Number of BP lookups -system.cpu.branchPred.condPredicted 15652255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 367731 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11526736 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5853565 # Number of BTB hits +system.cpu.branchPred.lookups 17926200 # Number of BP lookups +system.cpu.branchPred.condPredicted 15634549 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 367641 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11517888 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5853508 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.782503 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 912127 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21143 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.821019 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 912312 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21142 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10250861 # DTB read hits -system.cpu.dtb.read_misses 41155 # DTB read misses -system.cpu.dtb.read_acv 533 # DTB read access violations -system.cpu.dtb.read_accesses 965519 # DTB read accesses -system.cpu.dtb.write_hits 6643163 # DTB write hits -system.cpu.dtb.write_misses 9679 # DTB write misses -system.cpu.dtb.write_acv 405 # DTB write access violations -system.cpu.dtb.write_accesses 341919 # DTB write accesses -system.cpu.dtb.data_hits 16894024 # DTB hits -system.cpu.dtb.data_misses 50834 # DTB misses -system.cpu.dtb.data_acv 938 # DTB access violations -system.cpu.dtb.data_accesses 1307438 # DTB accesses -system.cpu.itb.fetch_hits 1771509 # ITB hits -system.cpu.itb.fetch_misses 27218 # ITB misses -system.cpu.itb.fetch_acv 651 # ITB acv -system.cpu.itb.fetch_accesses 1798727 # ITB accesses +system.cpu.dtb.read_hits 10248777 # DTB read hits +system.cpu.dtb.read_misses 41124 # DTB read misses +system.cpu.dtb.read_acv 537 # DTB read access violations +system.cpu.dtb.read_accesses 965282 # DTB read accesses +system.cpu.dtb.write_hits 6643148 # DTB write hits +system.cpu.dtb.write_misses 9690 # DTB write misses +system.cpu.dtb.write_acv 398 # DTB write access violations +system.cpu.dtb.write_accesses 341994 # DTB write accesses +system.cpu.dtb.data_hits 16891925 # DTB hits +system.cpu.dtb.data_misses 50814 # DTB misses +system.cpu.dtb.data_acv 935 # DTB access violations +system.cpu.dtb.data_accesses 1307276 # DTB accesses +system.cpu.itb.fetch_hits 1767471 # ITB hits +system.cpu.itb.fetch_misses 28221 # ITB misses +system.cpu.itb.fetch_acv 656 # ITB acv +system.cpu.itb.fetch_accesses 1795692 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -354,251 +344,251 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 154312476 # number of cpu cycles simulated +system.cpu.numCycles 154296938 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29589797 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78040481 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17943792 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6765692 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115536731 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1228012 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1868 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28793 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1263154 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 470523 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8990853 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 270749 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 147505430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.529069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.785300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29565992 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 77998562 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17926200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6765820 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115499750 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1227580 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1879 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 29906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1313604 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 470747 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 522 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8986717 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269982 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 147496190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.528817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.784795 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132981412 90.15% 90.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 927735 0.63% 90.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1956667 1.33% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 905252 0.61% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2772062 1.88% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 613973 0.42% 95.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 725766 0.49% 95.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009557 0.68% 96.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5613006 3.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132977860 90.16% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 927689 0.63% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1955483 1.33% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 905427 0.61% 92.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772003 1.88% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 615447 0.42% 95.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 725348 0.49% 95.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009173 0.68% 96.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5607760 3.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 147505430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116282 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.505730 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23997616 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 111589834 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9436408 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1909015 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 572556 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 581578 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 41802 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68051619 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 132447 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 572556 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24921470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78409233 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21681516 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10334902 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11585751 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65629269 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204540 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2094492 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 230558 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7313834 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43742274 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79592762 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79412105 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168205 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38181578 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5560688 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1689598 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239417 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13566650 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10375081 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6952014 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1510108 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1095838 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58467936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2138049 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57495232 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57340 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7623893 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3407756 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1476849 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 147505430 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.389784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.113628 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 147496190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116180 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.505509 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23986183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 111594322 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9434858 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1908489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 572337 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 581608 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 41807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68042420 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 132440 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 572337 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24909467 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78381394 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21682831 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10333745 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11616414 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65623799 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 205401 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2094519 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 225742 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7349306 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43739456 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79586592 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79405874 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168265 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38181154 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5558294 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1689229 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239421 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13564930 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10374266 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6952166 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1510457 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1094829 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58464384 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2137218 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57492092 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57307 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7620053 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3404147 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476015 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147496190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.389787 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.113704 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 123907632 84.00% 84.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10178942 6.90% 90.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4283791 2.90% 93.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3020718 2.05% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3080788 2.09% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1492274 1.01% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1011781 0.69% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 404686 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124818 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 123903149 84.00% 84.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10174594 6.90% 90.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4283554 2.90% 93.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3020095 2.05% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3079434 2.09% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1494296 1.01% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011464 0.69% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404727 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124877 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 147505430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147496190 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210139 18.65% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 541380 48.04% 66.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375310 33.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210492 18.68% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 541350 48.03% 66.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375218 33.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7282 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39050510 67.92% 67.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61871 0.11% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39049419 67.92% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61870 0.11% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10660993 18.54% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6723341 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949046 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10658869 18.54% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6723409 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949053 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57495232 # Type of FU issued -system.cpu.iq.rate 0.372590 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1126829 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019599 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262967275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67912541 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55849108 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712787 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336322 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328951 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58232058 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382721 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 635480 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57492092 # Type of FU issued +system.cpu.iq.rate 0.372607 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1127060 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019604 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262951820 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67904206 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55848058 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712920 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336440 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329015 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58229078 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382791 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 635540 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1282102 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3336 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1281314 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3324 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 573763 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 573929 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 460617 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 459106 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 572556 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74664181 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1190404 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64295088 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 139940 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10375081 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6952014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890561 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43857 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 943603 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 572337 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 74665457 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1160593 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64290812 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139650 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10374266 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6952166 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1889682 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43932 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 913665 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 177030 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409389 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 586419 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56909013 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10319700 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586218 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 176905 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409384 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 586289 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56905925 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10317589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586166 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3689103 # number of nop insts executed -system.cpu.iew.exec_refs 16987647 # number of memory reference insts executed -system.cpu.iew.exec_branches 8974028 # Number of branches executed -system.cpu.iew.exec_stores 6667947 # Number of stores executed -system.cpu.iew.exec_rate 0.368791 # Inst execution rate -system.cpu.iew.wb_sent 56315341 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56178059 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28756993 # num instructions producing a value -system.cpu.iew.wb_consumers 39942343 # num instructions consuming a value -system.cpu.iew.wb_rate 0.364054 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719963 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8005041 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661200 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146102886 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.384475 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.286214 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3689210 # number of nop insts executed +system.cpu.iew.exec_refs 16985526 # number of memory reference insts executed +system.cpu.iew.exec_branches 8973539 # Number of branches executed +system.cpu.iew.exec_stores 6667937 # Number of stores executed +system.cpu.iew.exec_rate 0.368808 # Inst execution rate +system.cpu.iew.wb_sent 56314090 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56177073 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28757350 # num instructions producing a value +system.cpu.iew.wb_consumers 39943859 # num instructions consuming a value +system.cpu.iew.wb_rate 0.364084 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719944 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8001816 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661203 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537200 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146094021 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.384495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.286335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 126320849 86.46% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7855297 5.38% 91.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4275062 2.93% 94.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2236701 1.53% 96.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1745224 1.19% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615726 0.42% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 478400 0.33% 98.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 477555 0.33% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2098072 1.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 126314306 86.46% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7853790 5.38% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4274774 2.93% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2236101 1.53% 96.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1744788 1.19% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615632 0.42% 97.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 478334 0.33% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 476966 0.33% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2099330 1.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146102886 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56172911 # Number of instructions committed -system.cpu.commit.committedOps 56172911 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146094021 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56172359 # Number of instructions committed +system.cpu.commit.committedOps 56172359 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471230 # Number of memory references committed -system.cpu.commit.loads 9092979 # Number of loads committed -system.cpu.commit.membars 226353 # Number of memory barriers committed -system.cpu.commit.branches 8440862 # Number of branches committed +system.cpu.commit.refs 15471189 # Number of memory references committed +system.cpu.commit.loads 9092952 # Number of loads committed +system.cpu.commit.membars 226351 # Number of memory barriers committed +system.cpu.commit.branches 8440746 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52022252 # Number of committed integer instructions. -system.cpu.commit.function_calls 740590 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198097 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36219833 64.48% 70.17% # Class of committed instruction +system.cpu.commit.int_insts 52021709 # Number of committed integer instructions. +system.cpu.commit.function_calls 740586 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198088 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36219325 64.48% 70.17% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction @@ -627,34 +617,34 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319332 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384206 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949045 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9319303 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6384192 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949053 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56172911 # Class of committed instruction -system.cpu.commit.bw_lim_events 2098072 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 207933116 # The number of ROB reads -system.cpu.rob.rob_writes 129754111 # The number of ROB writes -system.cpu.timesIdled 581360 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6807046 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3597208249 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52982087 # Number of Instructions Simulated -system.cpu.committedOps 52982087 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.912541 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.912541 # CPI: Total CPI of All Threads -system.cpu.ipc 0.343343 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.343343 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74569031 # number of integer regfile reads -system.cpu.int_regfile_writes 40527114 # number of integer regfile writes -system.cpu.fp_regfile_reads 166982 # number of floating regfile reads -system.cpu.fp_regfile_writes 167538 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985520 # number of misc regfile reads -system.cpu.misc_regfile_writes 939432 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1401817 # number of replacements +system.cpu.commit.op_class_0::total 56172359 # Class of committed instruction +system.cpu.commit.bw_lim_events 2099330 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 207919346 # The number of ROB reads +system.cpu.rob.rob_writes 129746181 # The number of ROB writes +system.cpu.timesIdled 581168 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6800748 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3597219294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52981544 # Number of Instructions Simulated +system.cpu.committedOps 52981544 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.912277 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.912277 # CPI: Total CPI of All Threads +system.cpu.ipc 0.343374 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.343374 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74565581 # number of integer regfile reads +system.cpu.int_regfile_writes 40526554 # number of integer regfile writes +system.cpu.fp_regfile_reads 167056 # number of floating regfile reads +system.cpu.fp_regfile_writes 167536 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985625 # number of misc regfile reads +system.cpu.misc_regfile_writes 939435 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1401792 # number of replacements system.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11831384 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1402329 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.436953 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 11831016 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1402304 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.436841 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy @@ -664,386 +654,386 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63839342 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63839342 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7238802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7238802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4190242 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4190242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186215 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186215 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215725 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215725 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11429044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11429044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11429044 # number of overall hits -system.cpu.dcache.overall_hits::total 11429044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1797438 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1797438 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1957552 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1957552 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23250 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23250 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 63836509 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63836509 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7238578 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7238578 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4190111 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4190111 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186204 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186204 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215724 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215724 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11428689 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11428689 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11428689 # number of overall hits +system.cpu.dcache.overall_hits::total 11428689 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1796989 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1796989 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1957670 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1957670 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23246 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23246 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3754990 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3754990 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3754990 # number of overall misses -system.cpu.dcache.overall_misses::total 3754990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57215969500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57215969500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116801916611 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116801916611 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447608000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 447608000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 892500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 892500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 174017886111 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 174017886111 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 174017886111 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 174017886111 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9036240 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9036240 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147794 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147794 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209465 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209465 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15184034 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15184034 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15184034 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15184034 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198914 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198914 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318415 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318415 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110997 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.110997 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3754659 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3754659 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3754659 # number of overall misses +system.cpu.dcache.overall_misses::total 3754659 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57191537500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57191537500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116815247150 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116815247150 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 448333000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 448333000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 872000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 872000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 174006784650 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 174006784650 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 174006784650 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 174006784650 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9035567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9035567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147781 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147781 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209450 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209450 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215753 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215753 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15183348 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15183348 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15183348 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15183348 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198879 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198879 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318435 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318435 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110986 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.110986 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247299 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247299 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247299 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247299 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.957208 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.957208 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59667.337885 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59667.337885 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.102408 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46343.102408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.102408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46343.102408 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7142391 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5288 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 134027 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.247288 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247288 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247288 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247288 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31826.314741 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31826.314741 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59670.550782 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59670.550782 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19286.457885 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19286.457885 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30068.965517 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30068.965517 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46344.231167 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46344.231167 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7151643 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5595 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133832 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.290688 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 188.857143 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437466 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 199.821429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841132 # number of writebacks -system.cpu.dcache.writebacks::total 841132 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703605 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 703605 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1666863 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2370468 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2370468 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2370468 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2370468 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1093833 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1093833 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290689 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290689 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18017 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18017 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 841120 # number of writebacks +system.cpu.dcache.writebacks::total 841120 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703166 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 703166 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666991 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1666991 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5234 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5234 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2370157 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2370157 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2370157 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2370157 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1093823 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1093823 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290679 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290679 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18012 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18012 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384522 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384522 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384522 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384522 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384502 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384502 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384502 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384502 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44560579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 44560579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18438109720 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18438109720 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229318500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229318500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 863500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 863500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62998688720 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62998688720 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62998688720 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62998688720 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529006000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529006000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154205500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154205500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683211500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683211500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121050 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121050 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086014 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086014 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44561431000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 44561431000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18441083775 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18441083775 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229476500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229476500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 843000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 843000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63002514775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63002514775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63002514775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63002514775 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528979500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528979500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154218500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154218500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683198000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683198000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121057 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121057 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047282 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047282 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085997 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085997 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091183 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091183 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.009367 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.009367 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.990158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.990158 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12727.895876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12727.895876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29775.862069 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29775.862069 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.121830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.121830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.121830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.121830 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220635.786436 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220635.786436 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224443.165243 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224443.165243 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222846.775169 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222846.775169 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091186 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091186 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40739.160723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40739.160723 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63441.403662 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63441.403662 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12740.200977 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12740.200977 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29068.965517 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29068.965517 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220631.962482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220631.962482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224444.519692 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224444.519692 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222845.958374 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222845.958374 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1036100 # number of replacements -system.cpu.icache.tags.tagsinuse 507.835115 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7900592 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1036608 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.621581 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1035081 # number of replacements +system.cpu.icache.tags.tagsinuse 507.835100 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7897485 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1035589 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.626080 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.835115 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 507.835100 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.991865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10027831 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10027831 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7900593 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7900593 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7900593 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7900593 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7900593 # number of overall hits -system.cpu.icache.overall_hits::total 7900593 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1090257 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1090257 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1090257 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1090257 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1090257 # number of overall misses -system.cpu.icache.overall_misses::total 1090257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16373914482 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16373914482 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16373914482 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16373914482 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16373914482 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16373914482 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8990850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8990850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8990850 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8990850 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8990850 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8990850 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121263 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121263 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121263 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121263 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121263 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121263 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.398856 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15018.398856 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.398856 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15018.398856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.398856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15018.398856 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 11165 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10022677 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10022677 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7897486 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7897486 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7897486 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7897486 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7897486 # number of overall hits +system.cpu.icache.overall_hits::total 7897486 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1089229 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1089229 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1089229 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1089229 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1089229 # number of overall misses +system.cpu.icache.overall_misses::total 1089229 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16358882985 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16358882985 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16358882985 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16358882985 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16358882985 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16358882985 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8986715 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8986715 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8986715 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8986715 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8986715 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8986715 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121204 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121204 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121204 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121204 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121204 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121204 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.772898 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15018.772898 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.772898 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15018.772898 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.772898 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15018.772898 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 10400 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 304 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 36.726974 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.766234 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1036100 # number of writebacks -system.cpu.icache.writebacks::total 1036100 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53276 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53276 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53276 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53276 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53276 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53276 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1036981 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1036981 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1036981 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1036981 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1036981 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1036981 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14441953990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14441953990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14441953990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14441953990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14441953990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14441953990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115337 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115337 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115337 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.922470 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.922470 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.922470 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.922470 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.922470 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.922470 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1035081 # number of writebacks +system.cpu.icache.writebacks::total 1035081 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53267 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53267 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53267 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53267 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53267 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53267 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035962 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1035962 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1035962 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1035962 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1035962 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1035962 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14427899492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14427899492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14427899492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14427899492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14427899492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14427899492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115277 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115277 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115277 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115277 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13927.054749 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13927.054749 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13927.054749 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13927.054749 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13927.054749 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13927.054749 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338547 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65279.195987 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4167777 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403714 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.323588 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 338544 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65279.658287 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4165713 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403711 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.318552 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 9186443000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53290.316261 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5240.255495 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6748.624231 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.813146 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.079960 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.102976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996081 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 53291.619090 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5239.581641 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6748.457555 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.813166 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.079950 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.102973 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996089 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3482 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3334 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2423 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55435 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3333 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55433 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39707271 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39707271 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 841132 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 841132 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1035549 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1035549 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 39690670 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39690670 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 841120 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 841120 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1034540 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1034540 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185951 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185951 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1021691 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1021691 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827089 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 827089 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1021691 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1013040 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2034731 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1021691 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1013040 # number of overall hits -system.cpu.l2cache.overall_hits::total 2034731 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185946 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185946 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1020673 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1020673 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827071 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 827071 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1020673 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1013017 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2033690 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1020673 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1013017 # number of overall hits +system.cpu.l2cache.overall_hits::total 2033690 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 101 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 101 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 7 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115511 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115511 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115508 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115508 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 14974 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 14974 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273860 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 273860 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273861 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 273861 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 14974 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389371 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404345 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389369 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404343 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 14974 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389371 # number of overall misses -system.cpu.l2cache.overall_misses::total 404345 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 815500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 815500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 243500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 243500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16101413500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16101413500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2016727500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2016727500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34005178500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 34005178500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2016727500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 50106592000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 52123319500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2016727500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 50106592000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 52123319500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 841132 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 841132 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1035549 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1035549 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 389369 # number of overall misses +system.cpu.l2cache.overall_misses::total 404343 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 786000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 786000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 235500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 235500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16104953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16104953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2014947000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2014947000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34006362500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 34006362500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2014947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 50111315500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 52126262500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2014947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 50111315500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 52126262500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 841120 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 841120 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1034540 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1034540 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 130 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 29 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301462 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301462 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1036665 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1036665 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1100949 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1100949 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1036665 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1402411 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2439076 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1036665 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1402411 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2439076 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301454 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301454 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1035647 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1035647 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1100932 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1100932 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1035647 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1402386 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2438033 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1035647 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1402386 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2438033 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.776923 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.776923 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.241379 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.241379 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383169 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383169 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014444 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014444 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248749 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248749 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014444 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277644 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165778 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014444 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277644 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165778 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8074.257426 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8074.257426 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139392.901975 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139392.901975 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134681.948711 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134681.948711 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124169.935368 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124169.935368 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134681.948711 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128685.988427 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 128908.035217 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134681.948711 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128685.988427 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 128908.035217 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383170 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383170 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014459 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014459 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248754 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248754 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014459 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277648 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.165848 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014459 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277648 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.165848 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7782.178218 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7782.178218 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 33642.857143 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 33642.857143 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139427.165218 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139427.165218 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134563.042607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134563.042607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124173.805325 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124173.805325 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134563.042607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128698.780591 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 128915.951309 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134563.042607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128698.780591 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 128915.951309 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1052,8 +1042,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76062 # number of writebacks -system.cpu.l2cache.writebacks::total 76062 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 76064 # number of writebacks +system.cpu.l2cache.writebacks::total 76064 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits @@ -1064,132 +1054,132 @@ system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 101 system.cpu.l2cache.UpgradeReq_mshr_misses::total 101 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115511 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115511 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115508 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115508 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 14973 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 14973 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273860 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273861 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273861 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 14973 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389371 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404344 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389369 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404342 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 14973 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389371 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404344 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389369 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404342 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7246500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7246500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 500000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 500000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14946303500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14946303500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1866866500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1866866500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31277093000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31277093000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1866866500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46223396500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 48090263000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1866866500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46223396500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 48090263000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442306500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442306500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043789000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043789000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486095500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486095500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6981000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6981000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 479500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 479500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14949871007 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14949871007 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1865086000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1865086000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31278266000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31278266000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1865086000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46228137007 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 48093223007 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1865086000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46228137007 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 48093223007 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043799500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043799500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486079500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486079500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.776923 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.776923 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.241379 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.241379 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383169 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383169 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014443 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248749 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248749 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277644 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165778 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277644 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165778 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71747.524752 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71747.524752 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71428.571429 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71428.571429 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.901975 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.901975 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124682.194617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124682.194617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114208.329073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114208.329073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124682.194617 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118712.992236 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118934.033892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124682.194617 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118712.992236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118934.033892 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208125.036075 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208125.036075 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210920.589303 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210920.589303 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383170 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383170 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014458 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248754 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248754 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165848 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165848 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69118.811881 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69118.811881 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129427.147964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129427.147964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124563.280572 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124563.280572 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114212.195238 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114212.195238 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208121.212121 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208121.212121 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212940.143780 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212940.143780 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210919.621249 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210919.621249 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4877468 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2438381 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4875380 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2437337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2172 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2144935 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2143899 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 958726 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1035549 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 821965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 958701 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1035081 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 823325 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1036981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101105 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3109195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4238791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7347986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132621696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143635700 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 276257396 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422449 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2878056 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001305 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.036107 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7346784 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132526592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143633332 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 276159924 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422430 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2876994 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001301 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.036051 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2874299 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3757 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2873250 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3744 0.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2878056 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4329029000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2876994 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4326954000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1556718501 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1555197985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2115441804 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2115406799 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1233,37 +1223,37 @@ system.iobus.pkt_size_system.bridge.master::total 44148 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5356500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 826000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 825500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14342000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14331000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5944500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5952500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 88000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215036503 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215698160 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.249428 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.249420 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1725995793000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.249428 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1725995722000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.249420 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1281,8 +1271,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5430705120 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5430705120 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245293777 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5245293777 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles @@ -1305,17 +1295,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130696.599923 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130696.599923 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126234.447848 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126234.447848 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency system.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency system.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 216 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.705882 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1331,8 +1321,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353105120 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3353105120 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165897973 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165897973 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles @@ -1347,62 +1337,61 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80696.599923 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80696.599923 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.229616 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.229616 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295855 # Transaction distribution +system.membus.trans_dist::ReadResp 295856 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117574 # Transaction distribution -system.membus.trans_dist::CleanEvict 261706 # Transaction distribution -system.membus.trans_dist::UpgradeReq 351 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117576 # Transaction distribution +system.membus.trans_dist::CleanEvict 261861 # Transaction distribution +system.membus.trans_dist::UpgradeReq 350 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 358 # Transaction distribution -system.membus.trans_dist::ReadExReq 115261 # Transaction distribution -system.membus.trans_dist::ReadExResp 115261 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289006 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 115259 # Transaction distribution +system.membus.trans_dist::ReadExResp 115259 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289007 # Transaction distribution system.membus.trans_dist::BadAddressError 81 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145859 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1304255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1262502 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751476 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33409140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33409204 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842165 # Request fanout histogram +system.membus.snoop_fanout::samples 842145 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842165 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842145 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842165 # Request fanout histogram -system.membus.reqLayer0.occupancy 28939500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842145 # Request fanout histogram +system.membus.reqLayer0.occupancy 28932500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314314398 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314336715 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 105000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139101639 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2138304000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69817453 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 911117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1436,28 +1425,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211011 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211012 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105567 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182242 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105568 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818035845500 96.92% 96.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64907500 0.00% 96.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561478000 0.03% 96.96% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57097305000 3.04% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1875759536000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1818034033000 96.92% 96.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64890000 0.00% 96.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561380500 0.03% 96.96% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57096986000 3.04% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1875757289500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815427 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694311 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815422 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1496,7 +1485,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175125 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175126 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1505,20 +1494,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191970 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 191971 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394011 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29997949500 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2897677500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1842863901000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29989573500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2896538000 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842871170000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 190a0b7d0..1e558125c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,21 +4,21 @@ sim_seconds 1.843590 # Nu sim_ticks 1843589966000 # Number of ticks simulated final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221527 # Simulator instruction rate (inst/s) -host_op_rate 221527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5683484333 # Simulator tick rate (ticks/s) -host_mem_usage 334252 # Number of bytes of host memory used -host_seconds 324.38 # Real time elapsed on the host -sim_insts 71858146 # Number of instructions simulated -sim_ops 71858146 # Number of ops (including micro ops) simulated +host_inst_rate 235004 # Simulator instruction rate (inst/s) +host_op_rate 235004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6029262323 # Simulator tick rate (ticks/s) +host_mem_usage 334496 # Number of bytes of host memory used +host_seconds 305.77 # Real time elapsed on the host +sim_insts 71858166 # Number of instructions simulated +sim_ops 71858166 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 498752 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 20812864 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 142016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1542016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1542464 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 270784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2513856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2513408 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 25781248 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 498752 # Number of instructions bytes read from this memory @@ -30,9 +30,9 @@ system.physmem.bytes_written::total 7470272 # Nu system.physmem.num_reads::cpu0.inst 7793 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 325201 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24101 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 4231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39279 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39272 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 402832 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 116723 # Number of write requests responded to by this memory @@ -40,9 +40,9 @@ system.physmem.num_writes::total 116723 # Nu system.physmem.bw_read::cpu0.inst 270533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 11289313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 77032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 836420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 836663 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 146879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1363566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1363323 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 13984264 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 270533 # Instruction read bandwidth from this memory (bytes/s) @@ -55,58 +55,58 @@ system.physmem.bw_total::writebacks 4052025 # To system.physmem.bw_total::cpu0.inst 270533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 11289313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 77032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 836420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 836663 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 146879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1363566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1363323 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18036288 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 69838 # Number of read requests accepted -system.physmem.writeReqs 42816 # Number of write requests accepted +system.physmem.writeReqs 43200 # Number of write requests accepted system.physmem.readBursts 69838 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 42816 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 43200 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 4468672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue -system.physmem.bytesWritten 2738752 # Total number of bytes written to DRAM +system.physmem.bytesWritten 2763328 # Total number of bytes written to DRAM system.physmem.bytesReadSys 4469632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2740224 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 2764800 # Total written bytes from the system interface side system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 59609 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 4348 # Per bank write bursts system.physmem.perBankRdBursts::1 4129 # Per bank write bursts system.physmem.perBankRdBursts::2 4337 # Per bank write bursts system.physmem.perBankRdBursts::3 4598 # Per bank write bursts system.physmem.perBankRdBursts::4 3888 # Per bank write bursts system.physmem.perBankRdBursts::5 4661 # Per bank write bursts -system.physmem.perBankRdBursts::6 4236 # Per bank write bursts +system.physmem.perBankRdBursts::6 4235 # Per bank write bursts system.physmem.perBankRdBursts::7 4148 # Per bank write bursts -system.physmem.perBankRdBursts::8 4711 # Per bank write bursts +system.physmem.perBankRdBursts::8 4712 # Per bank write bursts system.physmem.perBankRdBursts::9 4417 # Per bank write bursts system.physmem.perBankRdBursts::10 4595 # Per bank write bursts system.physmem.perBankRdBursts::11 4084 # Per bank write bursts -system.physmem.perBankRdBursts::12 4057 # Per bank write bursts -system.physmem.perBankRdBursts::13 4571 # Per bank write bursts +system.physmem.perBankRdBursts::12 4058 # Per bank write bursts +system.physmem.perBankRdBursts::13 4570 # Per bank write bursts system.physmem.perBankRdBursts::14 4705 # Per bank write bursts system.physmem.perBankRdBursts::15 4338 # Per bank write bursts system.physmem.perBankWrBursts::0 2799 # Per bank write bursts system.physmem.perBankWrBursts::1 2436 # Per bank write bursts -system.physmem.perBankWrBursts::2 2776 # Per bank write bursts -system.physmem.perBankWrBursts::3 2976 # Per bank write bursts -system.physmem.perBankWrBursts::4 2273 # Per bank write bursts -system.physmem.perBankWrBursts::5 2670 # Per bank write bursts +system.physmem.perBankWrBursts::2 2792 # Per bank write bursts +system.physmem.perBankWrBursts::3 3104 # Per bank write bursts +system.physmem.perBankWrBursts::4 2401 # Per bank write bursts +system.physmem.perBankWrBursts::5 2782 # Per bank write bursts system.physmem.perBankWrBursts::6 2480 # Per bank write bursts system.physmem.perBankWrBursts::7 2289 # Per bank write bursts -system.physmem.perBankWrBursts::8 3133 # Per bank write bursts +system.physmem.perBankWrBursts::8 3134 # Per bank write bursts system.physmem.perBankWrBursts::9 2510 # Per bank write bursts system.physmem.perBankWrBursts::10 2861 # Per bank write bursts system.physmem.perBankWrBursts::11 2441 # Per bank write bursts system.physmem.perBankWrBursts::12 2439 # Per bank write bursts -system.physmem.perBankWrBursts::13 2832 # Per bank write bursts +system.physmem.perBankWrBursts::13 2831 # Per bank write bursts system.physmem.perBankWrBursts::14 3033 # Per bank write bursts system.physmem.perBankWrBursts::15 2845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 1842578089000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 1842577981000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,11 +120,11 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 42816 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5331 # What read queue length does an incoming req see +system.physmem.writePktSize::6 43200 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -155,190 +155,183 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.185887 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.348650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 370.654869 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7177 35.77% 35.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4604 22.94% 58.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1640 8.17% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 939 4.68% 71.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 711 3.54% 75.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 484 2.41% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 449 2.24% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 396 1.97% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3666 18.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20066 # Bytes accessed per row activation +system.physmem.wrQLenPdf::15 746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.141427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.044984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 371.054922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7137 35.54% 35.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4621 23.01% 58.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1666 8.30% 66.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 928 4.62% 71.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 708 3.53% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 489 2.44% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 446 2.22% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 393 1.96% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3693 18.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20081 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 1852 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 37.694924 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 845.707060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 845.707136 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 1850 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 1852 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 1852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.106371 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.632339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.643623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.84% 1.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.38% 2.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.22% 2.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 3 0.16% 2.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1503 81.16% 83.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 52 2.81% 86.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 11 0.59% 87.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 74 4.00% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.22% 91.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 8 0.43% 91.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.92% 92.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.43% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.38% 93.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.05% 93.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.16% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.43% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.43% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 15 0.81% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.05% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 66 3.56% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.05% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.11% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.11% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.16% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.313715 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.866365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.527044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 41 2.21% 2.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 7 0.38% 2.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 1554 83.91% 86.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 22 1.19% 87.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 8 0.43% 88.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 17 0.92% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 85 4.59% 93.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 1 0.05% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 5 0.27% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 12 0.65% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 79 4.27% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.05% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 1 0.05% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 2 0.11% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.11% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 1 0.05% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 1 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.22% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 1852 # Writes before turning the bus around for reads -system.physmem.totQLat 871326250 # Total ticks spent queuing -system.physmem.totMemAccLat 2180507500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 868841000 # Total ticks spent queuing +system.physmem.totMemAccLat 2178022250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 349115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12479.07 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12443.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31229.07 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31193.48 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.08 # Average write queue length when enqueuing -system.physmem.readRowHits 58948 # Number of row buffer hits during reads -system.physmem.writeRowHits 33602 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.48 # Row buffer hit rate for writes -system.physmem.avgGap 16356082.24 # Average gap between requests -system.physmem.pageHitRate 82.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75161520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 40936500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 267891000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 134129520 # Energy for write commands per rank (pJ) +system.physmem.avgWrQLen 4.02 # Average write queue length when enqueuing +system.physmem.readRowHits 58950 # Number of row buffer hits during reads +system.physmem.writeRowHits 33969 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.63 # Row buffer hit rate for writes +system.physmem.avgGap 16300518.24 # Average gap between requests +system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75327840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 41027250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 267883200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 136617840 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36125026515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 799629184500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 925463073795 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.948938 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1310373436000 # Time in different power states +system.physmem_0.actBackEnergy 36136650240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 799618982250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 925467232860 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.951944 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1310356278000 # Time in different power states system.physmem_0.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9753765000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9770912000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 76537440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41650125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 276728400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 76484520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41621250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 276736200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 143169120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35621035650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799049139750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 924399004725 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.002289 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1311095993000 # Time in different power states +system.physmem_1.actBackEnergy 35633622105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799038075000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 924400452435 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.003354 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1311078051250 # Time in different power states system.physmem_1.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9016803000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9034735750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4864865 # DTB read hits +system.cpu0.dtb.read_hits 4864866 # DTB read hits system.cpu0.dtb.read_misses 6190 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 429298 # DTB read accesses -system.cpu0.dtb.write_hits 3435007 # DTB write hits +system.cpu0.dtb.write_hits 3435008 # DTB write hits system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 165213 # DTB write accesses -system.cpu0.dtb.data_hits 8299872 # DTB hits +system.cpu0.dtb.data_hits 8299874 # DTB hits system.cpu0.dtb.data_misses 6878 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations system.cpu0.dtb.data_accesses 594511 # DTB accesses @@ -374,10 +367,10 @@ system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # nu system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1820420159000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1820420490500 98.74% 98.74% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 39420000 0.00% 98.75% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 369089000 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22760564000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22760232500 1.23% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1843589232000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -442,32 +435,32 @@ system.cpu0.kern.mode_switch_good::kernel 0.322243 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29996442500 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2592008500 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1811000779000 98.23% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 29995203000 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2591439000 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1811002588000 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.cpu0.committedInsts 32582067 # Number of instructions committed system.cpu0.committedOps 32582067 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 30467910 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 163902 # Number of float alu accesses -system.cpu0.num_func_calls 798063 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4326151 # number of instructions that are conditional controls +system.cpu0.num_func_calls 798062 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4326152 # number of instructions that are conditional controls system.cpu0.num_int_insts 30467910 # number of integer instructions system.cpu0.num_fp_insts 163902 # number of float instructions system.cpu0.num_int_register_reads 42599897 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22343202 # number of times the integer registers were written +system.cpu0.num_int_register_writes 22343200 # number of times the integer registers were written system.cpu0.num_fp_register_reads 84869 # number of times the floating registers were read system.cpu0.num_fp_register_writes 86282 # number of times the floating registers were written -system.cpu0.num_mem_refs 8329685 # number of memory refs -system.cpu0.num_load_insts 4886081 # Number of load instructions -system.cpu0.num_store_insts 3443604 # Number of store instructions -system.cpu0.num_idle_cycles 904742998.483282 # Number of idle cycles -system.cpu0.num_busy_cycles 23823652.516718 # Number of busy cycles +system.cpu0.num_mem_refs 8329687 # number of memory refs +system.cpu0.num_load_insts 4886082 # Number of load instructions +system.cpu0.num_store_insts 3443605 # Number of store instructions +system.cpu0.num_idle_cycles 904742998.451047 # Number of idle cycles +system.cpu0.num_busy_cycles 23823652.548953 # Number of busy cycles system.cpu0.not_idle_fraction 0.025656 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.974344 # Percentage of idle cycles system.cpu0.Branches 5381713 # Number of branches fetched system.cpu0.op_class::No_OpClass 1604740 4.92% 4.92% # Class of executed instruction -system.cpu0.op_class::IntAlu 21953707 67.37% 72.29% # Class of executed instruction +system.cpu0.op_class::IntAlu 21953705 67.37% 72.29% # Class of executed instruction system.cpu0.op_class::IntMult 32143 0.10% 72.39% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 72.39% # Class of executed instruction system.cpu0.op_class::FloatAdd 13006 0.04% 72.43% # Class of executed instruction @@ -496,196 +489,196 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.43% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.43% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.43% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::MemRead 5016903 15.39% 87.83% # Class of executed instruction -system.cpu0.op_class::MemWrite 3446713 10.58% 98.40% # Class of executed instruction +system.cpu0.op_class::MemRead 5016904 15.39% 87.83% # Class of executed instruction +system.cpu0.op_class::MemWrite 3446714 10.58% 98.40% # Class of executed instruction system.cpu0.op_class::IprAccess 520313 1.60% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 32589155 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1393262 # number of replacements +system.cpu0.dcache.tags.replacements 1393265 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13241810 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393774 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.500687 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13241654 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393777 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.500554 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.746834 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216845 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034134 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497552 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236752 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265692 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.747103 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216699 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034010 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497553 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236751 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265691 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63387052 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63387052 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4025112 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1019452 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2537983 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7582547 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3145682 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 772489 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357389 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5275560 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 63386315 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63386315 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4025113 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1019893 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2537393 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7582399 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3145683 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 772678 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1357185 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275546 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114073 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19050 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51169 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184292 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51175 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184298 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122917 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21014 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55400 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199331 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7170794 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1791941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3895372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12858107 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7170794 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1791941 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3895372 # number of overall hits -system.cpu0.dcache.overall_hits::total 12858107 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 7170796 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1792571 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3894578 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12857945 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7170796 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1792571 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3894578 # number of overall hits +system.cpu0.dcache.overall_hits::total 12857945 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 726690 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 86798 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 548610 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1362098 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 86811 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 548555 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1362056 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 165054 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 38388 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 671853 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 875295 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 38389 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 671866 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 875309 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9398 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2090 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7704 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19192 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7703 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19191 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 891744 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 125186 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1220463 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2237393 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 125200 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1220421 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2237365 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 891744 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 125186 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1220463 # number of overall misses -system.cpu0.dcache.overall_misses::total 2237393 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2310299500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8894370000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11204669500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2132273000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29520003133 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 31652276133 # number of WriteReq miss cycles +system.cpu0.dcache.overall_misses::cpu1.data 125200 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1220421 # number of overall misses +system.cpu0.dcache.overall_misses::total 2237365 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2310208500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8890735000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11200943500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2130423000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29514538622 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 31644961622 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27861500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 150264500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 178126000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 111000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 111000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4442572500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 38414373133 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42856945633 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4442572500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 38414373133 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42856945633 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4751802 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1106250 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3086593 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8944645 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3310736 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 810877 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2029242 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 150253000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 178114500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 108000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 108000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4440631500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 38405273622 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 42845905122 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4440631500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 38405273622 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 42845905122 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4751803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1106704 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3085948 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8944455 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3310737 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 811067 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2029051 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 6150855 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123471 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21140 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58873 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203484 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58878 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203489 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122918 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21014 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55403 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 199335 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8062538 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1917127 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5115835 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15095500 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8062538 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1917127 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5115835 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15095500 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 8062540 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 1917771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5114999 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15095310 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8062540 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 1917771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5114999 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15095310 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.152929 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.078461 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.177740 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152281 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.078441 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.177759 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152279 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049854 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047341 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331086 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.142305 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047331 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331123 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.142307 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076115 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.098865 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130858 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094317 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130830 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094310 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110603 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065299 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.238566 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065284 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.238597 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.148216 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110603 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065299 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.238566 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065284 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.238597 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.148216 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26616.966981 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16212.555367 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8226.037701 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55545.300615 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43938.187569 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36161.838161 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26611.932820 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16207.554393 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8223.555786 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55495.662820 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43929.204070 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 36152.903286 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13330.861244 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19504.737799 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9281.263026 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 37000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27750 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35487.774192 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31475.245979 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19154.858191 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35487.774192 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31475.245979 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19154.858191 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1652146 # number of cycles access was blocked +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19505.776970 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9281.147413 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 36000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35468.302716 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31468.873136 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19150.163305 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35468.302716 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31468.873136 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19150.163305 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1652562 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 2580 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 59796 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 59814 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.629708 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.628348 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 215 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835859 # number of writebacks -system.cpu0.dcache.writebacks::total 835859 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 288357 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 288357 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 572581 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 572581 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1582 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1582 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 860938 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 860938 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 860938 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 860938 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86798 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 260253 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 347051 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38388 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99272 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 137660 # number of WriteReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 835864 # number of writebacks +system.cpu0.dcache.writebacks::total 835864 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 288309 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 288309 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 572598 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 572598 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1581 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1581 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 860907 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 860907 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 860907 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 860907 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86811 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 260246 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 347057 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38389 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99268 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137657 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2090 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6122 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8212 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 125186 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 359525 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 484711 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 125186 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 359525 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 484711 # number of overall MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 125200 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 359514 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484714 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 125200 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 359514 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484714 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2652 # number of ReadReq MSHR uncacheable @@ -695,235 +688,235 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3516 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223501500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676661000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6900162500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2093885000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4616741882 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6710626882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223397500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676165000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6899562500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092034000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4615486880 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6707520880 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25771500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103207500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 108000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 108000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4317386500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9293402882 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13610789382 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4317386500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9293402882 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13610789382 # number of overall MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103208000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 105000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 105000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4315431500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9291651880 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13607083380 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4315431500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9291651880 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13607083380 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 293417500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 298094000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591511500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372514000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372517000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 424017500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796531500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665931500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796534500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665934500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 722111500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388043000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078461 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084317 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048921 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022381 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388046000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078441 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084333 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048923 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022380 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.098865 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103987 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103978 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040356 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25616.966981 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17969.671819 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19882.272346 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54545.300615 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46505.982372 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48747.834389 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25611.932820 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17968.249272 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19880.199794 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54495.662820 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46495.213765 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.333423 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.807579 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.888456 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 36000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.889252 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.949342 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230231.149567 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230233.003708 # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226544.795222 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225969.290804 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226545.648464 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225970.308789 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.396887 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.883268 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 963474 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.175730 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41537475 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 963985 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 43.089337 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 963447 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.175727 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41538422 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 963958 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 43.091527 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 10558559500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250464 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956509 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.968757 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250530 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956033 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.969164 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.510255 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160071 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328064 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160070 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328065 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998390 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43482483 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43482483 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32077013 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7031290 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2429172 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41537475 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32077013 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7031290 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2429172 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41537475 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32077013 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7031290 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2429172 # number of overall hits -system.cpu0.icache.overall_hits::total 41537475 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 512142 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 125208 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 343493 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 980843 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 512142 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 125208 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 343493 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 980843 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 512142 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 125208 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 343493 # number of overall misses -system.cpu0.icache.overall_misses::total 980843 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1899043000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5060933969 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6959976969 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1899043000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5060933969 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6959976969 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1899043000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5060933969 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6959976969 # number of overall miss cycles +system.cpu0.icache.tags.tag_accesses 43483376 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43483376 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 32077016 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7032806 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2428600 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41538422 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32077016 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7032806 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2428600 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41538422 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32077016 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7032806 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2428600 # number of overall hits +system.cpu0.icache.overall_hits::total 41538422 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 512139 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 125213 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 343464 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 980816 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 512139 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 125213 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 343464 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 980816 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 512139 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 125213 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 343464 # number of overall misses +system.cpu0.icache.overall_misses::total 980816 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1899535500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5061406468 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6960941968 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1899535500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5061406468 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6960941968 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1899535500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5061406468 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6960941968 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 32589155 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7156498 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2772665 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42518318 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7158019 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2772064 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42519238 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 32589155 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7156498 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2772665 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42518318 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7158019 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2772064 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42519238 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 32589155 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7156498 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2772665 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42518318 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7158019 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2772064 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42519238 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015715 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.017496 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.123886 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023069 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.017493 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.123902 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023068 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015715 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.017496 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.123886 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023069 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.017493 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.123902 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023068 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015715 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017496 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.123886 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023069 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15167.105936 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14733.732475 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7095.913382 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15167.105936 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14733.732475 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7095.913382 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15167.105936 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14733.732475 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7095.913382 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8552 # number of cycles access was blocked +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017493 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.123902 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023068 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15170.433581 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14736.352188 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7097.092592 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15170.433581 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14736.352188 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7097.092592 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15170.433581 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14736.352188 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7097.092592 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8655 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 357 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 361 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.955182 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.975069 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 963474 # number of writebacks -system.cpu0.icache.writebacks::total 963474 # number of writebacks +system.cpu0.icache.writebacks::writebacks 963447 # number of writebacks +system.cpu0.icache.writebacks::total 963447 # number of writebacks system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16678 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_hits::total 16678 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits::cpu2.inst 16678 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_hits::total 16678 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu2.inst 16678 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 16678 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 125208 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326815 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 452023 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 125208 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 326815 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 452023 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 125208 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 326815 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 452023 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1773835000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4488659473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6262494473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1773835000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4488659473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6262494473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1773835000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4488659473 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6262494473 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010631 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010631 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010631 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13854.371289 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13854.371289 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13854.371289 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 125213 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326786 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 451999 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 125213 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 326786 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 451999 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 125213 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 326786 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 451999 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1774322500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4489110472 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6263432972 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1774322500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4489110472 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6263432972 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1774322500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4489110472 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6263432972 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010630 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010630 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13857.183250 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13857.183250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13857.183250 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1125427 # DTB read hits +system.cpu1.dtb.read_hits 1125881 # DTB read hits system.cpu1.dtb.read_misses 1262 # DTB read misses system.cpu1.dtb.read_acv 31 # DTB read access violations -system.cpu1.dtb.read_accesses 117717 # DTB read accesses -system.cpu1.dtb.write_hits 832316 # DTB write hits +system.cpu1.dtb.read_accesses 118172 # DTB read accesses +system.cpu1.dtb.write_hits 832506 # DTB write hits system.cpu1.dtb.write_misses 154 # DTB write misses system.cpu1.dtb.write_acv 18 # DTB write access violations -system.cpu1.dtb.write_accesses 48434 # DTB write accesses -system.cpu1.dtb.data_hits 1957743 # DTB hits +system.cpu1.dtb.write_accesses 48626 # DTB write accesses +system.cpu1.dtb.data_hits 1958387 # DTB hits system.cpu1.dtb.data_misses 1416 # DTB misses system.cpu1.dtb.data_acv 49 # DTB access violations -system.cpu1.dtb.data_accesses 166151 # DTB accesses -system.cpu1.itb.fetch_hits 753702 # ITB hits +system.cpu1.dtb.data_accesses 166798 # DTB accesses +system.cpu1.itb.fetch_hits 755228 # ITB hits system.cpu1.itb.fetch_misses 636 # ITB misses system.cpu1.itb.fetch_acv 28 # ITB acv -system.cpu1.itb.fetch_accesses 754338 # ITB accesses +system.cpu1.itb.fetch_accesses 755864 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -936,7 +929,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953452897 # number of cpu cycles simulated +system.cpu1.numCycles 953452805 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -956,35 +949,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7155032 # Number of instructions committed -system.cpu1.committedOps 7155032 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6639972 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 39507 # Number of float alu accesses -system.cpu1.num_func_calls 205327 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 849342 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6639972 # number of integer instructions -system.cpu1.num_fp_insts 39507 # number of float instructions -system.cpu1.num_int_register_reads 9236476 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4860513 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 20546 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21005 # number of times the floating registers were written -system.cpu1.num_mem_refs 1964570 # number of memory refs -system.cpu1.num_load_insts 1130012 # Number of load instructions -system.cpu1.num_store_insts 834558 # Number of store instructions -system.cpu1.num_idle_cycles 924897585.359422 # Number of idle cycles -system.cpu1.num_busy_cycles 28555311.640577 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029949 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970051 # Percentage of idle cycles -system.cpu1.Branches 1119214 # Number of branches fetched -system.cpu1.op_class::No_OpClass 390317 5.45% 5.45% # Class of executed instruction -system.cpu1.op_class::IntAlu 4631234 64.71% 70.17% # Class of executed instruction -system.cpu1.op_class::IntMult 7711 0.11% 70.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3307 0.05% 70.32% # Class of executed instruction +system.cpu1.committedInsts 7156553 # Number of instructions committed +system.cpu1.committedOps 7156553 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6641394 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 39637 # Number of float alu accesses +system.cpu1.num_func_calls 205363 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 849545 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6641394 # number of integer instructions +system.cpu1.num_fp_insts 39637 # number of float instructions +system.cpu1.num_int_register_reads 9238548 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4861490 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 20633 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21093 # number of times the floating registers were written +system.cpu1.num_mem_refs 1965214 # number of memory refs +system.cpu1.num_load_insts 1130466 # Number of load instructions +system.cpu1.num_store_insts 834748 # Number of store instructions +system.cpu1.num_idle_cycles 924897133.577308 # Number of idle cycles +system.cpu1.num_busy_cycles 28555671.422692 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029950 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970050 # Percentage of idle cycles +system.cpu1.Branches 1119461 # Number of branches fetched +system.cpu1.op_class::No_OpClass 390354 5.45% 5.45% # Class of executed instruction +system.cpu1.op_class::IntAlu 4632011 64.71% 70.16% # Class of executed instruction +system.cpu1.op_class::IntMult 7720 0.11% 70.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3352 0.05% 70.32% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatDiv 440 0.01% 70.33% # Class of executed instruction +system.cpu1.op_class::FloatDiv 449 0.01% 70.33% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction @@ -1006,40 +999,40 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::MemRead 1158585 16.19% 86.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 835763 11.68% 98.20% # Class of executed instruction +system.cpu1.op_class::MemRead 1159039 16.19% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 835953 11.68% 98.20% # Class of executed instruction system.cpu1.op_class::IprAccess 129140 1.80% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7156497 # Class of executed instruction -system.cpu2.branchPred.lookups 10791906 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10058996 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 121698 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8434906 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6656118 # Number of BTB hits +system.cpu1.op_class::total 7158018 # Class of executed instruction +system.cpu2.branchPred.lookups 10791255 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10058403 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 121654 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8435844 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6655738 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 78.911585 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 298697 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7721 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 78.898306 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 298678 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7720 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3520448 # DTB read hits -system.cpu2.dtb.read_misses 12146 # DTB read misses +system.cpu2.dtb.read_hits 3519605 # DTB read hits +system.cpu2.dtb.read_misses 12192 # DTB read misses system.cpu2.dtb.read_acv 125 # DTB read access violations -system.cpu2.dtb.read_accesses 256305 # DTB read accesses -system.cpu2.dtb.write_hits 2173477 # DTB write hits -system.cpu2.dtb.write_misses 2690 # DTB write misses +system.cpu2.dtb.read_accesses 255658 # DTB read accesses +system.cpu2.dtb.write_hits 2173211 # DTB write hits +system.cpu2.dtb.write_misses 2700 # DTB write misses system.cpu2.dtb.write_acv 124 # DTB write access violations -system.cpu2.dtb.write_accesses 93625 # DTB write accesses -system.cpu2.dtb.data_hits 5693925 # DTB hits -system.cpu2.dtb.data_misses 14836 # DTB misses +system.cpu2.dtb.write_accesses 93379 # DTB write accesses +system.cpu2.dtb.data_hits 5692816 # DTB hits +system.cpu2.dtb.data_misses 14892 # DTB misses system.cpu2.dtb.data_acv 249 # DTB access violations -system.cpu2.dtb.data_accesses 349930 # DTB accesses -system.cpu2.itb.fetch_hits 553155 # ITB hits -system.cpu2.itb.fetch_misses 5226 # ITB misses -system.cpu2.itb.fetch_acv 187 # ITB acv -system.cpu2.itb.fetch_accesses 558381 # ITB accesses +system.cpu2.dtb.data_accesses 349037 # DTB accesses +system.cpu2.itb.fetch_hits 552522 # ITB hits +system.cpu2.itb.fetch_misses 5239 # ITB misses +system.cpu2.itb.fetch_acv 186 # ITB acv +system.cpu2.itb.fetch_accesses 557761 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1052,143 +1045,143 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 32236279 # number of cpu cycles simulated +system.cpu2.numCycles 32231216 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9243840 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 40617547 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10791906 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6954815 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 20753592 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 401538 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 9243140 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40614337 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10791255 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6954416 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20748537 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 401448 # Number of cycles fetch has spent squashing system.cpu2.fetch.TlbCycles 916 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10212 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 2008 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 193151 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 89388 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1068 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2772679 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90084 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.MiscStallCycles 10245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2007 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 193088 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 89379 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1066 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2772079 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 89992 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 30494706 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.331954 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.325119 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 30488864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.332104 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.325204 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 21037778 68.99% 68.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 294298 0.97% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 469114 1.54% 71.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5033169 16.51% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 879924 2.89% 90.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194801 0.64% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 230028 0.75% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433107 1.42% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1922487 6.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 21032791 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 294156 0.96% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 468874 1.54% 71.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5033027 16.51% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 879823 2.89% 90.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194768 0.64% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 230051 0.75% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433078 1.42% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1922296 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 30494706 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.334775 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.259995 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7573321 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 14126025 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7836977 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 524605 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 187915 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 174630 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13216 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 37265458 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 41467 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 187915 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7850244 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4676437 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6613578 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8057400 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2863279 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 36458401 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 57802 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 368784 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 93789 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1799072 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 24336413 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 45554095 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 45489801 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 60051 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22465786 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1870627 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 531021 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 62908 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3828322 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3503706 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2266582 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 453499 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 325031 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 33954893 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 679527 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 33661057 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16143 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2513373 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1127788 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 486024 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 30494706 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.103833 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.612725 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30488864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.334808 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.260093 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7572995 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 14121086 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7836457 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 524591 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 187872 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 174587 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13215 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37262943 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 41463 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 187872 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7849913 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4677015 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6609993 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8056869 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2861349 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 36455800 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 58084 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 369048 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 93720 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1797134 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 24334504 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 45550794 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 45486602 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 59958 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22464723 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1869781 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 530990 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 62923 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3828293 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3503034 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2266301 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 453472 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 325651 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33952570 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 679538 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 33658910 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16165 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2512562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1127430 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 486035 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30488864 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.103974 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.612784 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18452821 60.51% 60.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2702851 8.86% 69.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1349809 4.43% 73.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5753089 18.87% 92.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1041578 3.42% 96.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 588420 1.93% 98.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 396893 1.30% 99.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 164409 0.54% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44836 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18447860 60.51% 60.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2702530 8.86% 69.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1349610 4.43% 73.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5752968 18.87% 92.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1041424 3.42% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 588365 1.93% 98.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 396836 1.30% 99.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 164449 0.54% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44822 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 30494706 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30488864 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 81527 21.02% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 179819 46.37% 67.39% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126481 32.61% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 81533 21.03% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179737 46.36% 67.39% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126415 32.61% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 3131 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 27465013 81.59% 81.60% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21327 0.06% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 3114 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27463980 81.59% 81.60% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21318 0.06% 81.67% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 22209 0.07% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 22163 0.07% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1557 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.74% # Type of FU issued @@ -1210,101 +1203,101 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.74% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3648084 10.84% 92.57% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2197360 6.53% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3647310 10.84% 92.57% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2197101 6.53% 99.10% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 302367 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 33661057 # Type of FU issued -system.cpu2.iq.rate 1.044198 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 387827 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.011522 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 97956454 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 37027606 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 33043548 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 264336 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 125822 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122705 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 33904668 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 141085 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 200240 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 33658910 # Type of FU issued +system.cpu2.iq.rate 1.044295 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387685 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011518 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 97946508 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 37024649 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 33041720 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 264026 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 125654 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122549 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 33902559 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 140922 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 200179 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 431120 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5749 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178621 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 430903 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1110 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5745 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178531 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 4239 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 217381 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.cacheBlocked 217245 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 187915 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4008679 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 205535 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35998675 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51747 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3503706 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2266582 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 605109 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12931 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 157162 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5749 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 59808 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134012 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193820 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33465262 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3541255 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 195795 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 187872 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4009534 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 206574 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35996335 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51785 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3503034 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2266301 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 605122 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12947 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 158194 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5745 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 59769 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 133968 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193737 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33463084 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3540458 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 195826 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1364255 # number of nop insts executed -system.cpu2.iew.exec_refs 5722116 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7732316 # Number of branches executed -system.cpu2.iew.exec_stores 2180861 # Number of stores executed -system.cpu2.iew.exec_rate 1.038124 # Inst execution rate -system.cpu2.iew.wb_sent 33208664 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 33166253 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 19395256 # num instructions producing a value -system.cpu2.iew.wb_consumers 23138933 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.028849 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.838209 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 2630446 # The number of squashed insts skipped by commit +system.cpu2.iew.exec_nop 1364227 # number of nop insts executed +system.cpu2.iew.exec_refs 5721059 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7732015 # Number of branches executed +system.cpu2.iew.exec_stores 2180601 # Number of stores executed +system.cpu2.iew.exec_rate 1.038220 # Inst execution rate +system.cpu2.iew.wb_sent 33206737 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 33164269 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 19394211 # num instructions producing a value +system.cpu2.iew.wb_consumers 23137569 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.028949 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.838213 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 2629534 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 193503 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177071 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 30033551 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.109504 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.847540 # Number of insts commited each cycle +system.cpu2.commit.branchMispredicts 177029 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 30027785 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.109667 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.847605 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 19200071 63.93% 63.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2226295 7.41% 71.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1158853 3.86% 75.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5473619 18.23% 93.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 589521 1.96% 95.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 197097 0.66% 96.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164200 0.55% 96.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 162437 0.54% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 861458 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 19194769 63.92% 63.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2226064 7.41% 71.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1158797 3.86% 75.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5473612 18.23% 93.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 589514 1.96% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 197059 0.66% 96.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164152 0.55% 96.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 162472 0.54% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 861346 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 30033551 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 33322350 # Number of instructions committed -system.cpu2.commit.committedOps 33322350 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 30027785 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 33320829 # Number of instructions committed +system.cpu2.commit.committedOps 33320829 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5160547 # Number of memory references committed -system.cpu2.commit.loads 3072586 # Number of loads committed +system.cpu2.commit.refs 5159901 # Number of memory references committed +system.cpu2.commit.loads 3072131 # Number of loads committed system.cpu2.commit.membars 67946 # Number of memory barriers committed -system.cpu2.commit.branches 7560075 # Number of branches committed -system.cpu2.commit.fp_insts 120848 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31822701 # Number of committed integer instructions. -system.cpu2.commit.function_calls 240099 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1204434 3.61% 3.61% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 26541208 79.65% 83.26% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20874 0.06% 83.33% # Class of committed instruction +system.cpu2.commit.branches 7559828 # Number of branches committed +system.cpu2.commit.fp_insts 120718 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31821279 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240082 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1204397 3.61% 3.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26540433 79.65% 83.27% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20865 0.06% 83.33% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21768 0.07% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21723 0.07% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1557 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.40% # Class of committed instruction @@ -1326,29 +1319,29 @@ system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.40% system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3140532 9.42% 92.82% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2089601 6.27% 99.09% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3140077 9.42% 92.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2089410 6.27% 99.09% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 302367 0.91% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 33322350 # Class of committed instruction -system.cpu2.commit.bw_lim_events 861458 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 65049813 # The number of ROB reads -system.cpu2.rob.rob_writes 72365341 # The number of ROB writes -system.cpu2.timesIdled 178213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1741573 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747477665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 32121047 # Number of Instructions Simulated -system.cpu2.committedOps 32121047 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.003587 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.003587 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.996425 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.996425 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 43934131 # number of integer regfile reads -system.cpu2.int_regfile_writes 23251716 # number of integer regfile writes -system.cpu2.fp_regfile_reads 74710 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74652 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5374912 # number of misc regfile reads -system.cpu2.misc_regfile_writes 272966 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 33320829 # Class of committed instruction +system.cpu2.commit.bw_lim_events 861346 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 65041726 # The number of ROB reads +system.cpu2.rob.rob_writes 72360391 # The number of ROB writes +system.cpu2.timesIdled 178229 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1742352 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747482810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 32119546 # Number of Instructions Simulated +system.cpu2.committedOps 32119546 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.003477 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.003477 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.996535 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.996535 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 43931463 # number of integer regfile reads +system.cpu2.int_regfile_writes 23250358 # number of integer regfile writes +system.cpu2.fp_regfile_reads 74602 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74558 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5374687 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272957 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1391,7 +1384,7 @@ system.iobus.pkt_size_system.bridge.master::total 45584 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2564500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2566000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 118500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1399,20 +1392,20 @@ system.iobus.reqLayer22.occupancy 55500 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2121000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2120500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 84230549 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 86466426 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16458000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16844000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements system.iocache.tags.tagsinuse 1.261273 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694926918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1694926915000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 1.261273 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078830 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078830 # Average percentage of cache occupancy @@ -1429,14 +1422,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9458962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9458962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2126843587 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2126843587 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9458962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9458962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9458962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9458962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9575962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9575962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2102569464 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2102569464 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9575962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9575962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9575962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9575962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1453,77 +1446,77 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54676.080925 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54676.080925 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 51185.107504 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 51185.107504 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54676.080925 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54676.080925 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55352.381503 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 55352.381503 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 50600.920870 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 50600.920870 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 55352.381503 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 55352.381503 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5.166667 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16272 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 16272 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 69 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 69 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 69 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 69 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6008962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6008962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1313243587 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1313243587 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 6008962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6008962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 6008962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6008962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.391606 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.391606 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.398844 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.398844 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 87086.405797 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80705.726831 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80705.726831 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16656 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 16656 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6075962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6075962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1269053528 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1269053528 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 6075962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6075962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 6075962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6075962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.400847 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.400847 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86799.457143 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.974544 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.974544 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 86799.457143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 86799.457143 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 337614 # number of replacements -system.l2c.tags.tagsinuse 65425.004009 # Cycle average of tags in use -system.l2c.tags.total_refs 4005267 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65425.009940 # Cycle average of tags in use +system.l2c.tags.total_refs 4005222 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 402776 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.944155 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 9.944043 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54894.973613 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2664.591905 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2878.625445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 441.912379 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 553.808439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2003.360689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1987.731539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 54894.998559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2664.593878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2878.621970 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 441.912362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 553.890082 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2003.349443 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1987.643647 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.837631 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.040658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.043924 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.006743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008450 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008452 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.030569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.030330 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.030329 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.998306 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id @@ -1532,12 +1525,12 @@ system.l2c.tags.age_task_id_blocks_1024::2 6136 # system.l2c.tags.age_task_id_blocks_1024::3 2779 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 55356 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38412750 # Number of tag accesses -system.l2c.tags.data_accesses 38412750 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 835859 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 835859 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 963177 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 963177 # number of WritebackClean hits +system.l2c.tags.tag_accesses 38412363 # Number of tag accesses +system.l2c.tags.data_accesses 38412363 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 835864 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 835864 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 963150 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 963150 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits @@ -1545,31 +1538,31 @@ system.l2c.UpgradeReq_hits::total 13 # nu system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 90398 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 24435 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 72282 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187115 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 504328 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 122989 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 322557 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 949874 # number of ReadCleanReq hits +system.l2c.ReadExReq_hits::cpu1.data 24436 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 72279 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187113 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 504325 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 122994 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 322528 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 949847 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 485259 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 78702 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 253717 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 817678 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 504328 # number of demand (read+write) hits +system.l2c.ReadSharedReq_hits::cpu1.data 78708 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 253716 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 817683 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 504325 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 575657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 122989 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 103137 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 322557 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 325999 # number of demand (read+write) hits -system.l2c.demand_hits::total 1954667 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 504328 # number of overall hits +system.l2c.demand_hits::cpu1.inst 122994 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 103144 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 322528 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 325995 # number of demand (read+write) hits +system.l2c.demand_hits::total 1954643 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 504325 # number of overall hits system.l2c.overall_hits::cpu0.data 575657 # number of overall hits -system.l2c.overall_hits::cpu1.inst 122989 # number of overall hits -system.l2c.overall_hits::cpu1.data 103137 # number of overall hits -system.l2c.overall_hits::cpu2.inst 322557 # number of overall hits -system.l2c.overall_hits::cpu2.data 325999 # number of overall hits -system.l2c.overall_hits::total 1954667 # number of overall hits +system.l2c.overall_hits::cpu1.inst 122994 # number of overall hits +system.l2c.overall_hits::cpu1.data 103144 # number of overall hits +system.l2c.overall_hits::cpu2.inst 322528 # number of overall hits +system.l2c.overall_hits::cpu2.data 325995 # number of overall hits +system.l2c.overall_hits::total 1954643 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 22 # number of UpgradeReq misses @@ -1578,57 +1571,57 @@ system.l2c.SCUpgradeReq_misses::cpu2.data 1 # n system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 74645 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13952 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 27192 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115789 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 27191 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115788 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 7793 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 2219 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu2.inst 4231 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 14243 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 250829 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 10186 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 12435 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 273450 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 10193 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 12429 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 273451 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 7793 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 325474 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 2219 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 24138 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 24145 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 4231 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 39627 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 39620 # number of demand (read+write) misses system.l2c.demand_misses::total 403482 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 7793 # number of overall misses system.l2c.overall_misses::cpu0.data 325474 # number of overall misses system.l2c.overall_misses::cpu1.inst 2219 # number of overall misses -system.l2c.overall_misses::cpu1.data 24138 # number of overall misses +system.l2c.overall_misses::cpu1.data 24145 # number of overall misses system.l2c.overall_misses::cpu2.inst 4231 # number of overall misses -system.l2c.overall_misses::cpu2.data 39627 # number of overall misses +system.l2c.overall_misses::cpu2.data 39620 # number of overall misses system.l2c.overall_misses::total 403482 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu2.data 574000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 574000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu2.data 80500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1779331000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 3689980500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5469311500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 292933000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 566377000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 859310000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 1287928500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 1552705500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 2840634000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 292933000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3067259500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 566377000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 5242686000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9169255500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 292933000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3067259500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 566377000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 5242686000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9169255500 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 835859 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 835859 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 963177 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 963177 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_miss_latency::cpu2.data 551000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 551000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu2.data 77500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 77500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1777468000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 3688796500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5466264500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 293360500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 567162500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 860523000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 1287741500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 1552243000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 2839984500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 293360500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3065209500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 567162500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 5241039500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9166772000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 293360500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3065209500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 567162500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 5241039500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9166772000 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 835864 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 835864 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 963150 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 963150 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 23 # number of UpgradeReq accesses(hits+misses) @@ -1637,31 +1630,31 @@ system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 165043 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 38387 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 99474 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302904 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 512121 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 125208 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 326788 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 964117 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 38388 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 99470 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302901 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 512118 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 125213 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 326759 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 964090 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.data 736088 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 88888 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 266152 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1091128 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 512121 # number of demand (read+write) accesses +system.l2c.ReadSharedReq_accesses::cpu1.data 88901 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 266145 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1091134 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 512118 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 901131 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 125208 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 127275 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 326788 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 365626 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2358149 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 512121 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 125213 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 127289 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 326759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 365615 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2358125 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 512118 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 901131 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 125208 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 127275 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 326788 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 365626 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2358149 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 125213 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 127289 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 326759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 365615 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2358125 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 0.608696 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.628571 # miss rate for UpgradeReq accesses @@ -1669,54 +1662,54 @@ system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.333333 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.452276 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.363456 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.273358 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382263 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.363447 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.273359 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382264 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015217 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.017723 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.012947 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.014773 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.017722 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.012948 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.014774 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.340760 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.114594 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.046721 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.114656 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.046700 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.250612 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.015217 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.361184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.017723 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.189652 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.012947 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.108381 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171101 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.017722 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.189686 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.012948 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.108365 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171103 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.015217 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.361184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.017723 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.189652 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.012947 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.108381 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171101 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 41000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 26090.909091 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 80500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 40250 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127532.325115 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 135700.959841 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 47235.156189 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132011.266336 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133863.625620 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 60332.092958 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 126441.046534 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 124865.741858 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 10388.129457 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 132011.266336 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 127071.816223 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 133863.625620 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 132300.855477 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 22725.314884 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 132011.266336 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 127071.816223 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 133863.625620 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 132300.855477 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 22725.314884 # average overall miss latency +system.l2c.overall_miss_rate::cpu1.inst 0.017722 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.189686 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.012948 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.108365 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171103 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 39357.142857 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 25045.454545 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 77500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 38750 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127398.795872 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 135662.406679 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 47209.248800 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132203.920685 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 134049.279130 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 60417.257600 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 126335.867752 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 124888.808432 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 10385.716271 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 132203.920685 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 126950.072479 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 134049.279130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 132282.672892 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 22719.159715 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 132203.920685 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 126950.072479 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 134049.279130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 132282.672892 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 22719.159715 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1732,23 +1725,23 @@ system.l2c.UpgradeReq_mshr_misses::total 14 # nu system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 13952 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 27192 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 41144 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 27191 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 41143 # number of ReadExReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2219 # number of ReadCleanReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 4231 # number of ReadCleanReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::total 6450 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 10186 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12435 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 22621 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 10193 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12429 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 22622 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 2219 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 24138 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 24145 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.inst 4231 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 39627 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 39620 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 70215 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 2219 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 24138 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 24145 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.inst 4231 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 39627 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 39620 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 70215 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable @@ -1759,191 +1752,191 @@ system.l2c.WriteReq_mshr_uncacheable::total 3516 # system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 1004500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1004500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 70500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1639811000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3418060500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5057871500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 270743000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 524067000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 794810000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1186068500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1461566500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 2647635000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 270743000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2825879500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 524067000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 4879627000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8500316500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 270743000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2825879500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 524067000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 4879627000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8500316500 # number of overall MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 960500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 960500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 67500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 67500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1637948000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3416886500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5054834500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 271170500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 524851004 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 796021504 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1185811500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1461164000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 2646975500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 271170500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2823759500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 524851004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 4878050500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8497831504 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 271170500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2823759500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 524851004 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 4878050500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8497831504 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 276798000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 281540000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 558338000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 353898000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 353901000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402187000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 756085000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 630696000 # number of overall MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 756088000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 630699000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu2.data 683727000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1314423000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1314426000 # number of overall MSHR uncacheable cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.608696 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.333333 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.363456 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.273358 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.135832 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.363447 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.273359 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.135830 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006690 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.114594 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046721 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.029775 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.029775 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 71750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71750 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117532.325115 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125700.959841 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 122930.961987 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123226.356589 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116441.046534 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117536.509851 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117043.234163 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.114656 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046700 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020733 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.189686 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.108365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.029776 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.189686 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.108365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.029776 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68607.142857 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68607.142857 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117398.795872 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125662.406679 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 122860.134166 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123414.186667 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116335.867752 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117560.865717 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117008.907258 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 116950.072479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123120.911156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121025.870597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 116950.072479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123120.911156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121025.870597 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208275.395034 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 212804.232804 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210534.690799 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218725.587145 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218727.441286 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211900.421496 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215041.240046 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214012.894469 # average overall mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215042.093288 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214013.912453 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212271.654766 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 213103.599222 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213104.085603 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294754 # Transaction distribution +system.membus.trans_dist::ReadResp 294755 # Transaction distribution system.membus.trans_dist::WriteReq 9812 # Transaction distribution system.membus.trans_dist::WriteResp 9812 # Transaction distribution system.membus.trans_dist::WritebackDirty 116723 # Transaction distribution -system.membus.trans_dist::CleanEvict 261691 # Transaction distribution +system.membus.trans_dist::CleanEvict 261851 # Transaction distribution system.membus.trans_dist::UpgradeReq 160 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 162 # Transaction distribution -system.membus.trans_dist::ReadExReq 115651 # Transaction distribution -system.membus.trans_dist::ReadExResp 115651 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287866 # Transaction distribution +system.membus.trans_dist::UpgradeResp 116 # Transaction distribution +system.membus.trans_dist::ReadExReq 115650 # Transaction distribution +system.membus.trans_dist::ReadExResp 115650 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287867 # Transaction distribution system.membus.trans_dist::BadAddressError 256 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 24896 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143238 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 512 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177708 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1302629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1286086 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30604608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 30650192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33314576 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 159 # Total snoops (count) -system.membus.snoop_fanout::samples 840768 # Request fanout histogram +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33314512 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 160 # Total snoops (count) +system.membus.snoop_fanout::samples 840765 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840768 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840765 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840768 # Request fanout histogram -system.membus.reqLayer0.occupancy 11147000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840765 # Request fanout histogram +system.membus.reqLayer0.occupancy 11148000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 348692458 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 350987320 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 375048955 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 374958750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 27286702 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 368038 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4714972 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2357166 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4714924 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2357142 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1129 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1129 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062235 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2062215 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 878682 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 963177 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 599628 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 879068 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 963447 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 600902 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 39 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302904 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302904 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 964165 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091197 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302901 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302901 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 964138 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091204 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 256 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 16272 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891480 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7105575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123348160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142745680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266093840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421214 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4208473 # Request fanout histogram +system.toL2Bus.trans_dist::InvalidateReq 16656 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891696 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4215380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7107076 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123363712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142746256 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266109968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421211 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4208443 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.000983 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.031334 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4204337 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4204307 99.90% 99.90% # Request fanout histogram system.toL2Bus.snoop_fanout::1 4136 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4208473 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1783329500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4208443 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1783289500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 99462 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 678448171 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 678414167 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 743541954 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 743545456 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |