diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
3 files changed, 3604 insertions, 3613 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 40315f031..8dbc85977 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,146 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.898811 # Number of seconds simulated -sim_ticks 1898811181000 # Number of ticks simulated -final_tick 1898811181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.899762 # Number of seconds simulated +sim_ticks 1899762444000 # Number of ticks simulated +final_tick 1899762444000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163774 # Simulator instruction rate (inst/s) -host_op_rate 163774 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5540525376 # Simulator tick rate (ticks/s) -host_mem_usage 339592 # Number of bytes of host memory used -host_seconds 342.71 # Real time elapsed on the host -sim_insts 56127436 # Number of instructions simulated -sim_ops 56127436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 739584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24165760 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 241984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1058688 # Number of bytes read from this memory -system.physmem.bytes_read::total 28856384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 739584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 241984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7824192 # Number of bytes written to this memory -system.physmem.bytes_written::total 7824192 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377590 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3781 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16542 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122253 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122253 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 389498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12726784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 127440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 557553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15197079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 127440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4120574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4120574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4120574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12726784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 127440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 557553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19317653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450881 # Total number of read requests seen -system.physmem.writeReqs 122253 # Total number of write requests seen -system.physmem.cpureqs 582476 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28856384 # Total number of bytes read from memory -system.physmem.bytesWritten 7824192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28856384 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7824192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 66 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3389 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28343 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28155 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27898 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8087 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7991 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7846 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7721 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7765 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7705 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7457 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7400 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7239 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7345 # Track writes on a per bank basis +host_inst_rate 165662 # Simulator instruction rate (inst/s) +host_op_rate 165662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5547317951 # Simulator tick rate (ticks/s) +host_mem_usage 338604 # Number of bytes of host memory used +host_seconds 342.47 # Real time elapsed on the host +sim_insts 56733550 # Number of instructions simulated +sim_ops 56733550 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 853120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24660608 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 536896 # Number of bytes read from this memory +system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 853120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7795456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7795456 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385322 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121804 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121804 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12980890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15173333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 514052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4103385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4103385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4103385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12980890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 282612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19276718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450402 # Total number of read requests seen +system.physmem.writeReqs 121804 # Total number of write requests seen +system.physmem.cpureqs 579957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28825728 # Total number of bytes read from memory +system.physmem.bytesWritten 7795456 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7795456 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5038 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28521 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27882 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27954 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7706 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7580 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7703 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7587 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7619 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7293 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7271 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7481 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7325 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7481 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1873 # Number of times wr buffer was full causing retry -system.physmem.totGap 1898811160000 # Total gap between requests +system.physmem.numWrRetry 2713 # Number of times wr buffer was full causing retry +system.physmem.totGap 1899757983000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450881 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 124126 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3389 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 320280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.readPktSize::6 450402 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 121804 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 319830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -151,226 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 8261632913 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 16092226663 # Sum of mem lat for all requests -system.physmem.totBusLat 2254075000 # Total cycles spent in databus access -system.physmem.totBankLat 5576518750 # Total cycles spent in bank access -system.physmem.avgQLat 18325.99 # Average queueing delay per request -system.physmem.avgBankLat 12369.86 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5296 # 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Total cycles spent in databus access +system.physmem.totBankLat 5553295000 # Total cycles spent in bank access +system.physmem.avgQLat 17222.89 # Average queueing delay per request +system.physmem.avgBankLat 12331.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35695.85 # Average memory access latency -system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34554.21 # Average memory access latency +system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.10 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28764500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392137500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2009193000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 611400000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2620593000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3372566000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 640164500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4012730500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271875 # 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miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -549,40 +534,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120840.897727 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120840.897727 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256518.502262 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256518.502262 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255946.242427 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255946.242427 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 284980 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120796.598870 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254843.468570 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 254843.468570 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 254274.888063 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 254274.888063 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 281737 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27128 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 26988 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.505013 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.439343 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41522 # number of writebacks -system.iocache.writebacks::total 41522 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12115250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12115250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8496857845 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8496857845 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8508973095 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8508973095 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8508973095 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8508973095 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12176249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8427244570 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8427244570 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8439420819 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8439420819 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8439420819 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8439420819 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -591,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68836.647727 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68836.647727 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204487.337433 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204487.337433 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202812.008327 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 202812.008327 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,35 +597,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 10581841 # Number of BP lookups -system.cpu0.branchPred.condPredicted 8959361 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 281985 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7046138 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4567974 # Number of BTB hits +system.cpu0.branchPred.lookups 12335027 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10393813 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 330568 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7867422 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5239774 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.829471 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 656046 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29257 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.600902 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 784891 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32664 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7560815 # DTB read hits -system.cpu0.dtb.read_misses 30461 # DTB read misses -system.cpu0.dtb.read_acv 538 # DTB read access violations -system.cpu0.dtb.read_accesses 623625 # DTB read accesses -system.cpu0.dtb.write_hits 5040625 # DTB write hits -system.cpu0.dtb.write_misses 7520 # DTB write misses -system.cpu0.dtb.write_acv 334 # DTB write access violations -system.cpu0.dtb.write_accesses 206551 # DTB write accesses -system.cpu0.dtb.data_hits 12601440 # DTB hits -system.cpu0.dtb.data_misses 37981 # DTB misses -system.cpu0.dtb.data_acv 872 # DTB access violations -system.cpu0.dtb.data_accesses 830176 # DTB accesses -system.cpu0.itb.fetch_hits 911527 # ITB hits -system.cpu0.itb.fetch_misses 30644 # ITB misses -system.cpu0.itb.fetch_acv 921 # ITB acv -system.cpu0.itb.fetch_accesses 942171 # ITB accesses +system.cpu0.dtb.read_hits 8753494 # DTB read hits +system.cpu0.dtb.read_misses 29787 # DTB read misses +system.cpu0.dtb.read_acv 536 # DTB read access violations +system.cpu0.dtb.read_accesses 623801 # DTB read accesses +system.cpu0.dtb.write_hits 5745053 # DTB write hits +system.cpu0.dtb.write_misses 8131 # DTB write misses +system.cpu0.dtb.write_acv 346 # DTB write access violations +system.cpu0.dtb.write_accesses 207769 # DTB write accesses +system.cpu0.dtb.data_hits 14498547 # DTB hits +system.cpu0.dtb.data_misses 37918 # DTB misses +system.cpu0.dtb.data_acv 882 # DTB access violations +system.cpu0.dtb.data_accesses 831570 # DTB accesses +system.cpu0.itb.fetch_hits 986254 # ITB hits +system.cpu0.itb.fetch_misses 27996 # ITB misses +system.cpu0.itb.fetch_acv 985 # ITB acv +system.cpu0.itb.fetch_accesses 1014250 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -653,269 +638,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 89753559 # number of cpu cycles simulated +system.cpu0.numCycles 101860002 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21107693 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 54367118 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 10581841 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5224020 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10262063 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1458036 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 30903552 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 30207 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 199263 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 186050 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6657299 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 195043 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 63623646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.854511 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.189260 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24837828 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63180848 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12335027 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6024665 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11886569 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1686741 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36619319 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 32566 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195803 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 292498 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7637223 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223881 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74953254 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.842937 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.180655 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 53361583 83.87% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 672459 1.06% 84.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1316592 2.07% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 583007 0.92% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2295308 3.61% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 445844 0.70% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 472664 0.74% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 743494 1.17% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3732695 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63066685 84.14% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 761791 1.02% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1555671 2.08% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 698950 0.93% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2562608 3.42% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 513718 0.69% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568258 0.76% 93.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 822289 1.10% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4403284 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 63623646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.117899 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.605738 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 22232367 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 30357900 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9303163 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 825009 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 905206 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 419214 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 29823 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53368764 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 92723 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 905206 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 23093913 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11627753 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15736016 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8768275 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3492481 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50503220 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 393829 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1341574 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 33876980 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 61564678 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 61250531 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 314147 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 29813717 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4063255 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1268860 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 187899 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9409132 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7922191 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5257693 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 964170 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 651506 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 44858999 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1558626 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 43884207 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 67322 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4967350 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2566909 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1055206 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 63623646 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.689747 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329677 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74953254 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.121098 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.620271 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26053984 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36115594 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10809914 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 920077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1053684 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507198 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35097 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62027396 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105101 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1053684 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27061357 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14627985 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18001405 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10130422 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4078399 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58721682 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6643 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 642092 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1424191 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39329555 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71492090 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71110334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 381756 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34559979 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4769568 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1435328 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 208629 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11112444 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9161053 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6009456 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1123532 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 742915 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52110985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1787265 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50968553 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87650 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5843461 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2979197 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1210641 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74953254 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680005 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329199 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 43919799 69.03% 69.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9075335 14.26% 83.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4098408 6.44% 89.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2614119 4.11% 93.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2006211 3.15% 97.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1055812 1.66% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 551217 0.87% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 263467 0.41% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 39278 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52302643 69.78% 69.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10307098 13.75% 83.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4640048 6.19% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3056236 4.08% 93.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2433864 3.25% 97.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1212107 1.62% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 643283 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 306838 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 51137 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 63623646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74953254 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62740 10.88% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 271097 47.03% 57.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 242616 42.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83602 12.51% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 310944 46.54% 59.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 273567 40.95% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30137882 68.68% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 45897 0.10% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14285 0.03% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7870096 17.93% 86.76% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5096964 11.61% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 713427 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35163137 68.99% 69.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56167 0.11% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9108259 17.87% 87.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5813234 11.41% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 806455 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 43884207 # Type of FU issued -system.cpu0.iq.rate 0.488941 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 576453 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013136 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 151584762 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 51176195 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43017955 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 451072 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 219118 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 212749 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 44220901 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 235982 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 487348 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50968553 # Type of FU issued +system.cpu0.iq.rate 0.500378 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 668113 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013108 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 177097926 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59488760 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 49954313 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 548196 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 265355 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 258816 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51345953 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 286939 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 543981 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 958085 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2941 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10552 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 366818 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1095536 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3484 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12649 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 447527 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13186 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 117811 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18428 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 123543 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 905206 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8069118 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 677733 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49115212 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 536411 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7922191 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5257693 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1375945 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 564143 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4652 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10552 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 138850 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 301409 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 440259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 43556869 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7611218 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 327337 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1053684 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10434033 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 794004 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57098821 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 607587 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9161053 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6009456 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1574353 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 581874 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5211 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12649 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164505 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 346352 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 510857 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50581166 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8806339 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387386 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2697587 # number of nop insts executed -system.cpu0.iew.exec_refs 12670581 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6879787 # Number of branches executed -system.cpu0.iew.exec_stores 5059363 # Number of stores executed -system.cpu0.iew.exec_rate 0.485294 # Inst execution rate -system.cpu0.iew.wb_sent 43311636 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43230704 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 21537449 # num instructions producing a value -system.cpu0.iew.wb_consumers 28771492 # num instructions consuming a value +system.cpu0.iew.exec_nop 3200571 # number of nop insts executed +system.cpu0.iew.exec_refs 14573024 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8058196 # Number of branches executed +system.cpu0.iew.exec_stores 5766685 # Number of stores executed +system.cpu0.iew.exec_rate 0.496575 # Inst execution rate +system.cpu0.iew.wb_sent 50300704 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50213129 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25063994 # num instructions producing a value +system.cpu0.iew.wb_consumers 33773959 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.481660 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.748569 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.492962 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742110 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5358562 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 503420 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 412035 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 62718440 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.696169 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.614251 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6307351 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 576624 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 477479 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73899570 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.685982 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.603952 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 46279929 73.79% 73.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6945490 11.07% 84.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3654930 5.83% 90.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2050520 3.27% 93.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1130391 1.80% 95.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 454158 0.72% 96.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 393863 0.63% 97.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 373108 0.59% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1436051 2.29% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54870784 74.25% 74.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7931577 10.73% 84.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4331737 5.86% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2351789 3.18% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1313178 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 548800 0.74% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466874 0.63% 97.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 433224 0.59% 97.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1651607 2.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 62718440 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 43662606 # Number of instructions committed -system.cpu0.commit.committedOps 43662606 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73899570 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50693798 # Number of instructions committed +system.cpu0.commit.committedOps 50693798 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11854981 # Number of memory references committed -system.cpu0.commit.loads 6964106 # Number of loads committed -system.cpu0.commit.membars 168172 # Number of memory barriers committed -system.cpu0.commit.branches 6551324 # Number of branches committed -system.cpu0.commit.fp_insts 210613 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 40489033 # Number of committed integer instructions. -system.cpu0.commit.function_calls 540020 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1436051 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13627446 # Number of memory references committed +system.cpu0.commit.loads 8065517 # Number of loads committed +system.cpu0.commit.membars 196376 # Number of memory barriers committed +system.cpu0.commit.branches 7658577 # Number of branches committed +system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46944411 # Number of committed integer instructions. +system.cpu0.commit.function_calls 646517 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1651607 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 110111593 # The number of ROB reads -system.cpu0.rob.rob_writes 98948174 # The number of ROB writes -system.cpu0.timesIdled 879648 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26129913 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3707863967 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41199881 # Number of Instructions Simulated -system.cpu0.committedOps 41199881 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 41199881 # Number of Instructions Simulated -system.cpu0.cpi 2.178491 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.178491 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.459033 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.459033 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 57370310 # number of integer regfile reads -system.cpu0.int_regfile_writes 31317782 # number of integer regfile writes -system.cpu0.fp_regfile_reads 104569 # number of floating regfile reads -system.cpu0.fp_regfile_writes 105332 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1463769 # number of misc regfile reads -system.cpu0.misc_regfile_writes 718581 # number of misc regfile writes +system.cpu0.rob.rob_reads 129054613 # The number of ROB reads +system.cpu0.rob.rob_writes 115056832 # The number of ROB writes +system.cpu0.timesIdled 1051988 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26906748 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3697658339 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47774945 # Number of Instructions Simulated +system.cpu0.committedOps 47774945 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47774945 # Number of Instructions Simulated +system.cpu0.cpi 2.132080 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.132080 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.469026 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.469026 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66569976 # number of integer regfile reads +system.cpu0.int_regfile_writes 36353057 # number of integer regfile writes +system.cpu0.fp_regfile_reads 127037 # number of floating regfile reads +system.cpu0.fp_regfile_writes 128676 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1691103 # number of misc regfile reads +system.cpu0.misc_regfile_writes 806046 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -947,245 +932,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 728874 # number of replacements -system.cpu0.icache.tagsinuse 510.265304 # Cycle average of tags in use -system.cpu0.icache.total_refs 5890439 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 729383 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.075920 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20962478000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.265304 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996612 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996612 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5890439 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5890439 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5890439 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5890439 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5890439 # number of overall hits -system.cpu0.icache.overall_hits::total 5890439 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 766860 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 766860 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 766860 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 766860 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 766860 # number of overall misses -system.cpu0.icache.overall_misses::total 766860 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10795349496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10795349496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10795349496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10795349496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10795349496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10795349496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6657299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6657299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6657299 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6657299 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6657299 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6657299 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.115191 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.115191 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.115191 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.115191 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.115191 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.115191 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14077.340709 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14077.340709 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14077.340709 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14077.340709 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2177 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 468 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 128 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.007812 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 468 # average number of cycles each access was blocked +system.cpu0.icache.replacements 863258 # number of replacements +system.cpu0.icache.tagsinuse 510.308888 # Cycle average of tags in use +system.cpu0.icache.total_refs 6729374 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 863770 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.790701 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.308888 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996697 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996697 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6729374 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6729374 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6729374 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6729374 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6729374 # number of overall hits +system.cpu0.icache.overall_hits::total 6729374 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 907848 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 907848 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 907848 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 907848 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 907848 # number of overall misses +system.cpu0.icache.overall_misses::total 907848 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12809117491 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12809117491 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12809117491 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12809117491 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12809117491 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12809117491 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7637222 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7637222 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7637222 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7637222 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7637222 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7637222 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118871 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118871 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118871 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118871 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118871 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118871 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14109.319502 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14109.319502 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14109.319502 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14109.319502 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5737 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 35.633540 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37318 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 37318 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37318 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 37318 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37318 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 37318 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 729542 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 729542 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 729542 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 729542 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 729542 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 729542 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8901782997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8901782997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8901782997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8901782997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8901782997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8901782997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109585 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.109585 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.109585 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12201.878709 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43927 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43927 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43927 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43927 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43927 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43927 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863921 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 863921 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 863921 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 863921 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 863921 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 863921 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10545414492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10545414492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10545414492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10545414492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10545414492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10545414492 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113120 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113120 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113120 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12206.456947 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1051655 # number of replacements -system.cpu0.dcache.tagsinuse 479.291529 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8945957 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1052167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.502412 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1272639 # number of replacements +system.cpu0.dcache.tagsinuse 505.727163 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10328741 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1273151 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.112738 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.291529 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.936116 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.936116 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5529733 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5529733 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3096724 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3096724 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 145068 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 145068 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 167974 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 167974 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8626457 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8626457 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8626457 # number of overall hits -system.cpu0.dcache.overall_hits::total 8626457 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1297164 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1297164 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1613226 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1613226 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 15668 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 15668 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2910390 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2910390 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2910390 # number of overall misses -system.cpu0.dcache.overall_misses::total 2910390 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 30009249500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 30009249500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61556935480 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 61556935480 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 231982500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 231982500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 91566184980 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 91566184980 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 91566184980 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 91566184980 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826897 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6826897 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4709950 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4709950 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160736 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 160736 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168740 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 168740 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11536847 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11536847 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11536847 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11536847 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.190008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.190008 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342514 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.342514 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.097477 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097477 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252269 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.252269 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252269 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.252269 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23134.506893 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23134.506893 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38157.663886 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38157.663886 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14806.133521 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14806.133521 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6110.313316 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6110.313316 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31461.826415 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31461.826415 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2024468 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 671 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 45038 # number of cycles access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 505.727163 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987748 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987748 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6350419 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6350419 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3622179 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3622179 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160143 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 160143 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184450 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 184450 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9972598 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9972598 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9972598 # number of overall hits +system.cpu0.dcache.overall_hits::total 9972598 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1584754 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1584754 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1737731 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1737731 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20393 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20393 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2991 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2991 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3322485 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3322485 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3322485 # number of overall misses +system.cpu0.dcache.overall_misses::total 3322485 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34254700500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34254700500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66543857651 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 66543857651 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293744000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 293744000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21938000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 21938000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 100798558151 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 100798558151 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 100798558151 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 100798558151 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935173 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7935173 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359910 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5359910 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180536 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 180536 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187441 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187441 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13295083 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13295083 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13295083 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13295083 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199713 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199713 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324209 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324209 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112958 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112958 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015957 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015957 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249903 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249903 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249903 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249903 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21615.153204 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21615.153204 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.531997 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.531997 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14404.158290 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14404.158290 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7334.670679 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7334.670679 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30338.303454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30338.303454 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2157066 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2274 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48232 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.950220 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 95.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.722715 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 324.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 554167 # number of writebacks -system.cpu0.dcache.writebacks::total 554167 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 497870 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 497870 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1365575 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1365575 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3772 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3772 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1863445 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1863445 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1863445 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1863445 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 799294 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 799294 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 247651 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 247651 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 11896 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11896 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1046945 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1046945 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1046945 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1046945 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19199342000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19199342000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8924614838 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8924614838 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148344000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148344000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3148500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3148500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 28123956838 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 28123956838 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 28123956838 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 28123956838 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 991461500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 991461500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668991999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668991999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2660453499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2660453499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117080 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117080 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004540 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004540 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090748 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090748 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24020.375481 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24020.375481 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36037.063602 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36037.063602 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12470.073974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.073974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4110.313316 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4110.313316 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 748565 # number of writebacks +system.cpu0.dcache.writebacks::total 748565 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585493 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 585493 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465453 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1465453 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4489 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4489 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2050946 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2050946 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2050946 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2050946 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999261 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 999261 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272278 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272278 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2991 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2991 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271539 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1271539 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271539 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1271539 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21490960000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21490960000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698199220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9698199220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183494500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183494500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15956000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15956000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31189159220 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31189159220 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31189159220 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31189159220 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2130479499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2130479499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3585386499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3585386499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125928 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125928 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015957 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095640 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095640 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21506.853565 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21506.853565 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35618.739744 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35618.739744 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.632042 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.632042 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5334.670679 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5334.670679 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,35 +1178,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4327546 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3555815 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 137782 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2736457 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1529937 # Number of BTB hits +system.cpu1.branchPred.lookups 2650086 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2188228 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 78181 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1530727 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 883629 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 55.909411 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 311519 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 14646 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.726100 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 184091 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8336 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3068448 # DTB read hits -system.cpu1.dtb.read_misses 13337 # DTB read misses -system.cpu1.dtb.read_acv 21 # DTB read access violations -system.cpu1.dtb.read_accesses 325420 # DTB read accesses -system.cpu1.dtb.write_hits 1915630 # DTB write hits -system.cpu1.dtb.write_misses 2521 # DTB write misses -system.cpu1.dtb.write_acv 68 # DTB write access violations -system.cpu1.dtb.write_accesses 132592 # DTB write accesses -system.cpu1.dtb.data_hits 4984078 # DTB hits -system.cpu1.dtb.data_misses 15858 # DTB misses -system.cpu1.dtb.data_acv 89 # DTB access violations -system.cpu1.dtb.data_accesses 458012 # DTB accesses -system.cpu1.itb.fetch_hits 498592 # ITB hits -system.cpu1.itb.fetch_misses 6957 # ITB misses -system.cpu1.itb.fetch_acv 210 # ITB acv -system.cpu1.itb.fetch_accesses 505549 # ITB accesses +system.cpu1.dtb.read_hits 1963408 # DTB read hits +system.cpu1.dtb.read_misses 10761 # DTB read misses +system.cpu1.dtb.read_acv 27 # DTB read access violations +system.cpu1.dtb.read_accesses 325022 # DTB read accesses +system.cpu1.dtb.write_hits 1266270 # DTB write hits +system.cpu1.dtb.write_misses 2185 # DTB write misses +system.cpu1.dtb.write_acv 66 # DTB write access violations +system.cpu1.dtb.write_accesses 133146 # DTB write accesses +system.cpu1.dtb.data_hits 3229678 # DTB hits +system.cpu1.dtb.data_misses 12946 # DTB misses +system.cpu1.dtb.data_acv 93 # DTB access violations +system.cpu1.dtb.data_accesses 458168 # DTB accesses +system.cpu1.itb.fetch_hits 437746 # ITB hits +system.cpu1.itb.fetch_misses 6892 # ITB misses +system.cpu1.itb.fetch_acv 236 # ITB acv +system.cpu1.itb.fetch_accesses 444638 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1234,508 +1219,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 28341850 # number of cpu cycles simulated +system.cpu1.numCycles 16144974 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9666058 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 20746660 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4327546 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1841456 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3769607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 667538 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 11516910 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24752 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65971 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 157862 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2430728 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 90320 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 25638274 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.809207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.171586 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6121442 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12493756 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2650086 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1067720 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2240899 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 409596 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6344466 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65860 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 57508 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1513677 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 52961 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15118787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.826373 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.200485 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 21868667 85.30% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 217825 0.85% 86.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 471767 1.84% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 290566 1.13% 89.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 572691 2.23% 91.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 192619 0.75% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 225020 0.88% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 283328 1.11% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1515791 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12877888 85.18% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 143885 0.95% 86.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 241695 1.60% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 180531 1.19% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 309762 2.05% 90.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 120449 0.80% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 135595 0.90% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 201831 1.33% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 907151 6.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 25638274 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.152691 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.732015 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 9733408 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 11767392 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3496252 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 218180 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 423041 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 197160 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 14107 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 20339380 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 42509 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 423041 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 10090973 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3436285 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 7189136 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 3265501 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1233336 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 19035683 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 302354 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 266371 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 12573410 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 22727510 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 22552449 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 175061 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 10671795 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1901615 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 598380 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 62207 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3655619 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3246585 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2021315 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 341799 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 191681 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 16730301 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 718132 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 16236732 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 38678 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2401085 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1178363 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 514161 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 25638274 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.633301 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.313801 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15118787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164143 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.773848 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6052870 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6602402 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2094481 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 114057 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 254976 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 116126 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7500 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12249807 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22555 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 254976 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6262682 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 497209 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5456490 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1996397 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 651031 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11355545 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 56660 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 160008 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7474719 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13559101 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13415671 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 143430 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6386740 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1087979 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 456269 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 43986 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2005882 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2076975 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1341554 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 190968 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 103806 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9970569 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 502731 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9700952 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 30075 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1449475 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 723922 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 361264 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15118787 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.641649 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.316312 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 18618463 72.62% 72.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3106773 12.12% 84.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1368758 5.34% 90.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 986929 3.85% 93.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 856057 3.34% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 349630 1.36% 98.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 219211 0.86% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 115612 0.45% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 16841 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10852712 71.78% 71.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1956314 12.94% 84.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 839077 5.55% 90.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 560111 3.70% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 472963 3.13% 97.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 218451 1.44% 98.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 140254 0.93% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 70720 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8185 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 25638274 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15118787 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22162 7.89% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 144030 51.29% 59.18% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 114619 40.82% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3675 1.85% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 107078 53.97% 55.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 87636 44.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3527 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 10692350 65.85% 65.87% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 24766 0.15% 66.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11484 0.07% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3204356 19.74% 85.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1945149 11.98% 97.82% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 353337 2.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6050828 62.37% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16408 0.17% 62.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2054303 21.18% 83.89% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1289929 13.30% 97.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 273346 2.82% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 16236732 # Type of FU issued -system.cpu1.iq.rate 0.572889 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 280811 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017295 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 58178646 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 19730507 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 15830008 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 252581 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 122599 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 119620 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 16382145 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 131871 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 151965 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9700952 # Type of FU issued +system.cpu1.iq.rate 0.600865 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 198389 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020450 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 34541883 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11823308 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9430294 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 207272 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 101213 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 98067 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9787736 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 108079 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94689 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 456957 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 998 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3692 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 187617 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 288018 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 887 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1813 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 126704 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5626 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 16438 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 10289 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 423041 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2638422 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 162147 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 18437863 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 211636 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3246585 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2021315 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 643129 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 60084 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2152 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3692 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 66784 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 149088 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 215872 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 16080551 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3090638 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 156181 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 254976 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 327284 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 41516 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10988492 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 148711 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2076975 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1341554 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 455253 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 34417 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1886 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1813 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 35814 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 100493 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 136307 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9610649 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1981550 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 90303 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 989430 # number of nop insts executed -system.cpu1.iew.exec_refs 5015230 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2535241 # Number of branches executed -system.cpu1.iew.exec_stores 1924592 # Number of stores executed -system.cpu1.iew.exec_rate 0.567378 # Inst execution rate -system.cpu1.iew.wb_sent 15988482 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 15949628 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 7724743 # num instructions producing a value -system.cpu1.iew.wb_consumers 10881499 # num instructions consuming a value +system.cpu1.iew.exec_nop 515192 # number of nop insts executed +system.cpu1.iew.exec_refs 3256018 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1435370 # Number of branches executed +system.cpu1.iew.exec_stores 1274468 # Number of stores executed +system.cpu1.iew.exec_rate 0.595272 # Inst execution rate +system.cpu1.iew.wb_sent 9557675 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9528361 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4461159 # num instructions producing a value +system.cpu1.iew.wb_consumers 6259469 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.562759 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709897 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.590175 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712706 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2575173 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 203971 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 201824 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 25215233 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.626683 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.561616 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1504147 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 141467 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 128937 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14863811 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633307 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.576989 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 19361338 76.78% 76.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2499341 9.91% 86.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1261575 5.00% 91.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 645749 2.56% 94.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 410067 1.63% 95.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 193046 0.77% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 184525 0.73% 97.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 147171 0.58% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 512421 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11340708 76.30% 76.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1645490 11.07% 87.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 614395 4.13% 91.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 372484 2.51% 94.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 264045 1.78% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 106401 0.72% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 110365 0.74% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 108140 0.73% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 301783 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 25215233 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 15801951 # Number of instructions committed -system.cpu1.commit.committedOps 15801951 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14863811 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9413351 # Number of instructions committed +system.cpu1.commit.committedOps 9413351 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4623326 # Number of memory references committed -system.cpu1.commit.loads 2789628 # Number of loads committed -system.cpu1.commit.membars 68640 # Number of memory barriers committed -system.cpu1.commit.branches 2366242 # Number of branches committed -system.cpu1.commit.fp_insts 118314 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 14589318 # Number of committed integer instructions. -system.cpu1.commit.function_calls 250839 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 512421 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3003807 # Number of memory references committed +system.cpu1.commit.loads 1788957 # Number of loads committed +system.cpu1.commit.membars 45075 # Number of memory barriers committed +system.cpu1.commit.branches 1347256 # Number of branches committed +system.cpu1.commit.fp_insts 96765 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8723626 # Number of committed integer instructions. +system.cpu1.commit.function_calls 150668 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 301783 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 42991260 # The number of ROB reads -system.cpu1.rob.rob_writes 37176651 # The number of ROB writes -system.cpu1.timesIdled 292999 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2703576 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3768655732 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 14927555 # Number of Instructions Simulated -system.cpu1.committedOps 14927555 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 14927555 # Number of Instructions Simulated -system.cpu1.cpi 1.898626 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.898626 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.526697 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.526697 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20802804 # number of integer regfile reads -system.cpu1.int_regfile_writes 11409368 # number of integer regfile writes -system.cpu1.fp_regfile_reads 63889 # number of floating regfile reads -system.cpu1.fp_regfile_writes 64169 # number of floating regfile writes -system.cpu1.misc_regfile_reads 688257 # number of misc regfile reads -system.cpu1.misc_regfile_writes 294653 # number of misc regfile writes -system.cpu1.icache.replacements 359909 # number of replacements -system.cpu1.icache.tagsinuse 505.656535 # Cycle average of tags in use -system.cpu1.icache.total_refs 2054105 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 360421 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.699182 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 43308699500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 505.656535 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.987610 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.987610 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 2054105 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2054105 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2054105 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2054105 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2054105 # number of overall hits -system.cpu1.icache.overall_hits::total 2054105 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 376623 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 376623 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 376623 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 376623 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 376623 # number of overall misses -system.cpu1.icache.overall_misses::total 376623 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5258660997 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5258660997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5258660997 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5258660997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5258660997 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5258660997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2430728 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2430728 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2430728 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2430728 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2430728 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2430728 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154942 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154942 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154942 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.154942 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154942 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.154942 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.665575 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13962.665575 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13962.665575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13962.665575 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2479 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 1476 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 54 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 45.907407 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 1476 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 25388124 # The number of ROB reads +system.cpu1.rob.rob_writes 22088528 # The number of ROB writes +system.cpu1.timesIdled 132804 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1026187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782762516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8958605 # Number of Instructions Simulated +system.cpu1.committedOps 8958605 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8958605 # Number of Instructions Simulated +system.cpu1.cpi 1.802175 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.802175 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554885 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554885 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12390777 # number of integer regfile reads +system.cpu1.int_regfile_writes 6781957 # number of integer regfile writes +system.cpu1.fp_regfile_reads 53541 # number of floating regfile reads +system.cpu1.fp_regfile_writes 53239 # number of floating regfile writes +system.cpu1.misc_regfile_reads 527070 # number of misc regfile reads +system.cpu1.misc_regfile_writes 221606 # number of misc regfile writes +system.cpu1.icache.replacements 226821 # number of replacements +system.cpu1.icache.tagsinuse 470.843395 # Cycle average of tags in use +system.cpu1.icache.total_refs 1277714 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 227333 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.620451 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874198606000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.843395 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919616 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919616 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1277714 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1277714 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1277714 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1277714 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1277714 # number of overall hits +system.cpu1.icache.overall_hits::total 1277714 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 235963 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 235963 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 235963 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 235963 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 235963 # number of overall misses +system.cpu1.icache.overall_misses::total 235963 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3262757999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3262757999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3262757999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3262757999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3262757999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3262757999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1513677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1513677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1513677 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1513677 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1513677 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1513677 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155887 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.155887 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155887 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.155887 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155887 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.155887 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13827.413616 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13827.413616 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13827.413616 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13827.413616 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 255 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16134 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 16134 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 16134 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 16134 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 16134 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 16134 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 360489 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 360489 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 360489 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 360489 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 360489 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 360489 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4342433998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4342433998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4342433998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4342433998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4342433998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4342433998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148305 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.148305 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.148305 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12045.954240 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.954240 # 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number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 227395 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 227395 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 227395 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 227395 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711257499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711257499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711257499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2711257499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711257499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2711257499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150227 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.150227 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.150227 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11923.118358 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 377681 # number of replacements -system.cpu1.dcache.tagsinuse 497.778191 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3769592 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 378084 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 9.970250 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 35370260000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 497.778191 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.972223 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.972223 # 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number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 542018 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 408775 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 408775 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9102 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9102 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 780 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 780 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 950793 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 950793 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 950793 # number of overall misses -system.cpu1.dcache.overall_misses::total 950793 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8456828000 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.205598 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.205598 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15602.485526 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15602.485526 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33083.014514 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33083.014514 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14544.825313 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14544.825313 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7120.512821 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7120.512821 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.959975 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.959975 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1619180 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1619180 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 952866 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 952866 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33989 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 33989 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32614 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 32614 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2572046 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2572046 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2572046 # 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number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3173212000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3173212000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7555840185 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7555840185 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56288500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 56288500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22631500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22631500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10729052185 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10729052185 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10729052185 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10729052185 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1828431 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1828431 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172976 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1172976 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39385 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 39385 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35760 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 35760 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3001407 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3001407 # 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miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.143053 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143053 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.143053 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15164.620480 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15164.620480 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34327.564331 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34327.564331 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10431.523351 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10431.523351 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7193.738080 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7193.738080 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24988.418103 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24988.418103 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 240297 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7994 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3869 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 49.256943 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 62.108297 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 289966 # number of writebacks -system.cpu1.dcache.writebacks::total 289966 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 235266 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 235266 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 338145 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 338145 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1764 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1764 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 573411 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 573411 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 573411 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 573411 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 306752 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 306752 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 70630 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 70630 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7338 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7338 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 780 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 780 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 377382 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 377382 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 377382 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 377382 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4029157000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4029157000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2036960738 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2036960738 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87414000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87414000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3994000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3994000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6066117738 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6066117738 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6066117738 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6066117738 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491781000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491781000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 942840000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 942840000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1434621000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1434621000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107635 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107635 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.039801 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.039801 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130593 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130593 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015084 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015084 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.081604 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.081604 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13134.900506 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13134.900506 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28839.880193 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28839.880193 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11912.510221 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11912.510221 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5120.512821 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5120.512821 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 72108 # number of writebacks +system.cpu1.dcache.writebacks::total 72108 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129790 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 129790 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180827 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 180827 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 598 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 598 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 310617 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 310617 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 310617 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 310617 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79461 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 79461 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39283 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 39283 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4798 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4798 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3146 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3146 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 118744 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 118744 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 118744 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 118744 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 970446000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 970446000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1118523985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1118523985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38903500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38903500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16339500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16339500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088969985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2088969985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088969985 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2088969985 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30978500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30978500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647630000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647630000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043459 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043459 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033490 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033490 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039563 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039563 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12212.859138 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12212.859138 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28473.486877 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28473.486877 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.274281 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.274281 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5193.738080 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5193.738080 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1744,32 +1729,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4837 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 159566 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 54412 39.60% 39.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.10% 39.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.40% 41.09% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.10% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80931 58.90% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 137415 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 53531 49.06% 49.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.76% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 53515 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 109118 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866933879000 98.32% 98.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62852000 0.00% 98.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 558860500 0.03% 98.35% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8730000 0.00% 98.35% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 31246000500 1.65% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1898810322000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983809 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6548 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 181674 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64152 40.43% 40.43% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 136 0.09% 40.52% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.21% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92254 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158662 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63162 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 136 0.11% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.50% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 62971 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128389 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864385169000 98.14% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63278000 0.00% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567602000 0.03% 98.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 94599000 0.00% 98.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34650950500 1.82% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1899761598500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.661242 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.794076 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682583 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809198 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1801,60 +1786,60 @@ system.cpu0.kern.syscall::144 1 0.50% 99.01% # nu system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 107 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2838 1.96% 2.03% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.07% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.07% # number of callpals executed -system.cpu0.kern.callpal::swpipl 131134 90.46% 92.54% # number of callpals executed -system.cpu0.kern.callpal::rdps 6127 4.23% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.77% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4208 2.90% 99.68% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.23% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 144957 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6180 # number of protection mode switches +system.cpu0.kern.callpal::wripir 297 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151918 91.03% 93.32% # number of callpals executed +system.cpu0.kern.callpal::rdps 6167 3.70% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::rti 4490 2.69% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 166884 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6992 # number of protection mode switches system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1257 system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.203398 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.179777 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.338129 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1896878389500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1931924500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.304848 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1897853280000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1908310500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2839 # number of times the context was actually changed +system.cpu0.kern.swap_context 3470 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3835 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77998 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27220 39.42% 39.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 2.78% 42.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 107 0.15% 42.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 39804 57.64% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69054 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26724 48.26% 48.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 3.47% 51.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 107 0.19% 51.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26617 48.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55371 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869610475000 98.48% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533425500 0.03% 98.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 50588500 0.00% 98.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28306196500 1.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1898500685500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981778 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2463 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58134 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18218 36.94% 36.94% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.90% 40.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28877 58.55% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49317 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17831 47.44% 47.44% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.12% 52.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17534 46.65% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37587 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874537930000 98.69% 98.69% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532213500 0.03% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 134642000 0.01% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24250176000 1.28% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1899454961500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978757 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.668702 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.801851 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.607196 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.762151 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1878,36 +1863,36 @@ system.cpu1.kern.syscall::132 3 2.42% 99.19% # nu system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1407 1.97% 2.00% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.01% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64017 89.75% 91.76% # number of callpals executed -system.cpu1.kern.callpal::rdps 2632 3.69% 95.45% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.45% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.46% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 95.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3006 4.21% 99.68% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.26% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 194 0.38% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43997 85.81% 88.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2594 5.06% 93.50% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed +system.cpu1.kern.callpal::rti 3097 6.04% 99.56% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71331 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1876 # number of protection mode switches +system.cpu1.kern.callpal::total 51275 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2061 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 557 +system.cpu1.kern.mode_switch::idle 2438 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 709 system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 69 -system.cpu1.kern.mode_switch_good::kernel 0.296908 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 221 +system.cpu1.kern.mode_switch_good::kernel 0.497893 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.033479 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.251751 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 39690497500 2.09% 2.09% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 850597000 0.04% 2.14% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1857949530000 97.86% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1408 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090648 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.325977 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4822300000 0.25% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 832322500 0.04% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893789827000 99.70% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1141 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 02dc83699..856de11b9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,137 +1,124 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854310 # Number of seconds simulated -sim_ticks 1854310111000 # Number of ticks simulated -final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854307 # Number of seconds simulated +sim_ticks 1854307399500 # Number of ticks simulated +final_tick 1854307399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145253 # Simulator instruction rate (inst/s) -host_op_rate 145253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5083862253 # Simulator tick rate (ticks/s) -host_mem_usage 332668 # Number of bytes of host memory used -host_seconds 364.74 # Real time elapsed on the host -sim_insts 52980262 # Number of instructions simulated -sim_ops 52980262 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445214 # Total number of read requests seen -system.physmem.writeReqs 117421 # Total number of write requests seen -system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28493696 # Total number of bytes read from memory -system.physmem.bytesWritten 7514944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27829 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7211 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7144 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7765 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7469 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis +host_inst_rate 106006 # Simulator instruction rate (inst/s) +host_op_rate 106006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3711029376 # Simulator tick rate (ticks/s) +host_mem_usage 333480 # Number of bytes of host memory used +host_seconds 499.67 # Real time elapsed on the host +sim_insts 52968721 # Number of instructions simulated +sim_ops 52968721 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 963456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875584 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28491392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7501184 # Number of bytes written to this memory +system.physmem.bytes_written::total 7501184 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388681 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445178 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117206 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117206 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13415027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15364978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13415027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19410253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445178 # Total number of read requests seen +system.physmem.writeReqs 117206 # Total number of write requests seen +system.physmem.cpureqs 565467 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28491392 # Total number of bytes read from memory +system.physmem.bytesWritten 7501184 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28491392 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7501184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27748 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27561 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28083 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7541 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7434 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7361 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7507 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7202 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 946 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854304705000 # Total gap between requests +system.physmem.numWrRetry 2907 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854301986000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445214 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118367 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 174 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 323357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 445178 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 117206 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -141,70 +128,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests -system.physmem.totBusLat 2225790000 # Total cycles spent in databus access -system.physmem.totBankLat 5510477500 # Total cycles spent in bank access -system.physmem.avgQLat 17776.60 # Average queueing delay per request -system.physmem.avgBankLat 12378.70 # Average bank access latency per request +system.physmem.wrQLenPdf::26 881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see +system.physmem.totQLat 7499469250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15210035500 # Sum of mem lat for all requests +system.physmem.totBusLat 2225595000 # Total cycles spent in databus access +system.physmem.totBankLat 5484971250 # Total cycles spent in bank access +system.physmem.avgQLat 16848.23 # Average queueing delay per request +system.physmem.avgBankLat 12322.48 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35155.30 # Average memory access latency -system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 34170.72 # Average memory access latency +system.physmem.avgRdBW 15.36 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.36 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 417628 # Number of row buffer hits during reads -system.physmem.writeRowHits 91533 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes -system.physmem.avgGap 3295750.72 # Average gap between requests +system.physmem.avgWrQLen 14.44 # Average write queue length over time +system.physmem.readRowHits 417746 # Number of row buffer hits during reads +system.physmem.writeRowHits 91351 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes +system.physmem.avgGap 3297216.82 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265053 # Cycle average of tags in use +system.iocache.tagsinuse 1.265036 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265036 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10707310806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10707310806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10728238804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10728238804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10728238804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10728238804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 257684.607384 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 257684.607384 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 257117.766423 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 257117.766423 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 287181 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27254 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.537206 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +248,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8545305081 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8545305081 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8557236330 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8557236330 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8557236330 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8557236330 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +264,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205653.279770 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 205653.279770 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -300,35 +285,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13838840 # Number of BP lookups -system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits +system.cpu.branchPred.lookups 13852347 # Number of BP lookups +system.cpu.branchPred.condPredicted 11625691 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399405 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9419832 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5813293 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.713341 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 901451 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38715 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9926019 # DTB read hits -system.cpu.dtb.read_misses 41533 # DTB read misses -system.cpu.dtb.read_acv 530 # DTB read access violations -system.cpu.dtb.read_accesses 942239 # DTB read accesses -system.cpu.dtb.write_hits 6593693 # DTB write hits -system.cpu.dtb.write_misses 10528 # DTB write misses -system.cpu.dtb.write_acv 400 # DTB write access violations -system.cpu.dtb.write_accesses 337995 # DTB write accesses -system.cpu.dtb.data_hits 16519712 # DTB hits -system.cpu.dtb.data_misses 52061 # DTB misses -system.cpu.dtb.data_acv 930 # DTB access violations -system.cpu.dtb.data_accesses 1280234 # DTB accesses -system.cpu.itb.fetch_hits 1304342 # ITB hits -system.cpu.itb.fetch_misses 39856 # ITB misses -system.cpu.itb.fetch_acv 1022 # ITB acv -system.cpu.itb.fetch_accesses 1344198 # ITB accesses +system.cpu.dtb.read_hits 9912757 # DTB read hits +system.cpu.dtb.read_misses 41466 # DTB read misses +system.cpu.dtb.read_acv 543 # DTB read access violations +system.cpu.dtb.read_accesses 941271 # DTB read accesses +system.cpu.dtb.write_hits 6601987 # DTB write hits +system.cpu.dtb.write_misses 10361 # DTB write misses +system.cpu.dtb.write_acv 401 # DTB write access violations +system.cpu.dtb.write_accesses 337783 # DTB write accesses +system.cpu.dtb.data_hits 16514744 # DTB hits +system.cpu.dtb.data_misses 51827 # DTB misses +system.cpu.dtb.data_acv 944 # DTB access violations +system.cpu.dtb.data_accesses 1279054 # DTB accesses +system.cpu.itb.fetch_hits 1307981 # ITB hits +system.cpu.itb.fetch_misses 36519 # ITB misses +system.cpu.itb.fetch_acv 1105 # ITB acv +system.cpu.itb.fetch_accesses 1344500 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -341,269 +326,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 109629781 # number of cpu cycles simulated +system.cpu.numCycles 108624305 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28031603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70677368 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13852347 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6714744 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13246931 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1983028 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37386086 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253691 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 294769 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 735 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8549977 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266732 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80529349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221433 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67282418 83.55% 83.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 855134 1.06% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1701405 2.11% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 823363 1.02% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2750758 3.42% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561116 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645464 0.80% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009589 1.25% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4900102 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80529349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127525 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650659 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29153342 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37060255 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12110722 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963448 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1241581 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585928 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42780 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69380340 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129844 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1241581 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30275533 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13620847 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19786861 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11346001 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4258524 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65625141 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6921 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 508210 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1478954 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43830191 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79653139 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79174156 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 478983 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38170900 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5659283 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1683041 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240056 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12113189 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10427468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6890622 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1312006 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 847421 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58167835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2052016 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56809344 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 88346 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6890448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503635 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1391090 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80529349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.366907 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55889300 69.40% 69.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10803861 13.42% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5162711 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3375118 4.19% 93.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2651639 3.29% 96.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461034 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 755339 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331829 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 98518 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80529349 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91375 11.51% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373733 47.09% 58.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 328605 41.40% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38736276 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10345170 18.21% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6680665 11.76% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948997 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued -system.cpu.iq.rate 0.518227 # Inst issue rate -system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56809344 # Type of FU issued +system.cpu.iq.rate 0.522989 # Inst issue rate +system.cpu.iq.fu_busy_cnt 793713 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013972 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194336981 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66788043 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55575971 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693114 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336007 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327916 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57233562 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362209 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 600992 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1337423 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4170 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 513944 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17964 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 173464 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1241581 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9950428 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684284 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63748308 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 674797 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10427468 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6890622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1807435 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512768 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18119 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 203235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412070 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615305 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56339118 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9982368 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 470225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3526575 # number of nop insts executed -system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed -system.cpu.iew.exec_branches 8926807 # Number of branches executed -system.cpu.iew.exec_stores 6619441 # Number of stores executed -system.cpu.iew.exec_rate 0.513966 # Inst execution rate -system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27769565 # num instructions producing a value -system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value +system.cpu.iew.exec_nop 3528457 # number of nop insts executed +system.cpu.iew.exec_refs 16609952 # number of memory reference insts executed +system.cpu.iew.exec_branches 8925181 # Number of branches executed +system.cpu.iew.exec_stores 6627584 # Number of stores executed +system.cpu.iew.exec_rate 0.518660 # Inst execution rate +system.cpu.iew.wb_sent 56017641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55903887 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27773544 # num instructions producing a value +system.cpu.iew.wb_consumers 37603829 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514654 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738583 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7472187 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660926 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568042 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79287768 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.708292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.638038 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58526272 73.82% 73.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8600403 10.85% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4599837 5.80% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2533746 3.20% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516837 1.91% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 606860 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 524643 0.66% 97.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 525259 0.66% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1853911 2.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56171016 # Number of instructions committed -system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79287768 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56158922 # Number of instructions committed +system.cpu.commit.committedOps 56158922 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470138 # Number of memory references committed -system.cpu.commit.loads 9092263 # Number of loads committed -system.cpu.commit.membars 226349 # Number of memory barriers committed -system.cpu.commit.branches 8440338 # Number of branches committed +system.cpu.commit.refs 15466723 # Number of memory references committed +system.cpu.commit.loads 9090045 # Number of loads committed +system.cpu.commit.membars 226335 # Number of memory barriers committed +system.cpu.commit.branches 8439344 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52020652 # Number of committed integer instructions. -system.cpu.commit.function_calls 740552 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52009184 # Number of committed integer instructions. +system.cpu.commit.function_calls 740395 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1853911 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140865752 # The number of ROB reads -system.cpu.rob.rob_writes 128516921 # The number of ROB writes -system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52980262 # Number of Instructions Simulated -system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated -system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads -system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73880365 # number of integer regfile reads -system.cpu.int_regfile_writes 40316413 # number of integer regfile writes -system.cpu.fp_regfile_reads 166011 # number of floating regfile reads -system.cpu.fp_regfile_writes 167446 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads -system.cpu.misc_regfile_writes 938994 # number of misc regfile writes +system.cpu.rob.rob_reads 140815408 # The number of ROB reads +system.cpu.rob.rob_writes 128505533 # The number of ROB writes +system.cpu.timesIdled 1178112 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28094956 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599984053 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52968721 # Number of Instructions Simulated +system.cpu.committedOps 52968721 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52968721 # Number of Instructions Simulated +system.cpu.cpi 2.050725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.050725 # CPI: Total CPI of All Threads +system.cpu.ipc 0.487632 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.487632 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73881531 # number of integer regfile reads +system.cpu.int_regfile_writes 40312822 # number of integer regfile writes +system.cpu.fp_regfile_reads 166061 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987886 # number of misc regfile reads +system.cpu.misc_regfile_writes 938918 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -635,189 +620,197 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1008798 # number of replacements -system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use -system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7480627 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7480627 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7480627 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7480627 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7480627 # number of overall hits -system.cpu.icache.overall_hits::total 7480627 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065018 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065018 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065018 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065018 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065018 # number of overall misses -system.cpu.icache.overall_misses::total 1065018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14700112992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14700112992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14700112992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14700112992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14700112992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8545645 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8545645 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8545645 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8545645 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8545645 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8545645 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124627 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124627 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124627 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124627 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13802.689712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13802.689712 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5838 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 237 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.758621 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 237 # average number of cycles each access was blocked +system.cpu.icache.replacements 1008795 # number of replacements +system.cpu.icache.tagsinuse 510.288576 # Cycle average of tags in use +system.cpu.icache.total_refs 7484836 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1009303 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.415846 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.288576 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7484837 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7484837 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7484837 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7484837 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7484837 # number of overall hits +system.cpu.icache.overall_hits::total 7484837 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1065140 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1065140 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1065140 # number of overall misses +system.cpu.icache.overall_misses::total 1065140 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14678664495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14678664495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14678664495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14678664495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14678664495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14678664495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8549977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8549977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8549977 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8549977 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8549977 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8549977 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13780.971980 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13780.971980 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13780.971980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13780.971980 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7122 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1606 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 164 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.426829 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 803 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55491 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55491 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55491 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55491 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55491 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55491 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009527 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009527 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009527 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009527 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009527 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009527 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12048771993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12048771993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12048771993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12048771993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12048771993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12048771993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118134 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118134 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118134 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11935.066613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11935.066613 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55619 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 55619 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 55619 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 55619 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 55619 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 55619 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1009521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1009521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1009521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1009521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1009521 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12035617996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12035617996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12035617996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12035617996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12035617996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12035617996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118073 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.118073 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.118073 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.107609 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.107609 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997386 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 994342 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827132 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1821474 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840875 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840875 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185593 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185593 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 994342 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167652 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167652 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57368.725227 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.789861 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34356.302756 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15055 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273775 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288830 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15055 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389170 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15055 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389170 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404225 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851622750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8594985001 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9446607751 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 547534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 547534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6209572959 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6209572959 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14804557960 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15656180710 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14804557960 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15656180710 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333813500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333813500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882743500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882743500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216557000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216557000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248784 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136896 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167687 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167687 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56567.436068 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31394.338420 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32706.463148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14039.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14039.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53811.455947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53811.455947 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -899,161 +900,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1401332 # number of replacements -system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use -system.cpu.dcache.total_refs 11818848 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401844 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.430930 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1400597 # number of replacements +system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use +system.cpu.dcache.total_refs 11804639 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401109 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.425211 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7212145 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7212145 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204906 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204906 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186063 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186063 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11417051 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11417051 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11417051 # number of overall hits -system.cpu.dcache.overall_hits::total 11417051 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802577 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802577 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1942748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1942748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22749 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22749 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3745325 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745325 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3745325 # number of overall misses -system.cpu.dcache.overall_misses::total 3745325 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 34332308500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 34332308500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 65131487898 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 65131487898 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306015000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306015000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99463796398 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99463796398 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99463796398 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99463796398 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9014722 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9014722 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147654 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147654 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208812 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208812 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15162376 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15162376 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15162376 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15162376 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199959 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.199959 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316015 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316015 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108945 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108945 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247014 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26556.786500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26556.786500 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2193487 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 506 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95928 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.865972 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.285714 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 7199170 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7199170 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203355 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186385 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186385 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11402525 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11402525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11402525 # number of overall hits +system.cpu.dcache.overall_hits::total 11402525 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1802469 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1802469 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943114 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943114 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22653 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22653 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3745583 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3745583 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3745583 # number of overall misses +system.cpu.dcache.overall_misses::total 3745583 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33840497500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33840497500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64776324525 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64776324525 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306197000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 306197000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98616822025 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98616822025 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98616822025 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98616822025 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9001639 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9001639 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146469 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146469 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15148108 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15148108 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15148108 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15148108 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200238 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200238 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316135 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108368 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108368 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247264 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247264 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247264 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247264 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18774.524000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18774.524000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33336.348009 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33336.348009 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13516.841037 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13516.841037 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19125 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19125 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26328.831059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26328.831059 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2181836 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95774 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.781089 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks -system.cpu.dcache.writebacks::total 840875 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840320 # number of writebacks +system.cpu.dcache.writebacks::total 840320 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718906 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 718906 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642971 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642971 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5109 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5109 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2361877 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2361877 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2361877 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2361877 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300143 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300143 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17544 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17544 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383706 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383706 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383706 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383706 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21325000500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21325000500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9835893766 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9835893766 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200292500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200292500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 68500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 68500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31160894266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31160894266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31160894266 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31160894266 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423890500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423890500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997911498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997911498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421801998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421801998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120374 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120374 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048832 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048832 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091345 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091345 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19680.443592 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19680.443592 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32770.691857 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32770.691857 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11416.581167 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11416.581167 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17125 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17125 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1062,28 +1063,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818335798500 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63864000 0.00% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 549180000 0.03% 98.09% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35357724000 1.91% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854306566500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1122,7 +1123,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1131,7 +1132,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191985 # number of callpals executed +system.cpu.kern.callpal::total 191959 # number of callpals executed system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -1142,9 +1143,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326552 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29457551500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2704315000 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822144692000 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 014619ced..1f0f241e7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,154 +1,141 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.841686 # Number of seconds simulated -sim_ticks 1841685645500 # Number of ticks simulated -final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1841685557500 # Number of ticks simulated +final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 300759 # Simulator instruction rate (inst/s) -host_op_rate 300759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7981184825 # Simulator tick rate (ticks/s) -host_mem_usage 313952 # Number of bytes of host memory used -host_seconds 230.75 # Real time elapsed on the host -sim_insts 69401254 # Number of instructions simulated -sim_ops 69401254 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19389440 # Number of bytes read from this memory +host_inst_rate 244491 # Simulator instruction rate (inst/s) +host_op_rate 244491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6478446279 # Simulator tick rate (ticks/s) +host_mem_usage 315916 # Number of bytes of host memory used +host_seconds 284.28 # Real time elapsed on the host +sim_insts 69503534 # Number of instructions simulated +sim_ops 69503534 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19348096 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2812736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 293952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2665600 # Number of bytes read from this memory -system.physmem.bytes_read::total 28438656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 293952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7476160 # Number of bytes written to this memory -system.physmem.bytes_written::total 7476160 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302960 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 150080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2814720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2705088 # Number of bytes read from this memory +system.physmem.bytes_read::total 28439424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 474240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7476992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7476992 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302314 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4593 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41650 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444354 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116815 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116815 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10528094 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 2345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 43980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444366 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116828 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116828 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 257503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10505646 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1527262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1447370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15441645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81595 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4059412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4059412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4059412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10528094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1528339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 160132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1468811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15442063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 257503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 160132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4059864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4059864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4059864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 257503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10505646 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1527262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1447370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19501057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109303 # Total number of read requests seen -system.physmem.writeReqs 45531 # Total number of write requests seen -system.physmem.cpureqs 156037 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6995392 # Total number of bytes read from memory -system.physmem.bytesWritten 2913984 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6995392 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2913984 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 81491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1528339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 160132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1468811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109963 # Total number of read requests seen +system.physmem.writeReqs 45515 # Total number of write requests seen +system.physmem.cpureqs 155620 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7037632 # Total number of bytes read from memory +system.physmem.bytesWritten 2912960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2912960 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6492 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6828 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6781 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2987 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2793 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2608 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2755 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2826 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2868 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2766 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 40 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6897 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6833 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7049 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6845 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2979 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2595 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2752 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3044 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2867 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2811 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1002 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840673558000 # Total gap between requests +system.physmem.numWrRetry 102 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840673470000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109303 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 46533 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 41 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 80133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.readPktSize::6 109963 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 45515 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 80954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 319 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,240 +148,242 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1965 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2420387927 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4417690427 # Sum of mem lat for all requests -system.physmem.totBusLat 546485000 # Total cycles spent in databus access -system.physmem.totBankLat 1450817500 # Total cycles spent in bank access -system.physmem.avgQLat 22145.05 # Average queueing delay per request -system.physmem.avgBankLat 13274.08 # Average bank access latency per request +system.physmem.wrQLenPdf::18 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.totQLat 2376401250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4386835000 # Sum of mem lat for all requests +system.physmem.totBusLat 549785000 # Total cycles spent in databus access +system.physmem.totBankLat 1460648750 # Total cycles spent in bank access +system.physmem.avgQLat 21612.10 # Average queueing delay per request +system.physmem.avgBankLat 13283.82 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40419.14 # Average memory access latency -system.physmem.avgRdBW 3.80 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 39895.91 # Average memory access latency +system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33865.108789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44582.685919 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -505,12 +494,12 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255467 # Cycle average of tags in use +system.iocache.tagsinuse 1.255479 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693876367000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255467 # Average occupied blocks per requestor +system.iocache.warmup_cycle 1693875860000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255479 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.078467 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.078467 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses @@ -521,14 +510,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 10497998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 10497998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4320435904 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4320435904 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4330933902 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4330933902 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4330933902 # 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number of WriteReq accesses(hits+misses) @@ -545,19 +534,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 60682.069364 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 60682.069364 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103976.605314 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 103976.605314 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 103797.097711 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 103797.097711 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 116360 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103619.293993 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 103619.293993 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 116041 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11123 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11151 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.461207 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.406331 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -571,14 +560,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 16837 system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6909249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6909249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3447972406 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3447972406 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3454881655 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3454881655 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3454881655 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3454881655 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433126461 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3433126461 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3438715710 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3438715710 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3438715710 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3438715710 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses @@ -587,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 100134.043478 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 100134.043478 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205628.125358 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 205628.125358 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204742.751729 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204742.751729 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,22 +601,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4870222 # DTB read hits -system.cpu0.dtb.read_misses 6004 # DTB read misses -system.cpu0.dtb.read_acv 119 # DTB read access violations -system.cpu0.dtb.read_accesses 427226 # DTB read accesses -system.cpu0.dtb.write_hits 3495920 # DTB write hits -system.cpu0.dtb.write_misses 662 # DTB write misses +system.cpu0.dtb.read_hits 4874109 # DTB read hits +system.cpu0.dtb.read_misses 5989 # DTB read misses +system.cpu0.dtb.read_acv 118 # DTB read access violations +system.cpu0.dtb.read_accesses 427176 # DTB read accesses +system.cpu0.dtb.write_hits 3500725 # DTB write hits +system.cpu0.dtb.write_misses 661 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162893 # DTB write accesses -system.cpu0.dtb.data_hits 8366142 # DTB hits -system.cpu0.dtb.data_misses 6666 # DTB misses -system.cpu0.dtb.data_acv 201 # DTB access violations -system.cpu0.dtb.data_accesses 590119 # DTB accesses -system.cpu0.itb.fetch_hits 2742252 # ITB hits -system.cpu0.itb.fetch_misses 2999 # ITB misses -system.cpu0.itb.fetch_acv 100 # ITB acv -system.cpu0.itb.fetch_accesses 2745251 # ITB accesses +system.cpu0.dtb.write_accesses 162885 # DTB write accesses +system.cpu0.dtb.data_hits 8374834 # DTB hits +system.cpu0.dtb.data_misses 6650 # DTB misses +system.cpu0.dtb.data_acv 200 # DTB access violations +system.cpu0.dtb.data_accesses 590061 # DTB accesses +system.cpu0.itb.fetch_hits 2743092 # ITB hits +system.cpu0.itb.fetch_misses 2995 # ITB misses +system.cpu0.itb.fetch_acv 98 # ITB acv +system.cpu0.itb.fetch_accesses 2746087 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -640,51 +629,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928524557 # number of cpu cycles simulated +system.cpu0.numCycles 928539725 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32346409 # Number of instructions committed -system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30227600 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses -system.cpu0.num_func_calls 807221 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30227600 # number of integer instructions -system.cpu0.num_fp_insts 167714 # number of float instructions -system.cpu0.num_int_register_reads 42120330 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22107857 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written -system.cpu0.num_mem_refs 8395829 # number of memory refs -system.cpu0.num_load_insts 4891258 # Number of load instructions -system.cpu0.num_store_insts 3504571 # Number of store instructions -system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles -system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles -system.cpu0.not_idle_fraction -228.514484 # Percentage of non-idle cycles -system.cpu0.idle_fraction 229.514484 # Percentage of idle cycles +system.cpu0.committedInsts 32518253 # Number of instructions committed +system.cpu0.committedOps 32518253 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30397519 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 168035 # Number of float alu accesses +system.cpu0.num_func_calls 808172 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4307008 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30397519 # number of integer instructions +system.cpu0.num_fp_insts 168035 # number of float instructions +system.cpu0.num_int_register_reads 42396693 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22221610 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 86774 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88345 # number of times the floating registers were written +system.cpu0.num_mem_refs 8404498 # number of memory refs +system.cpu0.num_load_insts 4895120 # Number of load instructions +system.cpu0.num_store_insts 3509378 # Number of store instructions +system.cpu0.num_idle_cycles 214025441196.436279 # Number of idle cycles +system.cpu0.num_busy_cycles -213096901471.436279 # Number of busy cycles +system.cpu0.not_idle_fraction -229.496806 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.496806 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211363 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74796 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211357 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105684 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182561 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73429 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818585888500 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39023500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22696621500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818586321500 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38755000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 363405500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22696319000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841684801000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815831 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694792 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -720,10 +709,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175304 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -732,21 +721,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192218 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.callpal::total 192213 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29741940500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2557110500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4178 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::total 0.391349 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29734416500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2561211500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809389169500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -778,356 +767,372 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 952688 # number of replacements -system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use -system.cpu0.icache.total_refs 41854962 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953199 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 43.909994 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 175.771257 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.155505 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.343303 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7734855 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2288179 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41854962 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31831928 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7734855 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2288179 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41854962 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31831928 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7734855 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2288179 # number of overall hits -system.cpu0.icache.overall_hits::total 41854962 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 521348 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 128929 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 320072 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970349 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 521348 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 128929 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 320072 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970349 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 521348 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 128929 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 320072 # number of overall misses -system.cpu0.icache.overall_misses::total 970349 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813964500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4473861486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6287825986 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1813964500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4473861486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6287825986 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1813964500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4473861486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6287825986 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32353276 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863784 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608251 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42825311 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32353276 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7863784 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2608251 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42825311 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32353276 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7863784 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2608251 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42825311 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016114 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016395 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122715 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122715 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122715 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.672168 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.963380 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6479.963380 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6479.963380 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5140 # number of cycles access was blocked +system.cpu0.icache.replacements 953667 # number of replacements +system.cpu0.icache.tagsinuse 511.197543 # Cycle average of tags in use +system.cpu0.icache.total_refs 42031546 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 954178 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 44.050005 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10246755000 # 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number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32525103 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7872875 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2604896 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43002874 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016051 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016394 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122925 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022588 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016051 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016394 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122925 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6475.089755 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4631 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 184 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.235294 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.168478 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # 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number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285653 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 285653 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 476174 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 476174 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1502 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1502 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 761827 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 761827 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 761827 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 761827 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 104504 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 262049 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366553 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48063 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85208 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133271 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85019 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133082 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5492 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7685 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 151743 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 347122 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263315500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465635120 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9728950620 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263315500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465635120 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9728950620 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342020000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760662000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053019 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045421 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021663 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102152 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037849 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033085 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.267943 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.796955 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.966169 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.481590 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5558 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7751 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 152567 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 347068 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 499635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 152567 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 347068 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 499635 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1975725000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4306208500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6281933500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1299140000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2144349624 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3443489624 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24977000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70824000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95801000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3274865000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6450558124 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9725423124 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3274865000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6450558124 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9725423124 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287731500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 345150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 632882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357324500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 421745500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 779070000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645056000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 766896000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411952000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086890 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088411 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041068 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.052979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045452 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021633 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102047 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.100173 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038166 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033138 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033138 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18905.735666 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.836989 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17137.858645 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27029.939871 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25222.004775 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25874.946454 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11389.420885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12742.713206 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12359.824539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1142,22 +1147,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1220324 # DTB read hits -system.cpu1.dtb.read_misses 1556 # DTB read misses -system.cpu1.dtb.read_acv 46 # DTB read access violations -system.cpu1.dtb.read_accesses 144016 # DTB read accesses -system.cpu1.dtb.write_hits 928239 # DTB write hits -system.cpu1.dtb.write_misses 207 # DTB write misses +system.cpu1.dtb.read_hits 1221793 # DTB read hits +system.cpu1.dtb.read_misses 1550 # DTB read misses +system.cpu1.dtb.read_acv 45 # DTB read access violations +system.cpu1.dtb.read_accesses 143987 # DTB read accesses +system.cpu1.dtb.write_hits 928954 # DTB write hits +system.cpu1.dtb.write_misses 206 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 60107 # DTB write accesses -system.cpu1.dtb.data_hits 2148563 # DTB hits -system.cpu1.dtb.data_misses 1763 # DTB misses -system.cpu1.dtb.data_acv 70 # DTB access violations -system.cpu1.dtb.data_accesses 204123 # DTB accesses -system.cpu1.itb.fetch_hits 875123 # ITB hits -system.cpu1.itb.fetch_misses 774 # ITB misses +system.cpu1.dtb.write_accesses 60098 # DTB write accesses +system.cpu1.dtb.data_hits 2150747 # DTB hits +system.cpu1.dtb.data_misses 1756 # DTB misses +system.cpu1.dtb.data_acv 69 # DTB access violations +system.cpu1.dtb.data_accesses 204085 # DTB accesses +system.cpu1.itb.fetch_hits 875028 # ITB hits +system.cpu1.itb.fetch_misses 772 # ITB misses system.cpu1.itb.fetch_acv 46 # ITB acv -system.cpu1.itb.fetch_accesses 875897 # ITB accesses +system.cpu1.itb.fetch_accesses 875800 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1170,28 +1175,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953544041 # number of cpu cycles simulated +system.cpu1.numCycles 953543873 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7861950 # Number of instructions committed -system.cpu1.committedOps 7861950 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7314131 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses -system.cpu1.num_func_calls 212083 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7314131 # number of integer instructions -system.cpu1.num_fp_insts 45433 # number of float instructions -system.cpu1.num_int_register_reads 10166174 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5323213 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written -system.cpu1.num_mem_refs 2156447 # number of memory refs -system.cpu1.num_load_insts 1225739 # Number of load instructions -system.cpu1.num_store_insts 930708 # Number of store instructions -system.cpu1.num_idle_cycles 195910527.476772 # Number of idle cycles -system.cpu1.num_busy_cycles 757633513.523228 # Number of busy cycles -system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles +system.cpu1.committedInsts 7871049 # Number of instructions committed +system.cpu1.committedOps 7871049 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7322486 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45486 # Number of float alu accesses +system.cpu1.num_func_calls 212361 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 961543 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7322486 # number of integer instructions +system.cpu1.num_fp_insts 45486 # number of float instructions +system.cpu1.num_int_register_reads 10177666 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5328829 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24537 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24857 # number of times the floating registers were written +system.cpu1.num_mem_refs 2158619 # number of memory refs +system.cpu1.num_load_insts 1227197 # Number of load instructions +system.cpu1.num_store_insts 931422 # Number of store instructions +system.cpu1.num_idle_cycles -1678612352.135852 # Number of idle cycles +system.cpu1.num_busy_cycles 2632156225.135852 # Number of busy cycles +system.cpu1.not_idle_fraction 2.760393 # Percentage of non-idle cycles +system.cpu1.idle_fraction -1.760393 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1209,35 +1214,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8412639 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129283 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5762097 # Number of BTB hits +system.cpu2.branchPred.lookups 8388883 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7698653 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 129790 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6809522 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5746337 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.529003 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 288281 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.386790 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 285994 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15305 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3230838 # DTB read hits -system.cpu2.dtb.read_misses 11458 # DTB read misses -system.cpu2.dtb.read_acv 112 # DTB read access violations -system.cpu2.dtb.read_accesses 217040 # DTB read accesses -system.cpu2.dtb.write_hits 2001661 # DTB write hits -system.cpu2.dtb.write_misses 2605 # DTB write misses -system.cpu2.dtb.write_acv 143 # DTB write access violations -system.cpu2.dtb.write_accesses 81606 # DTB write accesses -system.cpu2.dtb.data_hits 5232499 # DTB hits -system.cpu2.dtb.data_misses 14063 # DTB misses -system.cpu2.dtb.data_acv 255 # DTB access violations -system.cpu2.dtb.data_accesses 298646 # DTB accesses -system.cpu2.itb.fetch_hits 371716 # ITB hits -system.cpu2.itb.fetch_misses 5691 # ITB misses -system.cpu2.itb.fetch_acv 245 # ITB acv -system.cpu2.itb.fetch_accesses 377407 # ITB accesses +system.cpu2.dtb.read_hits 3222753 # DTB read hits +system.cpu2.dtb.read_misses 11767 # DTB read misses +system.cpu2.dtb.read_acv 114 # DTB read access violations +system.cpu2.dtb.read_accesses 216394 # DTB read accesses +system.cpu2.dtb.write_hits 1997746 # DTB write hits +system.cpu2.dtb.write_misses 2597 # DTB write misses +system.cpu2.dtb.write_acv 133 # DTB write access violations +system.cpu2.dtb.write_accesses 81219 # DTB write accesses +system.cpu2.dtb.data_hits 5220499 # DTB hits +system.cpu2.dtb.data_misses 14364 # DTB misses +system.cpu2.dtb.data_acv 247 # DTB access violations +system.cpu2.dtb.data_accesses 297613 # DTB accesses +system.cpu2.itb.fetch_hits 371919 # ITB hits +system.cpu2.itb.fetch_misses 5650 # ITB misses +system.cpu2.itb.fetch_acv 270 # ITB acv +system.cpu2.itb.fetch_accesses 377569 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1250,141 +1255,141 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30535693 # number of cpu cycles simulated +system.cpu2.numCycles 30487191 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8533990 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34964700 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8412639 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8133501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 621341 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9684407 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2608255 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90277 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26910349 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.299303 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8524791 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34873991 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8388883 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6032331 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8111828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 622665 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9676306 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1940 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 62420 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 80561 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2604903 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90729 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26874751 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.297649 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.309099 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18776848 69.78% 69.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4254202 15.81% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1630674 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18762923 69.82% 69.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 273694 1.02% 70.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 440641 1.64% 72.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4237897 15.77% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 736346 2.74% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 166761 0.62% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 196079 0.73% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433619 1.61% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1626791 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26910349 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.145044 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8661368 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9779389 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7537152 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 392385 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 168928 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12969 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34563096 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40760 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 392385 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9017327 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2819479 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5795758 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7393745 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1245780 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33400490 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 410986 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22419818 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41624592 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41459015 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20587002 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1832816 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3692921 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2097986 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 374319 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30873003 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30415505 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2194500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1105040 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26910349 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565605 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26874751 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.275161 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.143890 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8657787 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9768162 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7515953 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293497 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 393434 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168963 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12933 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34472576 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40526 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 393434 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9012684 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2836795 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5769605 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7372565 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1243759 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33316352 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2373 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 234595 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 408588 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22366948 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41510379 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41345500 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 164879 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20534540 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1832408 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 504738 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 60071 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3686935 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3385510 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2088081 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 373278 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 254690 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30792200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 629969 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30337437 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 32004 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2187587 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1093629 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 444846 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26874751 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.128845 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.565283 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15319532 56.93% 56.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3107477 11.55% 68.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1555924 5.78% 74.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5075651 18.86% 93.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 913363 3.39% 96.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 492005 1.83% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286833 1.07% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 17804 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15311841 56.97% 56.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3103500 11.55% 68.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1551808 5.77% 74.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5059769 18.83% 93.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 912287 3.39% 96.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 489619 1.82% 98.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286015 1.06% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141615 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18297 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26910349 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26874751 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113310 45.00% 58.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34821 13.89% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112497 44.88% 58.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 103352 41.23% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24705611 81.23% 81.24% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24640378 81.22% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20252 0.07% 81.30% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1222 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8482 0.03% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued @@ -1406,114 +1411,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3362290 11.05% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2024696 6.66% 99.05% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3354206 11.06% 92.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2020424 6.66% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 290023 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30415505 # Type of FU issued -system.cpu2.iq.rate 0.996064 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87793654 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33586184 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 30009842 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30540947 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30337437 # Type of FU issued +system.cpu2.iq.rate 0.995088 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 250670 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008263 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87595744 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33498169 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29934734 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 236555 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 115613 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 112132 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30462481 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123178 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 189585 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 420180 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 166079 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 417411 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 964 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4105 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 161809 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4731 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 22958 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 392385 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32790350 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224390 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2097986 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 129831 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196511 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30250749 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3250588 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 164756 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 393434 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2055085 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 212014 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32707784 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224122 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3385510 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2088081 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 559310 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 150319 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2295 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4105 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 66873 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 130024 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196897 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30173481 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3242841 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 163956 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1286376 # number of nop insts executed -system.cpu2.iew.exec_refs 5259365 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6817857 # Number of branches executed -system.cpu2.iew.exec_stores 2008777 # Number of stores executed -system.cpu2.iew.exec_rate 0.990668 # Inst execution rate -system.cpu2.iew.wb_sent 30155480 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30122471 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17393530 # num instructions producing a value -system.cpu2.iew.wb_consumers 20640200 # num instructions consuming a value +system.cpu2.iew.exec_nop 1285615 # number of nop insts executed +system.cpu2.iew.exec_refs 5247672 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6797242 # Number of branches executed +system.cpu2.iew.exec_stores 2004831 # Number of stores executed +system.cpu2.iew.exec_rate 0.989710 # Inst execution rate +system.cpu2.iew.wb_sent 30079535 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30046866 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17352028 # num instructions producing a value +system.cpu2.iew.wb_consumers 20589621 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.986468 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.985557 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.842756 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182289 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26517964 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.145283 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.851177 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2372790 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 185123 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182681 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26481317 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.143824 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.850690 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16375646 61.75% 61.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2329504 8.78% 70.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1218959 4.60% 75.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4807373 18.13% 93.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186921 0.70% 95.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 179411 0.68% 96.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 736843 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16366667 61.80% 61.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2324205 8.78% 70.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1216165 4.59% 75.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4790733 18.09% 93.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 501931 1.90% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186373 0.70% 95.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 179761 0.68% 96.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180772 0.68% 97.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 734710 2.77% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26517964 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30370564 # Number of instructions committed -system.cpu2.commit.committedOps 30370564 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26481317 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30289973 # Number of instructions committed +system.cpu2.commit.committedOps 30289973 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4905590 # Number of memory references committed -system.cpu2.commit.loads 2973683 # Number of loads committed -system.cpu2.commit.membars 65235 # Number of memory barriers committed -system.cpu2.commit.branches 6667985 # Number of branches committed -system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28908366 # Number of committed integer instructions. -system.cpu2.commit.function_calls 232233 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 736843 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4894371 # Number of memory references committed +system.cpu2.commit.loads 2968099 # Number of loads committed +system.cpu2.commit.membars 65019 # Number of memory barriers committed +system.cpu2.commit.branches 6647353 # Number of branches committed +system.cpu2.commit.fp_insts 110870 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28830509 # Number of committed integer instructions. +system.cpu2.commit.function_calls 231619 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 734710 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58454819 # The number of ROB reads -system.cpu2.rob.rob_writes 65882909 # The number of ROB writes -system.cpu2.timesIdled 242872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3625344 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29192895 # Number of Instructions Simulated -system.cpu2.committedOps 29192895 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29192895 # Number of Instructions Simulated -system.cpu2.cpi 1.045997 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.045997 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39779596 # number of integer regfile reads -system.cpu2.int_regfile_writes 21289109 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads -system.cpu2.misc_regfile_writes 260558 # number of misc regfile writes +system.cpu2.rob.rob_reads 58337288 # The number of ROB reads +system.cpu2.rob.rob_writes 65718838 # The number of ROB writes +system.cpu2.timesIdled 243105 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3612440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745337726 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29114232 # Number of Instructions Simulated +system.cpu2.committedOps 29114232 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29114232 # Number of Instructions Simulated +system.cpu2.cpi 1.047158 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.047158 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.954966 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.954966 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39679960 # number of integer regfile reads +system.cpu2.int_regfile_writes 21237504 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68414 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68689 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4591435 # number of misc regfile reads +system.cpu2.misc_regfile_writes 259923 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |