diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
| commit | 26ca8b87470912d5e593a21fc968dd2ddf0e20b2 (patch) | |
| tree | bf97df45e65f08107321f58d83688b08bbd3f675 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (diff) | |
| download | gem5-26ca8b87470912d5e593a21fc968dd2ddf0e20b2.tar.xz | |
Regressions: Update stats due to O3 CPU changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
6 files changed, 1632 insertions, 1668 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 94bfc8925..46790add4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,14 +11,14 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -104,6 +105,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -135,6 +137,7 @@ tracer=system.cpu0.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -540,6 +543,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -571,6 +575,7 @@ tracer=system.cpu1.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -932,7 +937,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -952,7 +957,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1052,7 +1057,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1081,7 +1085,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -1122,7 +1126,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -1204,7 +1207,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1221,7 +1223,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1238,7 +1239,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1255,7 +1255,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1272,7 +1271,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1289,7 +1287,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1306,7 +1303,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1323,7 +1319,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1340,7 +1335,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1357,7 +1351,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1374,7 +1367,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1391,7 +1383,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1408,7 +1399,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1425,7 +1415,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1442,7 +1431,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1459,7 +1447,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1476,7 +1463,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1493,7 +1479,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1510,7 +1495,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1526,7 +1510,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -1591,7 +1574,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1602,7 +1584,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 35f0311de..fd99ca0d0 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 06:11:48 -gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Feb 3 2012 13:46:22 +gem5 started Feb 3 2012 13:46:34 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 106949500 -Exiting @ tick 1897465263500 because m5_exit instruction encountered +Exiting @ tick 1897464893500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index d2e784a3f..78411ca4d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,144 +1,144 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.897465 # Number of seconds simulated -sim_ticks 1897465263500 # Number of ticks simulated -final_tick 1897465263500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1897464893500 # Number of ticks simulated +final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131690 # Simulator instruction rate (inst/s) -host_tick_rate 4451680142 # Simulator tick rate (ticks/s) -host_mem_usage 298548 # Number of bytes of host memory used -host_seconds 426.24 # Real time elapsed on the host -sim_insts 56130966 # Number of instructions simulated -system.physmem.bytes_read 30408320 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1097728 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10468544 # Number of bytes written to this memory -system.physmem.num_reads 475130 # Number of read requests responded to by this memory -system.physmem.num_writes 163571 # Number of write requests responded to by this memory +host_inst_rate 100310 # Simulator instruction rate (inst/s) +host_tick_rate 3391719918 # Simulator tick rate (ticks/s) +host_mem_usage 326488 # Number of bytes of host memory used +host_seconds 559.44 # Real time elapsed on the host +sim_insts 56117221 # Number of instructions simulated +system.physmem.bytes_read 30408512 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10470144 # Number of bytes written to this memory +system.physmem.num_reads 475133 # Number of read requests responded to by this memory +system.physmem.num_writes 163596 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16025758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 578523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5517120 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21542879 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397795 # number of replacements -system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use -system.l2c.total_refs 2482671 # Total number of references to valid blocks. -system.l2c.sampled_refs 433561 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.726232 # Average number of references to valid blocks. +system.physmem.bw_read 16025863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 579367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5517965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21543827 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 397850 # number of replacements +system.l2c.tagsinuse 35109.782430 # Cycle average of tags in use +system.l2c.total_refs 2482376 # Total number of references to valid blocks. +system.l2c.sampled_refs 433566 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.725486 # Average number of references to valid blocks. system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12003.983788 # Average occupied blocks per context -system.l2c.occ_blocks::1 238.395777 # Average occupied blocks per context -system.l2c.occ_blocks::2 22874.505342 # Average occupied blocks per context -system.l2c.occ_percent::0 0.183166 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.003638 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.349037 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1719678 # number of ReadReq hits -system.l2c.ReadReq_hits::1 147350 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1867028 # number of ReadReq hits -system.l2c.Writeback_hits::0 826540 # number of Writeback hits -system.l2c.Writeback_hits::total 826540 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 46 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 28 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 28 # number of SCUpgradeReq hits +system.l2c.occ_blocks::0 12005.589305 # Average occupied blocks per context +system.l2c.occ_blocks::1 237.479904 # Average occupied blocks per context +system.l2c.occ_blocks::2 22866.713220 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183191 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.003624 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.348918 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1720206 # number of ReadReq hits +system.l2c.ReadReq_hits::1 147304 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1867510 # number of ReadReq hits +system.l2c.Writeback_hits::0 827202 # number of Writeback hits +system.l2c.Writeback_hits::total 827202 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 175 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 45 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 29 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 168225 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 11091 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179316 # number of ReadExReq hits -system.l2c.demand_hits::0 1887903 # number of demand (read+write) hits -system.l2c.demand_hits::1 158441 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 168180 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 11095 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits +system.l2c.demand_hits::0 1888386 # number of demand (read+write) hits +system.l2c.demand_hits::1 158399 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2046344 # number of demand (read+write) hits -system.l2c.overall_hits::0 1887903 # number of overall hits -system.l2c.overall_hits::1 158441 # number of overall hits +system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits +system.l2c.overall_hits::0 1888386 # number of overall hits +system.l2c.overall_hits::1 158399 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2046344 # number of overall hits -system.l2c.ReadReq_misses::0 305537 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4057 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309594 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2453 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 560 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3013 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 48 # number of SCUpgradeReq misses +system.l2c.overall_hits::total 2046785 # number of overall hits +system.l2c.ReadReq_misses::0 305580 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4046 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309626 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2447 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 562 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 45 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::1 84 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 132 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 113925 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 10735 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124660 # number of ReadExReq misses -system.l2c.demand_misses::0 419462 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::total 129 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 113888 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 10746 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124634 # number of ReadExReq misses +system.l2c.demand_misses::0 419468 # number of demand (read+write) misses system.l2c.demand_misses::1 14792 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 434254 # number of demand (read+write) misses -system.l2c.overall_misses::0 419462 # number of overall misses +system.l2c.demand_misses::total 434260 # number of demand (read+write) misses +system.l2c.overall_misses::0 419468 # number of overall misses system.l2c.overall_misses::1 14792 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 434254 # number of overall misses -system.l2c.ReadReq_miss_latency 16116451000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 3978500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 680500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6538718500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22655169500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22655169500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2025215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 151407 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2176622 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 826540 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 826540 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2625 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3231 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 76 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 112 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 282150 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21826 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 303976 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2307365 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 173233 # number of demand (read+write) accesses +system.l2c.overall_misses::total 434260 # number of overall misses +system.l2c.ReadReq_miss_latency 16117985000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 4084000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 629500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6538201500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22656186500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22656186500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2025786 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 151350 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2177136 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 827202 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 827202 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2622 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 607 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3229 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 74 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 111 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 185 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 282068 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21841 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 303909 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2307854 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 173191 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2480598 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2307365 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 173233 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2481045 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2307854 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 173191 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2480598 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.150866 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.026795 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.934476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.924092 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.631579 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.750000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.403775 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.491845 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.181793 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.085388 # miss rate for demand accesses +system.l2c.overall_accesses::total 2481045 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.150845 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.026733 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.933257 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.925865 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.608108 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.756757 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.403761 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.492010 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.181757 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.085409 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.181793 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.085388 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.181757 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.085409 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52747.951967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3972504.560020 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52745.549447 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3983683.885319 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 1621.891561 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7104.464286 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 1668.982427 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7266.903915 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 14177.083333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 8101.190476 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 13988.888889 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 7494.047619 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 57394.939653 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 609102.794597 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57409.046607 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 608431.183696 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 54010.064082 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1531582.578421 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 54011.716031 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1531651.331801 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 54010.064082 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1531582.578421 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 54011.716031 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1531651.331801 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -149,56 +149,56 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 122051 # number of writebacks +system.l2c.writebacks 122076 # number of writebacks system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 309576 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3013 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 132 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 124660 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 434236 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 434236 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 309608 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3009 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 129 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124634 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434242 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434242 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12393243000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 120589000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 5280000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5022395000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17415638000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17415638000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838122500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1421433998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2259556498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.152861 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.044661 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12394422500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 120428500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 5161500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5022578000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17417000500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17417000500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838122000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1420361498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2258483498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.152834 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.045643 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.147810 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.971947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.147597 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.957166 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.736842 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.178571 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.743243 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.162162 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.441822 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 5.711537 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.441858 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 5.706424 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.188196 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 2.506659 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.188158 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 2.507301 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.188196 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 2.506659 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.188158 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 2.507301 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40032.957981 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.900763 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40288.745387 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40032.629971 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.765038 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40011.627907 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40298.618355 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40108.972647 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40108.972647 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -206,13 +206,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.463240 # Cycle average of tags in use +system.iocache.tagsinuse 0.463236 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709322874000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.463240 # Average occupied blocks per context -system.iocache.occ_percent::1 0.028953 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709322783000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.463236 # Average occupied blocks per context +system.iocache.occ_percent::1 0.028952 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -229,10 +229,10 @@ system.iocache.demand_misses::total 41729 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41729 # number of overall misses system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency 20390998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5721236806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741627804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741627804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 20391998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5720293806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5740685804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5740685804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -252,22 +252,22 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115203.378531 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115209.028249 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137688.602378 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137665.907923 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137593.227827 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137570.653598 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137593.227827 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137570.653598 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64620068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64638062 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6179.008223 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6181.319881 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -279,10 +279,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41729 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41729 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11186998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3560378000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571564998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571564998 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11187998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3559436992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3570624990 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3570624990 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -296,10 +296,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63203.378531 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85684.876781 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85662.230266 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85566.991541 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85566.991541 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -320,22 +320,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9507417 # DTB read hits -system.cpu0.dtb.read_misses 35968 # DTB read misses -system.cpu0.dtb.read_acv 598 # DTB read access violations -system.cpu0.dtb.read_accesses 640032 # DTB read accesses -system.cpu0.dtb.write_hits 6191307 # DTB write hits -system.cpu0.dtb.write_misses 8160 # DTB write misses -system.cpu0.dtb.write_acv 353 # DTB write access violations -system.cpu0.dtb.write_accesses 218604 # DTB write accesses -system.cpu0.dtb.data_hits 15698724 # DTB hits -system.cpu0.dtb.data_misses 44128 # DTB misses -system.cpu0.dtb.data_acv 951 # DTB access violations -system.cpu0.dtb.data_accesses 858636 # DTB accesses -system.cpu0.itb.fetch_hits 1059111 # ITB hits -system.cpu0.itb.fetch_misses 28345 # ITB misses -system.cpu0.itb.fetch_acv 951 # ITB acv -system.cpu0.itb.fetch_accesses 1087456 # ITB accesses +system.cpu0.dtb.read_hits 9525013 # DTB read hits +system.cpu0.dtb.read_misses 35809 # DTB read misses +system.cpu0.dtb.read_acv 596 # DTB read access violations +system.cpu0.dtb.read_accesses 640960 # DTB read accesses +system.cpu0.dtb.write_hits 6193277 # DTB write hits +system.cpu0.dtb.write_misses 8191 # DTB write misses +system.cpu0.dtb.write_acv 352 # DTB write access violations +system.cpu0.dtb.write_accesses 218947 # DTB write accesses +system.cpu0.dtb.data_hits 15718290 # DTB hits +system.cpu0.dtb.data_misses 44000 # DTB misses +system.cpu0.dtb.data_acv 948 # DTB access violations +system.cpu0.dtb.data_accesses 859907 # DTB accesses +system.cpu0.itb.fetch_hits 1059968 # ITB hits +system.cpu0.itb.fetch_misses 28334 # ITB misses +system.cpu0.itb.fetch_acv 968 # ITB acv +system.cpu0.itb.fetch_accesses 1088302 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -348,276 +348,276 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112078637 # number of cpu cycles simulated +system.cpu0.numCycles 112143855 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13676513 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11471993 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 481224 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 12342117 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 6355141 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13691834 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11482212 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 486842 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 12387016 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 6381871 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 915334 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37832 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28007609 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69419364 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13676513 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 7270475 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 13464854 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2130456 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34838342 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 192876 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 330870 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8508842 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 295697 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 78241728 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.887242 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.203788 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 919331 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37475 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28027181 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69568075 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13691834 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 7301202 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 13494473 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2151438 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34839073 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 192820 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 330609 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8536872 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 297084 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 78309049 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.888378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.203941 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64776874 82.79% 82.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 958993 1.23% 84.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1895458 2.42% 86.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 896557 1.15% 87.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2826529 3.61% 91.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 644193 0.82% 92.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 736181 0.94% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1019927 1.30% 94.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4487016 5.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64814576 82.77% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 945457 1.21% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1900376 2.43% 86.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 913364 1.17% 87.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2830968 3.62% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 643425 0.82% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 763526 0.98% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1019235 1.30% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4478122 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78241728 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.122026 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.619381 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29114965 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34547748 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12317154 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 921824 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1340036 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 563514 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 37992 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 67952438 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 114909 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1340036 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30246504 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12447336 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18631420 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11494424 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4082006 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64196257 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6719 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 464674 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1470831 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 42946380 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 77900777 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77469173 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 431604 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36477108 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6469264 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1576496 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238440 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11483101 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10008373 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6527102 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1185571 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 771360 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56320474 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2007436 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54875963 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 110266 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7429207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3754226 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1369428 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78241728 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.701364 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.347589 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 78309049 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.122092 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.620347 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29152885 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34531702 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12346249 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 922431 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1355781 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 563186 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 37995 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 68107436 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 115019 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1355781 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30289459 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12441617 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18623001 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11519994 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4079195 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64318914 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6762 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 463310 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1470134 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 43045469 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 78042276 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77610485 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 431791 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36467151 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6578318 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1575666 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238414 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11470150 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10031617 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6527341 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1189503 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 776121 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56398484 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2006474 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54915556 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 111021 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7522313 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3811151 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1368811 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 78309049 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.701267 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.347671 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54100520 69.15% 69.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10639232 13.60% 82.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5191485 6.64% 89.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3321136 4.24% 93.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2520069 3.22% 96.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1468713 1.88% 98.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 637402 0.81% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 263268 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 99903 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54156181 69.16% 69.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10641057 13.59% 82.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5191025 6.63% 89.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3329795 4.25% 93.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2517318 3.21% 96.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1471186 1.88% 98.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 638979 0.82% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 264076 0.34% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 99432 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78241728 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 78309049 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61581 8.74% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 342929 48.66% 57.40% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 300261 42.60% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 63169 8.93% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 344330 48.66% 57.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 300145 42.41% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3329 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37711302 68.72% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60327 0.11% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9937545 18.11% 86.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6268980 11.42% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 877144 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3325 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37729557 68.70% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60298 0.11% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9958587 18.13% 86.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6269977 11.42% 98.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 876476 1.60% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54875963 # Type of FU issued -system.cpu0.iq.rate 0.489620 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 704772 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012843 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 188187092 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65472775 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53463452 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 621599 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 297101 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294471 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55250754 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326652 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 544032 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54915556 # Type of FU issued +system.cpu0.iq.rate 0.489688 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 707644 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012886 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 188337006 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65642365 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53492231 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 621820 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 297359 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294491 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55293187 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326688 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 545095 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1411765 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 14119 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13054 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 526523 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1437170 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 14653 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12768 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 528040 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 19033 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 166880 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18971 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 166861 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1340036 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8692237 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 606269 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61830785 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 830784 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10008373 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6527102 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1772467 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 482817 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10549 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13054 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 346528 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 358003 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 704531 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54241616 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9570533 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 634346 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1355781 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8686714 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 606542 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61919404 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 833136 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10031617 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6527341 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1771520 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 483474 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10610 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12768 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 354996 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 356258 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 711254 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54276592 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9587869 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 638964 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3502875 # number of nop insts executed -system.cpu0.iew.exec_refs 15784325 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8657029 # Number of branches executed -system.cpu0.iew.exec_stores 6213792 # Number of stores executed -system.cpu0.iew.exec_rate 0.483960 # Inst execution rate -system.cpu0.iew.wb_sent 53872827 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53757923 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26542591 # num instructions producing a value -system.cpu0.iew.wb_consumers 35724968 # num instructions consuming a value +system.cpu0.iew.exec_nop 3514446 # number of nop insts executed +system.cpu0.iew.exec_refs 15803723 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8658040 # Number of branches executed +system.cpu0.iew.exec_stores 6215854 # Number of stores executed +system.cpu0.iew.exec_rate 0.483991 # Inst execution rate +system.cpu0.iew.wb_sent 53903758 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53786722 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26555285 # num instructions producing a value +system.cpu0.iew.wb_consumers 35742632 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.479645 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742970 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.479623 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742958 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 53656716 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 8078010 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638008 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 642783 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76901692 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.697731 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.609209 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 53643051 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 8183882 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 637663 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 648245 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76953268 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.697086 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608248 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56673915 73.70% 73.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8488315 11.04% 84.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4528829 5.89% 90.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2497024 3.25% 93.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1465718 1.91% 95.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 614414 0.80% 96.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 447034 0.58% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 489019 0.64% 97.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1697424 2.21% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56721555 73.71% 73.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8492436 11.04% 84.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4533561 5.89% 90.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2497224 3.25% 93.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1462149 1.90% 95.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 614089 0.80% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 448311 0.58% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 488630 0.63% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1695313 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76901692 # Number of insts commited each cycle -system.cpu0.commit.count 53656716 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 76953268 # Number of insts commited each cycle +system.cpu0.commit.count 53643051 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14597187 # Number of memory references committed -system.cpu0.commit.loads 8596608 # Number of loads committed -system.cpu0.commit.membars 217615 # Number of memory barriers committed -system.cpu0.commit.branches 8092300 # Number of branches committed +system.cpu0.commit.refs 14593748 # Number of memory references committed +system.cpu0.commit.loads 8594447 # Number of loads committed +system.cpu0.commit.membars 217509 # Number of memory barriers committed +system.cpu0.commit.branches 8090596 # Number of branches committed system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49637924 # Number of committed integer instructions. -system.cpu0.commit.function_calls 704482 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1697424 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 49625357 # Number of committed integer instructions. +system.cpu0.commit.function_calls 704226 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1695313 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 136748495 # The number of ROB reads -system.cpu0.rob.rob_writes 124811050 # The number of ROB writes -system.cpu0.timesIdled 1231942 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33836909 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3682845519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50542242 # Number of Instructions Simulated -system.cpu0.committedInsts_total 50542242 # Number of Instructions Simulated -system.cpu0.cpi 2.217524 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.217524 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.450953 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.450953 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71124780 # number of integer regfile reads -system.cpu0.int_regfile_writes 38876207 # number of integer regfile writes -system.cpu0.fp_regfile_reads 143910 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146325 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1863327 # number of misc regfile reads -system.cpu0.misc_regfile_writes 888204 # number of misc regfile writes +system.cpu0.rob.rob_reads 136894487 # The number of ROB reads +system.cpu0.rob.rob_writes 125011331 # The number of ROB writes +system.cpu0.timesIdled 1231743 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33834806 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3682779567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 50529139 # Number of Instructions Simulated +system.cpu0.committedInsts_total 50529139 # Number of Instructions Simulated +system.cpu0.cpi 2.219390 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.219390 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.450574 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.450574 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71166140 # number of integer regfile reads +system.cpu0.int_regfile_writes 38904534 # number of integer regfile writes +system.cpu0.fp_regfile_reads 143931 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146323 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1862401 # number of misc regfile reads +system.cpu0.misc_regfile_writes 887781 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -649,233 +649,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 970482 # number of replacements -system.cpu0.icache.tagsinuse 510.008508 # Cycle average of tags in use -system.cpu0.icache.total_refs 7483994 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 970994 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.707559 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23358720000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 510.008508 # Average occupied blocks per context +system.cpu0.icache.replacements 970410 # number of replacements +system.cpu0.icache.tagsinuse 510.008513 # Cycle average of tags in use +system.cpu0.icache.total_refs 7511566 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 970922 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.736529 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23358767000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 510.008513 # Average occupied blocks per context system.cpu0.icache.occ_percent::0 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 7483994 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7483994 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 7483994 # number of demand (read+write) hits +system.cpu0.icache.ReadReq_hits::0 7511566 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7511566 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 7511566 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7483994 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 7483994 # number of overall hits +system.cpu0.icache.demand_hits::total 7511566 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 7511566 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 7483994 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 1024848 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1024848 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 1024848 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 7511566 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 1025306 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1025306 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 1025306 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1024848 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 1024848 # number of overall misses +system.cpu0.icache.demand_misses::total 1025306 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 1025306 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 1024848 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 15319794498 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 15319794498 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 15319794498 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 8508842 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8508842 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 8508842 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 1025306 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 15323045497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 15323045497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 15323045497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 8536872 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8536872 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 8536872 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8508842 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 8508842 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 8536872 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 8536872 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8508842 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.120445 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.120445 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 8536872 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.120103 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.120103 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.120445 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.120103 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14948.357706 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14944.851095 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14948.357706 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14944.851095 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14948.357706 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14944.851095 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1225998 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1297498 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 103 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 107 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11902.893204 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 218 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 53716 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 53716 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 53716 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 971132 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 971132 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 971132 # number of overall MSHR misses +system.cpu0.icache.writebacks 220 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 54249 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 54249 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 54249 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 971057 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 971057 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 971057 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 11617050998 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 11617050998 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 11617050998 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 11617533498 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 11617533498 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 11617533498 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.114132 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113749 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.114132 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.113749 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.114132 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.113749 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11962.381013 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11963.801814 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11963.801814 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11963.801814 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1339905 # number of replacements -system.cpu0.dcache.tagsinuse 503.729057 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11343106 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1340416 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.462377 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1340651 # number of replacements +system.cpu0.dcache.tagsinuse 503.872538 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11358067 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1341162 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.468826 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 504.729057 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 504.872538 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context 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number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1697480 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1808304 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1808304 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 21693 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21693 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 688 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 3505784 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3505435 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 3505435 # number of overall misses +system.cpu0.dcache.demand_misses::total 3505784 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 3505784 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3505435 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 37036233000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 55166183811 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 327139500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 6516000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 92202416811 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 92202416811 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8674794 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8674794 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5776492 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5776492 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 204219 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204219 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 209251 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209251 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14451286 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 3505784 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 37053025000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 55161743853 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 326351000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 6342500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 92214768853 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 92214768853 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8691352 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8691352 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 5775274 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5775274 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 204237 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 204237 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 209178 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209178 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14466626 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14451286 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14451286 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14466626 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14466626 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14451286 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.195569 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.313151 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106410 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003312 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.242569 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14466626 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.195307 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.313111 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106215 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003289 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.242336 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.242569 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.242336 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 21830.708156 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 21828.254236 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 30496.835844 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 30504.684972 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15054.047214 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15044.069516 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9402.597403 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9218.750000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 26302.703320 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 26303.608224 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 26302.703320 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 26303.608224 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 886352311 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 100011 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8862.548230 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 23388.888889 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 888039305 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 98700 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8997.358713 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 790429 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 651194 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1524352 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4898 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 2175546 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 2175546 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 1045326 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 284563 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 693 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1329889 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1329889 # number of overall MSHR misses +system.cpu0.dcache.writebacks 791009 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 651385 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1523767 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4864 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 2175152 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 2175152 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 1046095 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 284537 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 688 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1330632 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1330632 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 24217800500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 8294565311 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 195726500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4430000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 32512365811 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 32512365811 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 916795000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1253240498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 2170035498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120502 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 24225951000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 8293520304 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 195490000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4269500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 32519471304 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 32519471304 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 916801000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1252089998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 2168890998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120360 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049262 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049268 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082426 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082399 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003312 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003289 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.092026 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.091979 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.092026 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.091979 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23167.701272 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29148.432196 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11627.547080 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6392.496392 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23158.461708 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29147.423021 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11616.257650 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6205.668605 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 24439.117129 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 24439.117129 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -886,22 +886,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1326048 # DTB read hits -system.cpu1.dtb.read_misses 10245 # DTB read misses -system.cpu1.dtb.read_acv 4 # DTB read access violations -system.cpu1.dtb.read_accesses 331667 # DTB read accesses -system.cpu1.dtb.write_hits 775032 # DTB write hits -system.cpu1.dtb.write_misses 3356 # DTB write misses -system.cpu1.dtb.write_acv 50 # DTB write access violations -system.cpu1.dtb.write_accesses 128144 # DTB write accesses -system.cpu1.dtb.data_hits 2101080 # DTB hits -system.cpu1.dtb.data_misses 13601 # DTB misses -system.cpu1.dtb.data_acv 54 # DTB access violations -system.cpu1.dtb.data_accesses 459811 # DTB accesses -system.cpu1.itb.fetch_hits 367550 # ITB hits -system.cpu1.itb.fetch_misses 7752 # ITB misses -system.cpu1.itb.fetch_acv 129 # ITB acv -system.cpu1.itb.fetch_accesses 375302 # ITB accesses +system.cpu1.dtb.read_hits 1327892 # DTB read hits +system.cpu1.dtb.read_misses 10318 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 331425 # DTB read accesses +system.cpu1.dtb.write_hits 775217 # DTB write hits +system.cpu1.dtb.write_misses 3380 # DTB write misses +system.cpu1.dtb.write_acv 51 # DTB write access violations +system.cpu1.dtb.write_accesses 128049 # DTB write accesses +system.cpu1.dtb.data_hits 2103109 # DTB hits +system.cpu1.dtb.data_misses 13698 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 459474 # DTB accesses +system.cpu1.itb.fetch_hits 367800 # ITB hits +system.cpu1.itb.fetch_misses 7781 # ITB misses +system.cpu1.itb.fetch_acv 134 # ITB acv +system.cpu1.itb.fetch_accesses 375581 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -914,501 +914,501 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 9966962 # number of cpu cycles simulated +system.cpu1.numCycles 9964881 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1746608 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1443175 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 66232 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1579747 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 700902 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1747552 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1443569 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 66414 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1567726 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 697812 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 120007 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5197 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3352188 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8389538 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1746608 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 820909 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1600088 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 340649 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3953742 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24318 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65300 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48169 # Number of stall cycles due to pending quiesce instructions +system.cpu1.BPredUnit.usedRAS 120159 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5219 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3352807 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8393265 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1747552 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 817971 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1599998 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 341231 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3951622 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24365 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48200 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1052111 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 37387 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9268453 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.905171 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.248228 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 1053319 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 37675 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9267506 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.905666 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.249416 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7668365 82.74% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 115994 1.25% 83.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 231226 2.49% 86.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 132329 1.43% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 251751 2.72% 90.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 85931 0.93% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 105894 1.14% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 73622 0.79% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 603341 6.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7667508 82.74% 82.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 116348 1.26% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 230890 2.49% 86.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 132710 1.43% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 250243 2.70% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 85158 0.92% 91.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 106718 1.15% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 73511 0.79% 93.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 604420 6.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9268453 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.175240 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.841735 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3426888 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4059985 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1487039 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 74425 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 220115 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 74752 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4586 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8123817 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13801 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 220115 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3563676 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 426586 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3211249 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1411283 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 435542 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7548530 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 46052 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 92764 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5048861 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9245845 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9192898 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52947 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4017246 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1031615 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 305905 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22528 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1292369 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1416426 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 841512 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 141179 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 90021 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6602199 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 325316 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6284355 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22621 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1273450 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 716539 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 249793 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9268453 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.678037 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.328780 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9267506 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.175371 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.842285 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3427974 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4057837 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1486886 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 74257 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 220551 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 74813 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4599 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8126768 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13850 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 220551 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3564378 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 427759 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3208421 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1411256 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 435139 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7552023 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 45897 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 92610 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 5051424 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9247695 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9194844 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52851 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4016877 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1034547 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 305973 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22549 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1293822 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1418447 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 841500 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 143535 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 89440 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6603642 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 325438 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6286957 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22758 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1275148 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 714507 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 249945 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9267506 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.678387 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.328894 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 6498051 70.11% 70.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1227525 13.24% 83.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 582679 6.29% 89.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 391581 4.22% 93.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 294983 3.18% 97.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 158395 1.71% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 72456 0.78% 99.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 32178 0.35% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10605 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 6496050 70.09% 70.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1227596 13.25% 83.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 583666 6.30% 89.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 391304 4.22% 93.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 294316 3.18% 97.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 159029 1.72% 98.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 73572 0.79% 99.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 31508 0.34% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10465 0.11% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9268453 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9267506 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2859 1.97% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 82047 56.45% 58.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60446 41.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2850 1.96% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 81883 56.36% 58.33% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60541 41.67% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3978 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3890788 61.91% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10226 0.16% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1381194 21.98% 84.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 794695 12.65% 96.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 191415 3.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3977 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3891249 61.89% 61.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10225 0.16% 62.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1383111 22.00% 84.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 794977 12.64% 96.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 191359 3.04% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6284355 # Type of FU issued -system.cpu1.iq.rate 0.630519 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 145352 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023129 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 21926150 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8163461 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6082297 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 78986 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 39141 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37853 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6384800 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40929 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 61528 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6286957 # Type of FU issued +system.cpu1.iq.rate 0.630911 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 145274 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023107 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 21930562 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8166757 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6084651 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 78890 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 39096 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37806 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6387378 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40876 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 61877 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 262809 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1750 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 113415 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 265041 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6645 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1728 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 113419 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 366 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 22210 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 368 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 22536 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 220115 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 309272 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12037 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7192077 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 99271 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1416426 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 841512 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 303434 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 3996 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4977 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1750 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 48213 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 60062 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 108275 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6205529 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1339876 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 78826 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 220551 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 309881 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12131 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7193888 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 99371 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1418447 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 841500 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 303567 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4003 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 5102 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1728 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 48086 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 60250 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 108336 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6208556 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1341795 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 78401 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 264562 # number of nop insts executed -system.cpu1.iew.exec_refs 2121617 # number of memory reference insts executed -system.cpu1.iew.exec_branches 906286 # Number of branches executed -system.cpu1.iew.exec_stores 781741 # Number of stores executed -system.cpu1.iew.exec_rate 0.622610 # Inst execution rate -system.cpu1.iew.wb_sent 6147670 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6120150 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2958458 # num instructions producing a value -system.cpu1.iew.wb_consumers 4045224 # num instructions consuming a value +system.cpu1.iew.exec_nop 264808 # number of nop insts executed +system.cpu1.iew.exec_refs 2123746 # number of memory reference insts executed +system.cpu1.iew.exec_branches 906293 # Number of branches executed +system.cpu1.iew.exec_stores 781951 # Number of stores executed +system.cpu1.iew.exec_rate 0.623044 # Inst execution rate +system.cpu1.iew.wb_sent 6150217 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6122457 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2959215 # num instructions producing a value +system.cpu1.iew.wb_consumers 4044738 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614044 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.731346 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614403 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.731621 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5812223 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1307029 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 75523 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 100285 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9048338 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642353 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.547343 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5811574 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1309607 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 75493 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 100450 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9046955 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642379 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.547455 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6777327 74.90% 74.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1099919 12.16% 87.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 394591 4.36% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 244546 2.70% 94.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 155405 1.72% 95.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 74689 0.83% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76341 0.84% 97.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 67787 0.75% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 157733 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6775881 74.90% 74.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1100597 12.17% 87.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 394396 4.36% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 244103 2.70% 94.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 155347 1.72% 95.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 74536 0.82% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 76677 0.85% 97.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 67598 0.75% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 157820 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9048338 # Number of insts commited each cycle -system.cpu1.commit.count 5812223 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 9046955 # Number of insts commited each cycle +system.cpu1.commit.count 5811574 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1881714 # Number of memory references committed -system.cpu1.commit.loads 1153617 # Number of loads committed -system.cpu1.commit.membars 20508 # Number of memory barriers committed -system.cpu1.commit.branches 821256 # Number of branches committed +system.cpu1.commit.refs 1881487 # Number of memory references committed +system.cpu1.commit.loads 1153406 # Number of loads committed +system.cpu1.commit.membars 20496 # Number of memory barriers committed +system.cpu1.commit.branches 821024 # Number of branches committed system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5437919 # Number of committed integer instructions. -system.cpu1.commit.function_calls 89388 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 157733 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 5437311 # Number of committed integer instructions. +system.cpu1.commit.function_calls 89377 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 157820 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 15919184 # The number of ROB reads -system.cpu1.rob.rob_writes 14457399 # The number of ROB writes -system.cpu1.timesIdled 81947 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 698509 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3784960163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5588724 # Number of Instructions Simulated -system.cpu1.committedInsts_total 5588724 # Number of Instructions Simulated -system.cpu1.cpi 1.783406 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.783406 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.560725 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.560725 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8091693 # number of integer regfile reads -system.cpu1.int_regfile_writes 4410635 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24636 # number of floating regfile reads -system.cpu1.fp_regfile_writes 23087 # number of floating regfile writes -system.cpu1.misc_regfile_reads 284786 # number of misc regfile reads -system.cpu1.misc_regfile_writes 134830 # number of misc regfile writes -system.cpu1.icache.replacements 110610 # number of replacements -system.cpu1.icache.tagsinuse 452.934793 # Cycle average of tags in use -system.cpu1.icache.total_refs 935676 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 111121 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.420335 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874818206000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 452.934793 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.884638 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 935676 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 935676 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 935676 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 15919643 # The number of ROB reads +system.cpu1.rob.rob_writes 14461697 # The number of ROB writes +system.cpu1.timesIdled 81901 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 697375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3784961926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5588082 # Number of Instructions Simulated +system.cpu1.committedInsts_total 5588082 # Number of Instructions Simulated +system.cpu1.cpi 1.783238 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.783238 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.560778 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.560778 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8095217 # number of integer regfile reads +system.cpu1.int_regfile_writes 4412873 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24584 # number of floating regfile reads +system.cpu1.fp_regfile_writes 23091 # number of floating regfile writes +system.cpu1.misc_regfile_reads 284668 # number of misc regfile reads +system.cpu1.misc_regfile_writes 134791 # number of misc regfile writes +system.cpu1.icache.replacements 110606 # number of replacements +system.cpu1.icache.tagsinuse 453.435417 # Cycle average of tags in use +system.cpu1.icache.total_refs 936898 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 111117 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.431635 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874818624000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 453.435417 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.885616 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 936898 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 936898 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 936898 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 935676 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 935676 # number of overall hits +system.cpu1.icache.demand_hits::total 936898 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 936898 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 935676 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 116435 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 116435 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 116435 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 936898 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 116421 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 116421 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 116421 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 116435 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 116435 # number of overall misses +system.cpu1.icache.demand_misses::total 116421 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 116421 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 116435 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 1751730499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 1751730499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 1751730499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1052111 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1052111 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1052111 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 116421 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 1750783999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 1750783999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 1750783999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1053319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1053319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1053319 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1052111 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1052111 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1053319 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1053319 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1052111 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.110668 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.110668 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1053319 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.110528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.110528 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.110668 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.110528 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.707339 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 15038.386537 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 15044.707339 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 15038.386537 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 15044.707339 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 15038.386537 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 93999 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 96999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7230.692308 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6928.500000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks 37 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 5243 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 5243 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 5243 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 111192 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 111192 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 111192 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits 5236 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 5236 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 5236 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 111185 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 111185 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 111185 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1333669999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 1333669999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 1333669999 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 1333353499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 1333353499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 1333353499 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.105685 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.105557 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.105685 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.105557 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.105685 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.105557 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11994.298142 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11992.206674 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11992.206674 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11992.206674 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62429 # number of replacements -system.cpu1.dcache.tagsinuse 392.995073 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1698421 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62755 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 27.064314 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874613639500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 392.995073 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.767569 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1125916 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1125916 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 549554 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 549554 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 16796 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16796 # number of LoadLockedReq hits +system.cpu1.dcache.replacements 62388 # number of replacements +system.cpu1.dcache.tagsinuse 392.324021 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1699992 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62715 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 27.106625 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1874614053500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 392.324021 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.766258 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 1127254 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1127254 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 549515 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 549515 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 16791 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16791 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::0 14923 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 1675470 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::0 1676769 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1675470 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 1675470 # number of overall hits +system.cpu1.dcache.demand_hits::total 1676769 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 1676769 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1675470 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 106694 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 106694 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 157811 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 157811 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 1480 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1480 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 700 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 700 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 264505 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 1676769 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 106582 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 106582 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 157839 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 157839 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 1481 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1481 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 695 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 695 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 264421 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 264505 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 264505 # number of overall misses +system.cpu1.dcache.demand_misses::total 264421 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 264421 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 264505 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 1790096000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 5171682833 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 19414000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 8395500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 6961778833 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 6961778833 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 1232610 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1232610 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 707365 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 707365 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 18276 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18276 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 15623 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15623 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 1939975 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 264421 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 1787903500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 5181152780 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 19396000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 8380000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 6969056280 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 6969056280 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 1233836 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1233836 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 707354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 707354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 18272 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18272 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 15618 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15618 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 1941190 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1939975 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 1939975 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1941190 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 1941190 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1939975 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.086559 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.223097 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.080981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044806 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.136345 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 1941190 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.086383 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.223140 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081053 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044500 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.136216 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.136345 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.136216 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 16777.850676 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 16774.910398 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 32771.371026 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 32825.555028 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13117.567568 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13096.556381 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11993.571429 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12057.553957 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 26320.027345 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 26355.910764 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 26320.027345 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 26355.910764 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 86579997 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 86281997 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6823 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6886 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12689.432361 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 35856 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 62883 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 134026 # number of WriteReq MSHR hits +system.cpu1.dcache.writebacks 35937 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 62835 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 134042 # number of WriteReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 196909 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 196909 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 43811 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 23785 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1185 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 699 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 67596 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 67596 # number of overall MSHR misses +system.cpu1.dcache.demand_mshr_hits 196877 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 196877 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 43747 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 23797 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1186 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 695 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 67544 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 67544 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 556154000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 752491985 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11636500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6289000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 1308645985 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 1308645985 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19117500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320801000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 339918500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035543 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 555340000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 753314485 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6287000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 1308654485 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 1308654485 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19116500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320800500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 339917000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035456 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033625 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033642 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064908 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044742 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044500 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.034844 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.034795 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.034844 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.034795 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.391819 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31637.249737 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9819.831224 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8997.138770 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.356184 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31655.859352 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9807.757167 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9046.043165 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19374.844324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19374.844324 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1416,31 +1416,31 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6372 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199307 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71537 40.62% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.13% 40.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1922 1.09% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102421 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 176125 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70172 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1922 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199147 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71494 40.63% 40.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 238 0.14% 40.76% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1915 1.09% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102317 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 175972 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70129 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 238 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1915 1.34% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70164 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142503 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1858853057000 97.97% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90805500 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 391568500 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4023000 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38125490000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897464944000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980919 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 70122 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142412 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1858860218500 97.97% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90821000 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 390050500 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4014000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38119760000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897464864000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980907 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685055 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685341 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed @@ -1477,54 +1477,54 @@ system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # nu system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.16% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169189 91.54% 93.71% # number of callpals executed -system.cpu0.kern.callpal::rdps 6337 3.43% 97.14% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169050 91.54% 93.71% # number of callpals executed +system.cpu0.kern.callpal::rdps 6330 3.43% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rti 4768 2.58% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4761 2.58% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184818 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7264 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1248 # number of protection mode switches +system.cpu0.kern.callpal::total 184665 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7257 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1249 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1247 -system.cpu0.kern.mode_good::user 1248 +system.cpu0.kern.mode_good::kernel 1248 +system.cpu0.kern.mode_good::user 1249 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.171669 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.171972 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895604498000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1860438000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1895601847000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1863009000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3841 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38564 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10256 33.36% 33.36% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 38551 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10250 33.36% 33.36% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18460 60.05% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30741 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10244 45.72% 45.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 8.57% 54.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.47% 54.75% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10139 45.25% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22408 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871092276500 98.61% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343292500 0.02% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 42130500 0.00% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25986985000 1.37% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897464684500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998830 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_count::31 18453 60.05% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30728 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10238 45.71% 45.71% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 8.57% 54.29% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.47% 54.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10133 45.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22396 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871094081500 98.61% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343283500 0.02% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 42013500 0.00% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25985147000 1.37% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897464525500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998829 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.549242 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.549125 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed @@ -1547,29 +1547,29 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26187 82.50% 83.80% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26174 82.49% 83.79% # number of callpals executed system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.41% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.40% # number of callpals executed system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2528 7.96% 99.40% # number of callpals executed +system.cpu1.kern.callpal::rti 2528 7.97% 99.39% # number of callpals executed system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31743 # number of callpals executed +system.cpu1.kern.callpal::total 31730 # number of callpals executed system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches -system.cpu1.kern.mode_switch::user 492 # number of protection mode switches +system.cpu1.kern.mode_switch::user 491 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 522 -system.cpu1.kern.mode_good::user 492 +system.cpu1.kern.mode_good::kernel 521 +system.cpu1.kern.mode_good::user 491 system.cpu1.kern.mode_good::idle 30 -system.cpu1.kern.mode_switch_good::kernel 0.600690 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.615296 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2061638000 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 848590000 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893876047000 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 1.614145 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2062444500 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 847773000 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893876331500 99.85% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 394 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index b0a37466e..c884dc482 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,14 +11,14 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -104,6 +105,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -135,6 +137,7 @@ tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -496,7 +499,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -516,7 +519,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -616,7 +619,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -645,7 +647,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -686,7 +688,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -768,7 +769,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -785,7 +785,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -802,7 +801,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -819,7 +817,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -836,7 +833,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -853,7 +849,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -870,7 +865,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -887,7 +881,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -904,7 +897,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -921,7 +913,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -938,7 +929,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -955,7 +945,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -972,7 +961,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -989,7 +977,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1006,7 +993,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1023,7 +1009,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1040,7 +1025,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1057,7 +1041,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1074,7 +1057,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1090,7 +1072,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -1155,7 +1136,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1166,7 +1146,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 2911b29fc..0ab209212 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 06:11:15 -gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Feb 3 2012 13:46:22 +gem5 started Feb 3 2012 13:46:34 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858873594500 because m5_exit instruction encountered +Exiting @ tick 1859850554500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index de8941321..44b3ca581 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858874 # Number of seconds simulated -sim_ticks 1858873594500 # Number of ticks simulated -final_tick 1858873594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859851 # Number of seconds simulated +sim_ticks 1859850554500 # Number of ticks simulated +final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134152 # Simulator instruction rate (inst/s) -host_tick_rate 4696460042 # Simulator tick rate (ticks/s) -host_mem_usage 295432 # Number of bytes of host memory used -host_seconds 395.80 # Real time elapsed on the host -sim_insts 53097697 # Number of instructions simulated -system.physmem.bytes_read 29819840 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1062784 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10193408 # Number of bytes written to this memory -system.physmem.num_reads 465935 # Number of read requests responded to by this memory -system.physmem.num_writes 159272 # Number of write requests responded to by this memory +host_inst_rate 100457 # Simulator instruction rate (inst/s) +host_tick_rate 3519496587 # Simulator tick rate (ticks/s) +host_mem_usage 323652 # Number of bytes of host memory used +host_seconds 528.44 # Real time elapsed on the host +sim_insts 53085804 # Number of instructions simulated +system.physmem.bytes_read 29820864 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10193536 # Number of bytes written to this memory +system.physmem.num_reads 465951 # Number of read requests responded to by this memory +system.physmem.num_writes 159274 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16041887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 571735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5483648 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21525535 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 391354 # number of replacements -system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use -system.l2c.total_refs 2410581 # Total number of references to valid blocks. -system.l2c.sampled_refs 424231 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.682237 # Average number of references to valid blocks. +system.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 391353 # number of replacements +system.l2c.tagsinuse 34925.820021 # Cycle average of tags in use +system.l2c.total_refs 2406767 # Total number of references to valid blocks. +system.l2c.sampled_refs 424249 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.673006 # Average number of references to valid blocks. system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12293.296692 # Average occupied blocks per context -system.l2c.occ_blocks::1 22604.789448 # Average occupied blocks per context -system.l2c.occ_percent::0 0.187581 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.344922 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1801188 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1801188 # number of ReadReq hits -system.l2c.Writeback_hits::0 835090 # number of Writeback hits -system.l2c.Writeback_hits::total 835090 # number of Writeback hits +system.l2c.occ_blocks::0 12305.465353 # Average occupied blocks per context +system.l2c.occ_blocks::1 22620.354669 # Average occupied blocks per context +system.l2c.occ_percent::0 0.187767 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.345159 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1800764 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits +system.l2c.Writeback_hits::0 835189 # number of Writeback hits +system.l2c.Writeback_hits::total 835189 # number of Writeback hits system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183163 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183163 # number of ReadExReq hits -system.l2c.demand_hits::0 1984351 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183241 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits +system.l2c.demand_hits::0 1984005 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1984351 # number of demand (read+write) hits -system.l2c.overall_hits::0 1984351 # number of overall hits +system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits +system.l2c.overall_hits::0 1984005 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1984351 # number of overall hits -system.l2c.ReadReq_misses::0 308072 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308072 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 33 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 33 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116926 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116926 # number of ReadExReq misses -system.l2c.demand_misses::0 424998 # number of demand (read+write) misses +system.l2c.overall_hits::total 1984005 # number of overall hits +system.l2c.ReadReq_misses::0 308137 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 35 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116889 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses +system.l2c.demand_misses::0 425026 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424998 # number of demand (read+write) misses -system.l2c.overall_misses::0 424998 # number of overall misses +system.l2c.demand_misses::total 425026 # number of demand (read+write) misses +system.l2c.overall_misses::0 425026 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424998 # number of overall misses -system.l2c.ReadReq_miss_latency 16035098000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6133668000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22168766000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22168766000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2109260 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109260 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835090 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835090 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 49 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::total 425026 # number of overall misses +system.l2c.ReadReq_miss_latency 16037812500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 424500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6132457500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22170270000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22170270000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2108901 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 835189 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 51 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300089 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300089 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2409349 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300130 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2409031 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2409349 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2409349 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2409031 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2409349 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146057 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.673469 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389638 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176395 # miss rate for demand accesses +system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146113 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.686275 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389461 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176430 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176395 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176430 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52049.838999 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52047.668732 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 12878.787879 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 12128.571429 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52457.691189 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52463.940148 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52162.047821 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52162.150080 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52162.047821 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52162.150080 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -110,43 +110,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117760 # number of writebacks +system.l2c.writebacks 117762 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308072 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116926 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 424998 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 424998 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308137 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116889 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 425026 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 425026 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12331827500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1380000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4711722000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17043549500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17043549500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 810479000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1115452498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1925931498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146057 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12334071500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1460000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4711233500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17045305000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17045305000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 809589500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1114928998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1924518498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146113 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.673469 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.686275 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389638 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389461 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176430 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176430 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40029.043535 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41818.181818 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40296.614953 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40027.882078 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41714.285714 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40305.191250 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -154,13 +154,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.268274 # Cycle average of tags in use +system.iocache.tagsinuse 1.276011 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338694000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.268274 # Average occupied blocks per context -system.iocache.occ_percent::1 0.079267 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.276011 # Average occupied blocks per context +system.iocache.occ_percent::1 0.079751 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -177,10 +177,10 @@ system.iocache.demand_misses::total 41725 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722643806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742583804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742583804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5721891806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741829804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741829804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -200,22 +200,22 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137722.463564 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137704.365759 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137629.330234 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137611.259533 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137629.330234 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137611.259533 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64634068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6174.442874 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -227,10 +227,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561790996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572734994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572734994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561041984 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571983982 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571983982 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -244,10 +244,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85718.882268 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85700.856373 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -268,22 +268,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10138302 # DTB read hits -system.cpu.dtb.read_misses 46569 # DTB read misses -system.cpu.dtb.read_acv 588 # DTB read access violations -system.cpu.dtb.read_accesses 971478 # DTB read accesses -system.cpu.dtb.write_hits 6627002 # DTB write hits -system.cpu.dtb.write_misses 12216 # DTB write misses -system.cpu.dtb.write_acv 416 # DTB write access violations -system.cpu.dtb.write_accesses 347261 # DTB write accesses -system.cpu.dtb.data_hits 16765304 # DTB hits -system.cpu.dtb.data_misses 58785 # DTB misses -system.cpu.dtb.data_acv 1004 # DTB access violations -system.cpu.dtb.data_accesses 1318739 # DTB accesses -system.cpu.itb.fetch_hits 1327158 # ITB hits -system.cpu.itb.fetch_misses 39816 # ITB misses -system.cpu.itb.fetch_acv 1096 # ITB acv -system.cpu.itb.fetch_accesses 1366974 # ITB accesses +system.cpu.dtb.read_hits 10136178 # DTB read hits +system.cpu.dtb.read_misses 46729 # DTB read misses +system.cpu.dtb.read_acv 584 # DTB read access violations +system.cpu.dtb.read_accesses 970980 # DTB read accesses +system.cpu.dtb.write_hits 6626287 # DTB write hits +system.cpu.dtb.write_misses 12218 # DTB write misses +system.cpu.dtb.write_acv 419 # DTB write access violations +system.cpu.dtb.write_accesses 347267 # DTB write accesses +system.cpu.dtb.data_hits 16762465 # DTB hits +system.cpu.dtb.data_misses 58947 # DTB misses +system.cpu.dtb.data_acv 1003 # DTB access violations +system.cpu.dtb.data_accesses 1318247 # DTB accesses +system.cpu.itb.fetch_hits 1326719 # ITB hits +system.cpu.itb.fetch_misses 39613 # ITB misses +system.cpu.itb.fetch_acv 1063 # ITB acv +system.cpu.itb.fetch_accesses 1366332 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -296,276 +296,276 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 116293341 # number of cpu cycles simulated +system.cpu.numCycles 116271514 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14403200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12045652 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 530716 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12993662 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6702662 # Number of BTB hits +system.cpu.BPredUnit.lookups 14404381 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 972407 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45058 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29094387 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 73505774 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14403200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7675069 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14268794 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2359863 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36645005 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31889 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259043 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335706 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9051868 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 321893 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 82174946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.894503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211429 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67906152 82.64% 82.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1023009 1.24% 83.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2022244 2.46% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 965640 1.18% 87.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2953506 3.59% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 686113 0.83% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 790817 0.96% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1067854 1.30% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4759611 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 82174946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123852 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632072 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30353273 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36299982 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13051372 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 972104 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1498214 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 610003 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42096 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 71896046 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1498214 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31555942 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12820674 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19773044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12199083 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4327987 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 67967172 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7022 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 504365 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1538985 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45476353 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 82567749 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82088652 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479097 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38265070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7211275 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700634 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251496 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12093975 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10722948 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6992313 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1255970 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 835280 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59689379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116105 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57965210 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118570 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8314088 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4277616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1448303 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 82174946 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705388 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.352124 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13055396 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12205401 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56717955 69.02% 69.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11192734 13.62% 82.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5489796 6.68% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3501881 4.26% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2637968 3.21% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1562716 1.90% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 689256 0.84% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 274867 0.33% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 107773 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 82174946 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 67060 8.71% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 379426 49.28% 57.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323507 42.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39583689 68.29% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62189 0.11% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10615864 18.31% 86.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6714571 11.58% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952373 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57965210 # Type of FU issued -system.cpu.iq.rate 0.498440 # Inst issue rate -system.cpu.iq.fu_busy_cnt 769993 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013284 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 198301844 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 69800593 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56410393 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692084 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 332994 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328299 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58364794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363128 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 575597 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57966423 # Type of FU issued +system.cpu.iq.rate 0.498544 # Inst issue rate +system.cpu.iq.fu_busy_cnt 769465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1608607 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14401 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 599018 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18904 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 170936 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1498214 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8974617 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 617389 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65429620 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 865390 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10722948 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6992313 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1869565 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 485054 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15735 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14401 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 385242 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382803 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 768045 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57270091 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10215279 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 695118 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3624136 # number of nop insts executed -system.cpu.iew.exec_refs 16869985 # number of memory reference insts executed -system.cpu.iew.exec_branches 9097351 # Number of branches executed -system.cpu.iew.exec_stores 6654706 # Number of stores executed -system.cpu.iew.exec_rate 0.492462 # Inst execution rate -system.cpu.iew.wb_sent 56872608 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56738692 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28028831 # num instructions producing a value -system.cpu.iew.wb_consumers 37767423 # num instructions consuming a value +system.cpu.iew.exec_nop 3625473 # number of nop insts executed +system.cpu.iew.exec_refs 16867223 # number of memory reference insts executed +system.cpu.iew.exec_branches 9097936 # Number of branches executed +system.cpu.iew.exec_stores 6653902 # Number of stores executed +system.cpu.iew.exec_rate 0.492563 # Inst execution rate +system.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56738020 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28030988 # num instructions producing a value +system.cpu.iew.wb_consumers 37770905 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.487893 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742143 # average fanout of values written-back +system.cpu.iew.wb_rate 0.487979 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56292492 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9013620 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667802 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 700532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80676732 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.697754 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.611305 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59494729 73.74% 73.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8894659 11.03% 84.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4715834 5.85% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2613071 3.24% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1534221 1.90% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 644957 0.80% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475888 0.59% 97.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 517029 0.64% 97.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1786344 2.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80676732 # Number of insts commited each cycle -system.cpu.commit.count 56292492 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle +system.cpu.commit.count 56280196 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15507636 # Number of memory references committed -system.cpu.commit.loads 9114341 # Number of loads committed -system.cpu.commit.membars 227905 # Number of memory barriers committed -system.cpu.commit.branches 8463183 # Number of branches committed +system.cpu.commit.refs 15504446 # Number of memory references committed +system.cpu.commit.loads 9112319 # Number of loads committed +system.cpu.commit.membars 227818 # Number of memory barriers committed +system.cpu.commit.branches 8461284 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52130666 # Number of committed integer instructions. -system.cpu.commit.function_calls 744656 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1786344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52119152 # Number of committed integer instructions. +system.cpu.commit.function_calls 744404 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 143945413 # The number of ROB reads -system.cpu.rob.rob_writes 132113260 # The number of ROB writes -system.cpu.timesIdled 1256827 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34118395 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3601447413 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53097697 # Number of Instructions Simulated -system.cpu.committedInsts_total 53097697 # Number of Instructions Simulated -system.cpu.cpi 2.190177 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.190177 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456584 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456584 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75078413 # number of integer regfile reads -system.cpu.int_regfile_writes 40965985 # number of integer regfile writes -system.cpu.fp_regfile_reads 166494 # number of floating regfile reads +system.cpu.rob.rob_reads 143937484 # The number of ROB reads +system.cpu.rob.rob_writes 132136289 # The number of ROB writes +system.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53085804 # Number of Instructions Simulated +system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated +system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456568 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75080091 # number of integer regfile reads +system.cpu.int_regfile_writes 40965330 # number of integer regfile writes +system.cpu.fp_regfile_reads 166532 # number of floating regfile reads system.cpu.fp_regfile_writes 167403 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996876 # number of misc regfile reads -system.cpu.misc_regfile_writes 949968 # number of misc regfile writes +system.cpu.misc_regfile_reads 1996306 # number of misc regfile reads +system.cpu.misc_regfile_writes 949674 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -597,231 +597,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1004954 # number of replacements -system.cpu.icache.tagsinuse 509.962774 # Cycle average of tags in use -system.cpu.icache.total_refs 7985922 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005463 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.942532 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23358245000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.962774 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.996021 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 7985923 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7985923 # number of ReadReq hits -system.cpu.icache.demand_hits::0 7985923 # number of demand (read+write) hits +system.cpu.icache.replacements 1004588 # number of replacements +system.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use +system.cpu.icache.total_refs 7985769 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.963959 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.996023 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 7985770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits +system.cpu.icache.demand_hits::0 7985770 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7985923 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 7985923 # number of overall hits +system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 7985770 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7985923 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1065945 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065945 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1065945 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 7985770 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1065446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1065446 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065945 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1065945 # number of overall misses +system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1065446 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1065945 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15930410995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15930410995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15930410995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9051868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9051868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9051868 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1065446 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15927822494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15927822494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15927822494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9051216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9051216 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9051868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9051868 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9051216 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9051868 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.117760 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.117760 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.117713 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.117713 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.117760 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.117713 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14944.871447 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14949.441355 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14944.871447 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14949.441355 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14944.871447 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14949.441355 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1290996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10581.934426 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 235 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 60269 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 60269 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 60269 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005676 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005676 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005676 # number of overall MSHR misses +system.cpu.icache.writebacks 234 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 60134 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 60134 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 60134 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12050431496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12050431496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12050431496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12047333996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12047333996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12047333996 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111069 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.111101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.111069 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.111101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.111069 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.419284 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403374 # number of replacements -system.cpu.dcache.tagsinuse 511.996006 # Cycle average of tags in use -system.cpu.dcache.total_refs 12090411 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403886 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.612103 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1403406 # number of replacements +system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use +system.cpu.dcache.total_refs 12086534 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.996006 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.996008 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7456106 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7456106 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4221921 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4221921 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192075 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192075 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220104 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220104 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11678027 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 7453772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4220462 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192050 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220033 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11674234 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11678027 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11678027 # number of overall hits +system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11674234 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11678027 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1809770 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1809770 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1936125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1936125 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 22580 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22580 # number of LoadLockedReq misses +system.cpu.dcache.overall_hits::total 11674234 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1809182 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1936475 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 22599 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3745895 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3745657 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745895 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3745895 # number of overall misses +system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3745657 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3745895 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38933932500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57800126852 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 338100500 # number of LoadLockedReq miss cycles +system.cpu.dcache.overall_misses::total 3745657 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38930236000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57815325976 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 338636000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 96734059352 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 96734059352 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9265876 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9265876 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6158046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6158046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 214655 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214655 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220106 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220106 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15423922 # number of demand (read+write) accesses +system.cpu.dcache.demand_miss_latency 96745561976 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 96745561976 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9262954 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6156937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 214649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220035 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15419891 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15423922 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15423922 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15419891 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15423922 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.195316 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314406 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105192 # miss rate for LoadLockedReq accesses +system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.195314 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314519 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105284 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.242863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.242911 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.242863 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.242911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21513.193665 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29853.509898 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14973.449956 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25824.017852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25828.729640 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25824.017852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25828.729640 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 917367309 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 193500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 103073 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8900.170840 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834855 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 722036 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1637277 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5104 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2359313 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2359313 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087734 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298848 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17476 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834955 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 721461 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1637588 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5103 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2359049 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2359049 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087721 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298887 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17496 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386582 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386582 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386608 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386608 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24802725500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8508331309 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206132500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24804888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8509686826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206420500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33311056809 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33311056809 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905005000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234795498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2139800498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117391 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33314575326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33314575326 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904009500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234178998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2138188498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117427 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048530 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048545 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081414 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081510 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089898 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089923 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089898 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089923 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22802.197504 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28470.430818 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11795.176242 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -829,27 +829,27 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211595 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74877 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 245 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105819 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182823 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73510 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 245 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73514 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149151 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820223133000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94250000 0.01% 97.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384615500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38170735500 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858872734000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694715 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -888,29 +888,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175482 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5217 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192442 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5953 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.callpal::total 192344 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320343 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29154617000 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2680769000 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827037340000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |