diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 2235 insertions, 2254 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 9e5305367..94dc81bdc 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:31:55 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:47:55 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 107002000 -Exiting @ tick 1899401490000 because m5_exit instruction encountered +info: Launching CPU 1 @ 106801000 +Exiting @ tick 1896395899500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index e3ecd4b02..0c462a770 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.899401 # Number of seconds simulated -sim_ticks 1899401490000 # Number of ticks simulated -final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.896396 # Number of seconds simulated +sim_ticks 1896395899500 # Number of ticks simulated +final_tick 1896395899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124517 # Simulator instruction rate (inst/s) -host_op_rate 124517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4182952627 # Simulator tick rate (ticks/s) -host_mem_usage 300876 # Number of bytes of host memory used -host_seconds 454.08 # Real time elapsed on the host -sim_insts 56540749 # Number of instructions simulated -sim_ops 56540749 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 865216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25431680 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 268160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1206144 # Number of bytes read from this memory -system.physmem.bytes_read::total 30421696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 865216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 268160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1133376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10508736 # Number of bytes written to this memory -system.physmem.bytes_written::total 10508736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 397370 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4190 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 18846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475339 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 164199 # Number of write requests responded to by this memory -system.physmem.num_writes::total 164199 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 455520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13389312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 141181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 635013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16016464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 455520 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 141181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5532657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5532657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5532657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 455520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13389312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 141181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 635013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21549121 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397771 # number of replacements -system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use -system.l2c.total_refs 2469954 # Total number of references to valid blocks. -system.l2c.sampled_refs 433727 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.694720 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9252138000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22965.517435 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2876.895593 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7557.549613 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1417.164346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 926.790463 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.350426 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.043898 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.115319 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.021624 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.014142 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.545409 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 910711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 668584 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 173581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 117817 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1870693 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 806294 # number of Writeback hits -system.l2c.Writeback_hits::total 806294 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 126 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 295 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 154146 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 17714 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171860 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 910711 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 822730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 173581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 135531 # number of demand (read+write) hits -system.l2c.demand_hits::total 2042553 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 910711 # number of overall hits -system.l2c.overall_hits::cpu0.data 822730 # number of overall hits -system.l2c.overall_hits::cpu1.inst 173581 # number of overall hits -system.l2c.overall_hits::cpu1.data 135531 # number of overall hits -system.l2c.overall_hits::total 2042553 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13521 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 288493 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4207 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3184 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309405 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2939 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 698 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3637 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 248 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 292 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 540 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109252 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125215 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13521 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 397745 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4207 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 19147 # number of demand (read+write) misses -system.l2c.demand_misses::total 434620 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13521 # number of overall misses -system.l2c.overall_misses::cpu0.data 397745 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4207 # number of overall misses -system.l2c.overall_misses::cpu1.data 19147 # number of overall misses -system.l2c.overall_misses::total 434620 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 707237500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 15013277500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 220139500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 161535500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16102190000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2036500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2558500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 4595000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4304500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1626000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 5930500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5731732500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 836680000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6568412500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 707237500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20745010000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 220139500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 998215500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22670602500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 707237500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20745010000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 220139500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 998215500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22670602500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 924232 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 957077 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 177788 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 121001 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2180098 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 806294 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 806294 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3108 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 824 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3932 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 286 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 324 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 610 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 263398 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 33677 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 297075 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 924232 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1220475 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 177788 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 154678 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2477173 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 924232 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1220475 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 177788 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 154678 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2477173 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014629 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.301431 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.023663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.026314 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141923 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945624 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847087 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.924975 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.867133 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901235 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.885246 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.414779 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.474003 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.421493 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014629 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.325894 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.023663 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.123786 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.175450 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014629 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.325894 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.023663 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.123786 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.175450 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52306.597145 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52040.352799 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52326.955075 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 50733.511307 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52042.436289 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 692.922763 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3665.472779 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1263.403904 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17356.854839 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5568.493151 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 10982.407407 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52463.410281 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52413.706697 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52457.073833 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52161.894298 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52161.894298 # average overall miss latency +host_inst_rate 196112 # Simulator instruction rate (inst/s) +host_op_rate 196112 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6628227410 # Simulator tick rate (ticks/s) +host_mem_usage 302056 # Number of bytes of host memory used +host_seconds 286.11 # Real time elapsed on the host +sim_insts 56109524 # Number of instructions simulated +sim_ops 56109524 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 881728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24808704 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 99648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 472640 # Number of bytes read from this memory +system.physmem.bytes_read::total 28913408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 881728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 99648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7865856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7865856 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387636 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7385 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451772 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122904 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122904 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 464949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13082028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1397750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 249231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15246504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 464949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4147792 # 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number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 20390998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20390998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5719191806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5719191806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739582804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739582804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739582804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739582804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115247.179775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137665.980121 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137570.352360 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137570.352360 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115203.378531 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115203.378531 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137639.386937 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137639.386937 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137544.221141 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137544.221141 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64663068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6179.172374 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6183.711198 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11257998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11257998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559437998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3559437998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3570695996 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3570695996 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3570695996 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11186998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11186998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3558333000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3558333000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3569519998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3569519998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3569519998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3569519998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.179775 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85662.254476 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63203.378531 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63203.378531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85635.661340 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85635.661340 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8814586 # DTB read hits -system.cpu0.dtb.read_misses 32972 # DTB read misses -system.cpu0.dtb.read_acv 518 # DTB read access violations -system.cpu0.dtb.read_accesses 619797 # DTB read accesses -system.cpu0.dtb.write_hits 5858085 # DTB write hits -system.cpu0.dtb.write_misses 6892 # DTB write misses -system.cpu0.dtb.write_acv 315 # DTB write access violations -system.cpu0.dtb.write_accesses 207416 # DTB write accesses -system.cpu0.dtb.data_hits 14672671 # DTB hits -system.cpu0.dtb.data_misses 39864 # DTB misses -system.cpu0.dtb.data_acv 833 # DTB access violations -system.cpu0.dtb.data_accesses 827213 # DTB accesses -system.cpu0.itb.fetch_hits 1034325 # ITB hits -system.cpu0.itb.fetch_misses 27665 # ITB misses -system.cpu0.itb.fetch_acv 1025 # ITB acv -system.cpu0.itb.fetch_accesses 1061990 # ITB accesses +system.cpu0.dtb.read_hits 9453856 # DTB read hits +system.cpu0.dtb.read_misses 36184 # DTB read misses +system.cpu0.dtb.read_acv 571 # DTB read access violations +system.cpu0.dtb.read_accesses 675976 # DTB read accesses +system.cpu0.dtb.write_hits 6300368 # DTB write hits +system.cpu0.dtb.write_misses 8347 # DTB write misses +system.cpu0.dtb.write_acv 346 # DTB write access violations +system.cpu0.dtb.write_accesses 234133 # DTB write accesses +system.cpu0.dtb.data_hits 15754224 # DTB hits +system.cpu0.dtb.data_misses 44531 # DTB misses +system.cpu0.dtb.data_acv 917 # DTB access violations +system.cpu0.dtb.data_accesses 910109 # DTB accesses +system.cpu0.itb.fetch_hits 1108660 # ITB hits +system.cpu0.itb.fetch_misses 28136 # ITB misses +system.cpu0.itb.fetch_acv 1047 # ITB acv +system.cpu0.itb.fetch_accesses 1136796 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,279 +483,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 105407779 # number of cpu cycles simulated +system.cpu0.numCycles 111705884 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 12543533 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 10518625 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 389841 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9001573 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5310644 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13423445 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11229595 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 405618 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9732141 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5644182 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 819125 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 58295 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 26579965 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63634622 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12543533 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6129769 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12006508 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1822886 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32559683 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31957 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 177706 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 213013 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 154 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7876403 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 267953 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 72741022 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.874811 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.212644 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 889528 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 35792 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28347650 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 67883922 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13423445 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6533710 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12779049 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1882893 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34959873 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 30735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 200156 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 304542 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 145 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8317299 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 264993 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 77847394 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.872013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.211541 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 60734514 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 798536 1.10% 84.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1573590 2.16% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 701435 0.96% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2536566 3.49% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 541598 0.74% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 587478 0.81% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 932961 1.28% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4334344 5.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 65068345 83.58% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 840291 1.08% 84.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1663244 2.14% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 773630 0.99% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2654406 3.41% 91.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 587924 0.76% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 633021 0.81% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 971381 1.25% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4655152 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 72741022 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.119000 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.603699 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27434990 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 32338165 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10959738 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 873036 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1135092 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 524168 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 38246 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62454506 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 104596 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1135092 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28444580 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11348794 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17719135 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10252710 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3840709 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59087115 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6759 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 385226 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1425299 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39461950 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71535536 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71092330 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 443206 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34168968 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5292982 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1501174 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 229517 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10778320 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9311808 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6175617 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139122 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 734045 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52101492 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1888432 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 50847383 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 113537 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6290735 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3199038 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1282649 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 72741022 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.699019 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.352112 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77847394 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120168 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.607702 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29292805 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34750406 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11695757 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 922620 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1185805 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 575553 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 39816 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 66717094 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 118720 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1185805 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30365496 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12492089 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18756431 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10933791 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4113780 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 63191653 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6630 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 474971 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1473898 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 42180100 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 76536527 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 76096983 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 439544 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36808161 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5371931 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1596682 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238140 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11595704 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9967009 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6589337 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1245862 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 818929 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 55970736 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2008418 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54697537 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 108647 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6579388 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3235320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1364468 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77847394 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.702625 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.358580 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 50396766 69.28% 69.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9972815 13.71% 82.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4663131 6.41% 89.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3055348 4.20% 93.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2346789 3.23% 96.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1299072 1.79% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 640768 0.88% 99.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 275526 0.38% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 90807 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53933184 69.28% 69.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10617760 13.64% 82.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4942911 6.35% 89.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3320001 4.26% 93.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2532609 3.25% 96.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1408678 1.81% 98.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 686959 0.88% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 303964 0.39% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 101328 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 72741022 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77847394 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 76308 11.21% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 321562 47.25% 58.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 282678 41.54% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 87681 11.80% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 349168 46.97% 58.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 306477 41.23% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3304 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34794736 68.43% 68.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54066 0.11% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15533 0.03% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1651 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9216611 18.13% 86.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5928101 11.66% 98.36% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 833381 1.64% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3778 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37484034 68.53% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60241 0.11% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16826 0.03% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9867065 18.04% 86.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6373328 11.65% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 890382 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 50847383 # Type of FU issued -system.cpu0.iq.rate 0.482387 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 680548 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013384 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 174615866 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59997059 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 49635166 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 614007 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 294188 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 289709 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51201778 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 322849 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 529914 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54697537 # Type of FU issued +system.cpu0.iq.rate 0.489657 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 743326 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013590 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 187461216 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 64264846 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53535096 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 633224 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 306465 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 298013 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55105300 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 331785 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 567631 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1228237 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2717 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10847 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 496354 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1269870 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3726 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13071 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496722 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 15126 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 162620 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18808 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 143577 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1135092 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7799066 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 574299 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57208008 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 766721 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9311808 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6175617 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1662895 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 472481 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 9295 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10847 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 216142 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 364728 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 580870 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50321201 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8875076 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 526182 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1185805 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8725439 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 608869 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61441844 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 619329 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9967009 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6589337 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1767664 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 482033 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 12133 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13071 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 215254 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 393579 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 608833 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54218225 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9516523 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 479311 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3218084 # number of nop insts executed -system.cpu0.iew.exec_refs 14754207 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7980527 # Number of branches executed -system.cpu0.iew.exec_stores 5879131 # Number of stores executed -system.cpu0.iew.exec_rate 0.477396 # Inst execution rate -system.cpu0.iew.wb_sent 50024045 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 49924875 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24623982 # num instructions producing a value -system.cpu0.iew.wb_consumers 33198875 # num instructions consuming a value +system.cpu0.iew.exec_nop 3462690 # number of nop insts executed +system.cpu0.iew.exec_refs 15839640 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8639850 # Number of branches executed +system.cpu0.iew.exec_stores 6323117 # Number of stores executed +system.cpu0.iew.exec_rate 0.485366 # Inst execution rate +system.cpu0.iew.wb_sent 53937806 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53833109 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26624302 # num instructions producing a value +system.cpu0.iew.wb_consumers 35973761 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.473636 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.741711 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.481918 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.740103 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 50284711 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 50284711 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6832336 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 605783 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 542146 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 71605930 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.702242 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.623363 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 54183968 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 54183968 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 7167159 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 643950 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 567683 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76661589 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.706794 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.627118 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 52797293 73.73% 73.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7885539 11.01% 84.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4166098 5.82% 90.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2329305 3.25% 93.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1331723 1.86% 95.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575927 0.80% 96.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 415417 0.58% 97.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 456992 0.64% 97.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1647636 2.30% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56437400 73.62% 73.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8432395 11.00% 84.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4492859 5.86% 90.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2495159 3.25% 93.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1450592 1.89% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 646072 0.84% 96.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 460772 0.60% 97.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 487702 0.64% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1758638 2.29% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 71605930 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50284711 # Number of instructions committed -system.cpu0.commit.committedOps 50284711 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 76661589 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 54183968 # Number of instructions committed +system.cpu0.commit.committedOps 54183968 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13762834 # Number of memory references committed -system.cpu0.commit.loads 8083571 # Number of loads committed -system.cpu0.commit.membars 205088 # Number of memory barriers committed -system.cpu0.commit.branches 7564309 # Number of branches committed -system.cpu0.commit.fp_insts 287246 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46527621 # Number of committed integer instructions. -system.cpu0.commit.function_calls 644133 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1647636 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14789754 # Number of memory references committed +system.cpu0.commit.loads 8697139 # Number of loads committed +system.cpu0.commit.membars 219715 # Number of memory barriers committed +system.cpu0.commit.branches 8176675 # Number of branches committed +system.cpu0.commit.fp_insts 295518 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 50137398 # Number of committed integer instructions. +system.cpu0.commit.function_calls 709743 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1758638 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126892294 # The number of ROB reads -system.cpu0.rob.rob_writes 115369853 # The number of ROB writes -system.cpu0.timesIdled 1161435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32666757 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693390286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47376653 # Number of Instructions Simulated -system.cpu0.committedOps 47376653 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47376653 # Number of Instructions Simulated -system.cpu0.cpi 2.224889 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.224889 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.449461 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.449461 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65983871 # number of integer regfile reads -system.cpu0.int_regfile_writes 36054560 # number of integer regfile writes -system.cpu0.fp_regfile_reads 141566 # number of floating regfile reads -system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads -system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes +system.cpu0.rob.rob_reads 136054419 # The number of ROB reads +system.cpu0.rob.rob_writes 123888625 # The number of ROB writes +system.cpu0.timesIdled 1249831 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33858490 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3681079567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 51051860 # Number of Instructions Simulated +system.cpu0.committedOps 51051860 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 51051860 # Number of Instructions Simulated +system.cpu0.cpi 2.188086 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.188086 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.457020 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.457020 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71111535 # number of integer regfile reads +system.cpu0.int_regfile_writes 38857328 # number of integer regfile writes +system.cpu0.fp_regfile_reads 146185 # number of floating regfile reads +system.cpu0.fp_regfile_writes 148692 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1886112 # number of misc regfile reads +system.cpu0.misc_regfile_writes 899559 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -787,247 +787,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 923652 # number of replacements -system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use -system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.006511 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996106 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996106 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6902434 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6902434 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6902434 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6902434 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6902434 # number of overall hits -system.cpu0.icache.overall_hits::total 6902434 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 973969 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 973969 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 973969 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 973969 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 973969 # number of overall misses -system.cpu0.icache.overall_misses::total 973969 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14544794497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14544794497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14544794497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14544794497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14544794497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14544794497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7876403 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7876403 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7876403 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7876403 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.123657 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.123657 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.123657 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14933.529195 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14933.529195 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14933.529195 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked +system.cpu0.icache.replacements 991395 # number of replacements +system.cpu0.icache.tagsinuse 510.024196 # Cycle average of tags in use +system.cpu0.icache.total_refs 7272203 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 991905 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.331552 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23165696000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.024196 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996141 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996141 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 7272203 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7272203 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7272203 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7272203 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7272203 # number of overall hits +system.cpu0.icache.overall_hits::total 7272203 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1045096 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1045096 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1045096 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1045096 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1045096 # number of overall misses +system.cpu0.icache.overall_misses::total 1045096 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15554108994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 15554108994 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 15554108994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 15554108994 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 15554108994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 15554108994 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8317299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8317299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8317299 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8317299 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8317299 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8317299 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125653 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125653 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125653 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125653 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125653 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125653 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14882.947590 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14882.947590 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14882.947590 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14882.947590 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1419995 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11007.713178 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 196 # number of writebacks -system.cpu0.icache.writebacks::total 196 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 49660 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 49660 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 924309 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 924309 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 924309 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 924309 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 924309 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 924309 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11020233999 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11020233999 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11020233999 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.117352 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.117352 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.117352 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11922.673044 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 253 # number of writebacks +system.cpu0.icache.writebacks::total 253 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53062 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53062 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 53062 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53062 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 53062 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53062 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 992034 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 992034 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 992034 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 992034 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 992034 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 992034 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11805368995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11805368995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11805368995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11805368995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11805368995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11805368995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119274 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.119274 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.119274 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11900.165715 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1225027 # number of replacements -system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10607012 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1225539 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.654977 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19420000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 491.225534 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.959425 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.959425 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6460129 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6460129 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3759204 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3759204 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177511 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177511 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 200041 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 200041 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10219333 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10219333 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10219333 # number of overall hits -system.cpu0.dcache.overall_hits::total 10219333 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1549115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1549115 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1704606 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1704606 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20750 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20750 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2030 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2030 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3253721 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3253721 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3253721 # number of overall misses -system.cpu0.dcache.overall_misses::total 3253721 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34776889000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34776889000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52688012248 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 52688012248 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301583000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 301583000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 24841500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 24841500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 87464901248 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 87464901248 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 87464901248 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 87464901248 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8009244 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8009244 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5463810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5463810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 198261 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 198261 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 202071 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 202071 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13473054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13473054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.193416 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.311981 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104660 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.010046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.241498 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.241498 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22449.520533 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30909.202624 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14534.120482 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12237.192118 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26881.500057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26881.500057 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8893.625908 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 1352160 # number of replacements +system.cpu0.dcache.tagsinuse 506.886378 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11309312 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1352672 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.360720 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 19277000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 506.886378 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990012 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990012 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6911324 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6911324 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3997215 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3997215 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 183850 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 183850 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 210761 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 210761 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10908539 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10908539 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10908539 # number of overall hits +system.cpu0.dcache.overall_hits::total 10908539 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1709932 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1709932 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1869031 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1869031 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22271 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22271 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 641 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 641 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3578963 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3578963 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3578963 # number of overall misses +system.cpu0.dcache.overall_misses::total 3578963 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36329127500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36329127500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 56639435392 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 56639435392 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326225500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 326225500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5918000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5918000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 92968562892 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 92968562892 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 92968562892 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 92968562892 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8621256 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8621256 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5866246 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5866246 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 206121 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 206121 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211402 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 211402 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14487502 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14487502 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14487502 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14487502 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198339 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.198339 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318608 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.318608 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.108048 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.108048 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247038 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.247038 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247038 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.247038 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21245.948669 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21245.948669 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30304.171195 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30304.171195 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.995151 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.995151 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9232.449298 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9232.449298 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25976.396764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25976.396764 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 790531306 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 99401 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7952.951238 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 689568 # number of writebacks -system.cpu0.dcache.writebacks::total 689568 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 597617 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 597617 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436241 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1436241 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4277 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4277 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2033858 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2033858 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2033858 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2033858 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 951498 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 951498 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 268365 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 268365 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16473 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16473 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2030 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2030 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1219863 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1219863 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1219863 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1219863 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22991247500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22991247500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7905411394 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7905411394 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183295500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183295500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18744000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18744000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30896658894 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30896658894 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30896658894 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30896658894 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 635008500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 635008500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1065246998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049117 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.010046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090541 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090541 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24163.211588 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29457.684102 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11127.026043 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9233.497537 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 805259 # number of writebacks +system.cpu0.dcache.writebacks::total 805259 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 661851 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 661851 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1575507 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1575507 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5029 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5029 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2237358 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2237358 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2237358 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2237358 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1048081 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1048081 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 293524 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 293524 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17242 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17242 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1341605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1341605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1341605 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1341605 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23566810500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23566810500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8456840306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8456840306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195574000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195574000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3991500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3991500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32023650806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 32023650806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32023650806 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 32023650806 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 917307000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 917307000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253595498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253595498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2170902498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2170902498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121569 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121569 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050036 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050036 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083650 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083650 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092604 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092604 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22485.676680 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22485.676680 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28811.409990 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28811.409990 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11342.883656 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.883656 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6236.718750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6236.718750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1039,22 +1039,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1967803 # DTB read hits -system.cpu1.dtb.read_misses 13979 # DTB read misses -system.cpu1.dtb.read_acv 50 # DTB read access violations -system.cpu1.dtb.read_accesses 344857 # DTB read accesses -system.cpu1.dtb.write_hits 1156959 # DTB write hits -system.cpu1.dtb.write_misses 3426 # DTB write misses -system.cpu1.dtb.write_acv 86 # DTB write access violations -system.cpu1.dtb.write_accesses 133134 # DTB write accesses -system.cpu1.dtb.data_hits 3124762 # DTB hits -system.cpu1.dtb.data_misses 17405 # DTB misses -system.cpu1.dtb.data_acv 136 # DTB access violations -system.cpu1.dtb.data_accesses 477991 # DTB accesses -system.cpu1.itb.fetch_hits 421916 # ITB hits -system.cpu1.itb.fetch_misses 9109 # ITB misses -system.cpu1.itb.fetch_acv 356 # ITB acv -system.cpu1.itb.fetch_accesses 431025 # ITB accesses +system.cpu1.dtb.read_hits 1211336 # DTB read hits +system.cpu1.dtb.read_misses 9865 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 283619 # DTB read accesses +system.cpu1.dtb.write_hits 674221 # DTB write hits +system.cpu1.dtb.write_misses 1908 # DTB write misses +system.cpu1.dtb.write_acv 40 # DTB write access violations +system.cpu1.dtb.write_accesses 107232 # DTB write accesses +system.cpu1.dtb.data_hits 1885557 # DTB hits +system.cpu1.dtb.data_misses 11773 # DTB misses +system.cpu1.dtb.data_acv 46 # DTB access violations +system.cpu1.dtb.data_accesses 390851 # DTB accesses +system.cpu1.itb.fetch_hits 332989 # ITB hits +system.cpu1.itb.fetch_misses 6158 # ITB misses +system.cpu1.itb.fetch_acv 143 # ITB acv +system.cpu1.itb.fetch_accesses 339147 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1067,520 +1067,520 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16642884 # number of cpu cycles simulated +system.cpu1.numCycles 8872891 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 2705570 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2183133 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 103658 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1600081 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 956693 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1582523 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1301899 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 53959 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 749480 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 495600 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 205000 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 11458 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 5302876 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13307049 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2705570 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1161693 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2441613 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 501707 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6356468 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 74919 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 150190 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1679881 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 61959 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14687135 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.906034 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.268778 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 108561 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5012 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3100077 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 7469135 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1582523 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 604161 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1348473 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 293042 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3524434 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 23987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 56676 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47433 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 951392 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 34043 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 8293149 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.900639 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.276932 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12245522 83.38% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 134693 0.92% 84.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 301692 2.05% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 210681 1.43% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 386391 2.63% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 150965 1.03% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 158556 1.08% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 103876 0.71% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 994759 6.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 6944676 83.74% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 71085 0.86% 84.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 161786 1.95% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 117935 1.42% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 195029 2.35% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 79896 0.96% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 91030 1.10% 92.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 58799 0.71% 93.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 572913 6.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14687135 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.162566 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.799564 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5465828 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6500437 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2284956 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 109363 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 326550 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 135471 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 8440 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12979059 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22096 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 326550 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5675549 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 1529515 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4345584 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2134958 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 674977 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 12129764 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 166 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 128005 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 129891 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 8170378 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 14771785 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 14690250 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 81535 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6624020 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1546358 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 396407 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 33332 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2062542 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2114945 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1244442 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 252990 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 158890 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 10689942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 428775 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10217833 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 32007 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1868726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1009548 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 314972 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14687135 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.695700 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.377163 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 8293149 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.178355 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.841793 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3156648 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 3626684 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1266182 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 55854 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 187780 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 69682 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4376 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 7275177 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13096 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 187780 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3279437 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 303001 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 2955129 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1188563 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 379237 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 6712088 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 36332 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 73621 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 4503320 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 8147567 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 8100022 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 47545 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3660294 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 843026 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 283944 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 19782 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1166048 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1294582 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 736122 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 125256 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 86989 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 5902743 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 293921 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 5640439 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22605 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1087589 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 606184 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 224688 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 8293149 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.680132 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.353961 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10355359 70.51% 70.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1845686 12.57% 83.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 877719 5.98% 89.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 637269 4.34% 93.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 497555 3.39% 96.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 237687 1.62% 98.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 141618 0.96% 99.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 77397 0.53% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 16845 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 5841725 70.44% 70.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1091278 13.16% 83.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 496152 5.98% 89.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 349787 4.22% 93.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 258149 3.11% 96.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 126242 1.52% 98.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 71640 0.86% 99.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 51558 0.62% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 6618 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14687135 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 8293149 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 13419 6.74% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 108426 54.48% 61.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 77176 38.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3067 2.40% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 73236 57.36% 59.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 51382 40.24% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3982 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6701010 65.58% 65.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17534 0.17% 65.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10648 0.10% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2057377 20.14% 86.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1183005 11.58% 97.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 242286 2.37% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3484656 61.78% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10025 0.18% 62.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8917 0.16% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1261676 22.37% 84.58% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 692210 12.27% 96.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 177678 3.15% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10217833 # Type of FU issued -system.cpu1.iq.rate 0.613946 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 199021 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019478 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 35235052 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 12931686 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9924010 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 118777 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 58514 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 57042 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10351384 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 61488 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 101325 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 5640439 # Type of FU issued +system.cpu1.iq.rate 0.635693 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 127685 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.022637 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 19654183 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 7250568 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 5466934 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 70134 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 35039 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 33778 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 5728452 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 36154 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 64737 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 375645 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 853 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2882 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 159755 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 237812 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 428 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1426 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 105246 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 4092 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 23338 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 373 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 23964 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 326550 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1215619 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 41484 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 11650788 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 153391 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2114945 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1244442 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 389086 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9620 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6598 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2882 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 57079 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 98765 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 155844 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10093188 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1987752 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 124645 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 187780 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 210633 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 9248 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 6437285 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 88203 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1294582 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 736122 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 274301 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3887 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1426 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 25150 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 66283 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 91433 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 5579037 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1224301 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 61402 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 532071 # number of nop insts executed -system.cpu1.iew.exec_refs 3152815 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1559516 # Number of branches executed -system.cpu1.iew.exec_stores 1165063 # Number of stores executed -system.cpu1.iew.exec_rate 0.606457 # Inst execution rate -system.cpu1.iew.wb_sent 10020459 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9981052 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4916782 # num instructions producing a value -system.cpu1.iew.wb_consumers 6843934 # num instructions consuming a value +system.cpu1.iew.exec_nop 240621 # number of nop insts executed +system.cpu1.iew.exec_refs 1903575 # number of memory reference insts executed +system.cpu1.iew.exec_branches 816845 # Number of branches executed +system.cpu1.iew.exec_stores 679274 # Number of stores executed +system.cpu1.iew.exec_rate 0.628773 # Inst execution rate +system.cpu1.iew.wb_sent 5526738 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 5500712 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2655801 # num instructions producing a value +system.cpu1.iew.wb_consumers 3693565 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.599719 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.718415 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.619946 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.719035 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 9615778 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 9615778 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1958417 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 113803 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 145209 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14360585 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.669595 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.592350 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5260797 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 5260797 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1110508 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 69233 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 85933 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 8105369 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.649051 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.577854 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10743360 74.81% 74.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1616043 11.25% 86.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 700215 4.88% 90.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 397241 2.77% 93.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 279128 1.94% 95.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 129549 0.90% 96.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 113540 0.79% 97.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 89987 0.63% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 291522 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6083727 75.06% 75.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 977563 12.06% 87.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 351716 4.34% 91.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 209459 2.58% 94.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 128681 1.59% 95.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 67803 0.84% 96.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 72265 0.89% 97.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 49144 0.61% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 165011 2.04% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14360585 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9615778 # Number of instructions committed -system.cpu1.commit.committedOps 9615778 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 8105369 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 5260797 # Number of instructions committed +system.cpu1.commit.committedOps 5260797 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2823987 # Number of memory references committed -system.cpu1.commit.loads 1739300 # Number of loads committed -system.cpu1.commit.membars 35653 # Number of memory barriers committed -system.cpu1.commit.branches 1422938 # Number of branches committed -system.cpu1.commit.fp_insts 55483 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8948473 # Number of committed integer instructions. -system.cpu1.commit.function_calls 153476 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 291522 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1687646 # Number of memory references committed +system.cpu1.commit.loads 1056770 # Number of loads committed +system.cpu1.commit.membars 18284 # Number of memory barriers committed +system.cpu1.commit.branches 746127 # Number of branches committed +system.cpu1.commit.fp_insts 32538 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 4917553 # Number of committed integer instructions. +system.cpu1.commit.function_calls 83297 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 165011 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25542136 # The number of ROB reads -system.cpu1.rob.rob_writes 23473924 # The number of ROB writes -system.cpu1.timesIdled 165614 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1955749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3781507254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9164096 # Number of Instructions Simulated -system.cpu1.committedOps 9164096 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 9164096 # Number of Instructions Simulated -system.cpu1.cpi 1.816097 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.816097 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550631 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550631 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13179031 # number of integer regfile reads -system.cpu1.int_regfile_writes 7231354 # number of integer regfile writes -system.cpu1.fp_regfile_reads 33888 # number of floating regfile reads -system.cpu1.fp_regfile_writes 32897 # number of floating regfile writes -system.cpu1.misc_regfile_reads 392068 # number of misc regfile reads -system.cpu1.misc_regfile_writes 179438 # number of misc regfile writes -system.cpu1.icache.replacements 177236 # number of replacements -system.cpu1.icache.tagsinuse 505.128292 # Cycle average of tags in use -system.cpu1.icache.total_refs 1491482 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 177747 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.391039 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 108399350000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 505.128292 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.986579 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.986579 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1491482 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1491482 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1491482 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1491482 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1491482 # number of overall hits -system.cpu1.icache.overall_hits::total 1491482 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 188398 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 188398 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 188398 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 188398 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 188398 # number of overall misses -system.cpu1.icache.overall_misses::total 188398 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2886679000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2886679000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2886679000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2886679000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2886679000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2886679000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1679880 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1679880 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1679880 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1679880 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.112150 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.112150 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.112150 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15322.238028 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15322.238028 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15322.238028 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked +system.cpu1.rob.rob_reads 14229924 # The number of ROB reads +system.cpu1.rob.rob_writes 12929135 # The number of ROB writes +system.cpu1.timesIdled 74630 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 579742 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3783284242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5057664 # Number of Instructions Simulated +system.cpu1.committedOps 5057664 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 5057664 # Number of Instructions Simulated +system.cpu1.cpi 1.754346 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.754346 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.570013 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.570013 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 7235777 # number of integer regfile reads +system.cpu1.int_regfile_writes 3986410 # number of integer regfile writes +system.cpu1.fp_regfile_reads 21879 # number of floating regfile reads +system.cpu1.fp_regfile_writes 20613 # number of floating regfile writes +system.cpu1.misc_regfile_reads 262487 # number of misc regfile reads +system.cpu1.misc_regfile_writes 123180 # number of misc regfile writes +system.cpu1.icache.replacements 103776 # number of replacements +system.cpu1.icache.tagsinuse 452.422972 # Cycle average of tags in use +system.cpu1.icache.total_refs 841895 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 104287 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.072866 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1873827117000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 452.422972 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.883639 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.883639 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 841895 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 841895 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 841895 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 841895 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 841895 # number of overall hits +system.cpu1.icache.overall_hits::total 841895 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 109497 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 109497 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 109497 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 109497 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 109497 # number of overall misses +system.cpu1.icache.overall_misses::total 109497 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1632285999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1632285999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1632285999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1632285999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1632285999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1632285999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 951392 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 951392 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 951392 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 951392 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 951392 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 951392 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115091 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.115091 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115091 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.115091 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115091 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.115091 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14907.129867 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14907.129867 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14907.129867 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14907.129867 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 108999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7266.600000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 52 # number of writebacks -system.cpu1.icache.writebacks::total 52 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 10580 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 10580 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 177818 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 177818 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 177818 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 177818 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 177818 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 177818 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2188079500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2188079500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2188079500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105852 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.105852 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.105852 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12305.163144 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 39 # number of writebacks +system.cpu1.icache.writebacks::total 39 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5150 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 5150 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1240890499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1240890499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1240890499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1240890499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.109678 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.109678 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.109678 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11891.961427 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 156190 # number of replacements -system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2451996 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 156506 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 15.667105 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 42868987000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 478.738504 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.935036 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.935036 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1592507 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1592507 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 821344 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 821344 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 23925 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 23925 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 22430 # 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number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 460887 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 460887 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 460887 # number of overall misses -system.cpu1.dcache.overall_misses::total 460887 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3617978500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3617978500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7562454737 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7562454737 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50003000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 50003000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 26428500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 26428500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11180433237 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11180433237 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11180433237 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11180433237 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1821691 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1821691 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1053047 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1053047 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 27756 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 27756 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 24409 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 24409 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2874738 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2874738 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.125808 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.220031 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.138024 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081077 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.160323 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.160323 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15786.348523 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32638.570657 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13052.205690 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13354.471956 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24258.512904 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24258.512904 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked +system.cpu1.dcache.replacements 49122 # number of replacements +system.cpu1.dcache.tagsinuse 427.490507 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1549420 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 49435 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 31.342571 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1873347092000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 427.490507 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.834942 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.834942 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1023689 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1023689 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 507974 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 507974 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 14665 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 14665 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 12767 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 12767 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1531663 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1531663 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1531663 # number of overall hits +system.cpu1.dcache.overall_hits::total 1531663 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 89035 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 89035 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 104470 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 104470 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1314 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1314 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 680 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 680 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 193505 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 193505 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 193505 # number of overall misses +system.cpu1.dcache.overall_misses::total 193505 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1323211000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1323211000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3353600320 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3353600320 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 16083500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 16083500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7995500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 7995500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4676811320 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4676811320 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4676811320 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4676811320 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1112724 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1112724 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 612444 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 612444 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 15979 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 15979 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 13447 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 13447 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1725168 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1725168 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1725168 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1725168 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.080015 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.080015 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.170579 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.170579 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082233 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082233 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050569 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050569 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.112166 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.112166 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.112166 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.112166 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14861.694839 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14861.694839 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32101.084713 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32101.084713 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12240.106545 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12240.106545 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11758.088235 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11758.088235 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24168.943025 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24168.943025 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 52059498 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4983 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10447.420831 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks -system.cpu1.dcache.writebacks::total 116478 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 879 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 879 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296787 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296787 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296787 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296787 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 127049 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 127049 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37051 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 37051 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 2952 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 2952 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 1975 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 1975 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 164100 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 164100 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 164100 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 164100 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1572060500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1572060500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1129988939 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1129988939 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25904500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 25904500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 20495000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 20495000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2702049439 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2702049439 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2702049439 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2702049439 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 300850500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 300850500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 561357500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.069742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.035185 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106355 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080913 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.057083 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.057083 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12373.655046 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30498.203530 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8775.237127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10377.215190 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 27321 # number of writebacks +system.cpu1.dcache.writebacks::total 27321 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 51379 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 51379 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 87869 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 87869 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 246 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 246 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 139248 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 139248 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 139248 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 139248 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37656 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37656 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 16601 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 16601 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 674 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 674 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 54257 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 54257 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 54257 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 54257 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 431650500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 431650500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 497061484 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 497061484 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9472500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9472500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5965000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5965000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 928711984 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 928711984 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 928711984 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 928711984 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18616500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18616500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 318558500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 318558500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 337175000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 337175000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033841 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033841 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027106 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027106 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066838 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066838 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050123 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050123 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031450 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031450 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11462.993945 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11462.993945 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29941.659177 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29941.659177 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8869.382022 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8869.382022 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8850.148368 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8850.148368 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1589,166 +1589,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 189249 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 67157 40.25% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.14% 40.40% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.15% 41.55% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 121 0.07% 41.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 97397 58.38% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 166835 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 65800 49.19% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.18% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 1.44% 50.81% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 121 0.09% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 65679 49.10% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 133760 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863324430000 98.10% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91299000 0.00% 98.11% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 390735500 0.02% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 47295500 0.00% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35546879500 1.87% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1899400639500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.979794 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6349 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 201504 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72229 40.68% 40.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.13% 40.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1919 1.08% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 103147 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 177538 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70862 49.25% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.16% 49.42% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1919 1.33% 50.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 70856 49.25% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 143880 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1857798011000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91384000 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 387547000 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 3124500 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38114922000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1896394988500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981074 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.801750 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed -system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed -system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed -system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed -system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 209 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.686942 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810418 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed +system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 228 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 205 0.12% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3713 2.12% 2.24% # number of callpals executed -system.cpu0.kern.callpal::tbi 45 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 159757 91.11% 93.38% # number of callpals executed -system.cpu0.kern.callpal::rdps 6320 3.60% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rti 4796 2.74% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 348 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 134 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 175342 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches +system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3893 2.09% 2.15% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpipl 170509 91.52% 93.70% # number of callpals executed +system.cpu0.kern.callpal::rdps 6338 3.40% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.11% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed +system.cpu0.kern.callpal::rti 4866 2.61% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 386 0.21% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 186310 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7415 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1346 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1161 -system.cpu0.kern.mode_good::user 1162 +system.cpu0.kern.mode_good::kernel 1345 +system.cpu0.kern.mode_good::user 1346 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181389 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.278972 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307157 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1894436238500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1958742000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3714 # number of times the context was actually changed +system.cpu0.kern.swap_context 3894 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 4.71% 41.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 205 0.50% 42.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 23643 57.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 40791 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 15002 46.99% 46.99% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 6.02% 53.01% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 205 0.64% 53.65% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 14797 46.35% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 31925 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870054566000 98.47% 98.47% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 345480500 0.02% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 82493000 0.00% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28594480500 1.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1899077020000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998669 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2266 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 36241 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9521 32.62% 32.62% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1918 6.57% 39.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.36% 39.54% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17647 60.46% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 29190 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9511 45.42% 45.42% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1918 9.16% 54.58% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.50% 55.08% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9407 44.92% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20940 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870201149000 98.64% 98.64% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 342845500 0.02% 98.65% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 41642500 0.00% 98.66% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25494039500 1.34% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1896079676500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998950 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.782648 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed -system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed -system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed -system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed -system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed -system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed -system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 117 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.533065 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.717369 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed +system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed +system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 98 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 121 0.29% 0.29% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed -system.cpu1.kern.callpal::swpctx 734 1.74% 2.03% # number of callpals executed -system.cpu1.kern.callpal::tbi 9 0.02% 2.05% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 2.07% # number of callpals executed -system.cpu1.kern.callpal::swpipl 35949 85.20% 87.27% # number of callpals executed -system.cpu1.kern.callpal::rdps 2433 5.77% 93.03% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.03% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.05% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.05% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.06% # number of callpals executed -system.cpu1.kern.callpal::rti 2715 6.43% 99.49% # number of callpals executed -system.cpu1.kern.callpal::callsys 167 0.40% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 47 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 334 1.11% 1.14% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.15% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.17% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24745 82.19% 83.36% # number of callpals executed +system.cpu1.kern.callpal::rdps 2407 7.99% 91.36% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.36% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.37% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed +system.cpu1.kern.callpal::rti 2422 8.04% 99.43% # number of callpals executed +system.cpu1.kern.callpal::callsys 129 0.43% 99.86% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 42196 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1189 # number of protection mode switches -system.cpu1.kern.mode_switch::user 578 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2262 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 747 -system.cpu1.kern.mode_good::user 578 -system.cpu1.kern.mode_good::idle 169 -system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 30107 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 710 # number of protection mode switches +system.cpu1.kern.mode_switch::user 392 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 420 +system.cpu1.kern.mode_good::user 392 +system.cpu1.kern.mode_good::idle 28 +system.cpu1.kern.mode_switch_good::kernel 0.591549 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370812 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 735 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.013672 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.266667 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1688462500 0.09% 0.09% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 719657500 0.04% 0.13% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893332404000 99.87% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 335 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f3bacddca..3b2f5c4a1 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:16:04 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:47:37 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858684403000 because m5_exit instruction encountered +Exiting @ tick 1858879782500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index d7b6a1ccb..90f62bf97 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,146 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858684 # Number of seconds simulated -sim_ticks 1858684403000 # Number of ticks simulated -final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.858880 # Number of seconds simulated +sim_ticks 1858879782500 # Number of ticks simulated +final_tick 1858879782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125153 # Simulator instruction rate (inst/s) -host_op_rate 125153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4381630644 # Simulator tick rate (ticks/s) -host_mem_usage 297044 # Number of bytes of host memory used -host_seconds 424.20 # Real time elapsed on the host -sim_insts 53089851 # Number of instructions simulated -sim_ops 53089851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 1082432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 26112576 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652544 # Number of bytes read from this memory -system.physmem.bytes_read::total 29847552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1082432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1082432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10195968 # Number of bytes written to this memory -system.physmem.bytes_written::total 10195968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16913 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 408009 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 466368 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 159312 # Number of write requests responded to by this memory -system.physmem.num_writes::total 159312 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 582365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14048956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1427108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16058429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 582365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 582365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5485583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5485583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5485583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 582365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14048956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1427108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21544012 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 391653 # number of replacements -system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use -system.l2c.total_refs 2427420 # Total number of references to valid blocks. -system.l2c.sampled_refs 424662 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.716122 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5620155000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22664.143946 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4133.885317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8135.052193 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.345827 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.063078 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.124131 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.533037 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 1009333 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 810762 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1820095 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 834721 # number of Writeback hits -system.l2c.Writeback_hits::total 834721 # number of Writeback hits +host_inst_rate 196297 # Simulator instruction rate (inst/s) +host_op_rate 196297 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6876664069 # Simulator tick rate (ticks/s) +host_mem_usage 298988 # Number of bytes of host memory used +host_seconds 270.32 # Real time elapsed on the host +sim_insts 53062487 # Number of instructions simulated +sim_ops 53062487 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24884032 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28505408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388813 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445397 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 521329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13386574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1426821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15334724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 521329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 521329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 521329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13386574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1426821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19382788 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 338457 # number of replacements +system.l2c.tagsinuse 65351.732427 # Cycle average of tags in use +system.l2c.total_refs 2557615 # Total number of references to valid blocks. +system.l2c.sampled_refs 403631 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.336518 # Average number of references to valid blocks. +system.l2c.warmup_cycle 4816079000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53832.150010 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5352.172668 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6167.409749 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.821413 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.081668 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094107 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997188 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1006386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 826813 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1833199 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 841169 # number of Writeback hits +system.l2c.Writeback_hits::total 841169 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 183748 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183748 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 1009333 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 994510 # number of demand (read+write) hits -system.l2c.demand_hits::total 2003843 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 1009333 # number of overall hits -system.l2c.overall_hits::cpu.data 994510 # number of overall hits -system.l2c.overall_hits::total 2003843 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 16915 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 291468 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308383 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 32 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 32 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 117029 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117029 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 16915 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 408497 # number of demand (read+write) misses -system.l2c.demand_misses::total 425412 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 16915 # 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number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 884741000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 21306631500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22191372500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 1026248 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1102230 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2128478 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 834721 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 834721 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 47 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 47 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 300777 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300777 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1026248 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1403007 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2429255 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1026248 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1403007 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.144884 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.680851 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.389089 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.175120 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.175120 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52055.178139 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 13296.875000 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52452.302421 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52164.425310 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52164.425310 # average overall miss latency +system.l2c.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 185491 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185491 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1006386 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1012304 # number of demand (read+write) hits +system.l2c.demand_hits::total 2018690 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 1006386 # number of overall hits +system.l2c.overall_hits::cpu.data 1012304 # number of overall hits +system.l2c.overall_hits::total 2018690 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 273879 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289023 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 27 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 115423 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115423 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 15144 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 389302 # number of demand (read+write) misses +system.l2c.demand_misses::total 404446 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 15144 # number of overall misses +system.l2c.overall_misses::cpu.data 389302 # number of overall misses +system.l2c.overall_misses::total 404446 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 792218000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14246173000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15038391000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 322000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 322000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6056487000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6056487000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 792218000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20302660000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21094878000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 792218000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20302660000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21094878000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1021530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1100692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2122222 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 841169 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 841169 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 42 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 42 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 300914 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300914 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 1021530 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1401606 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2423136 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1021530 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1401606 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2423136 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014825 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.248824 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.136189 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.642857 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.642857 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383575 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383575 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014825 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.277754 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166910 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014825 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.277754 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166910 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52312.334918 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52016.302820 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52031.814077 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11925.925926 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 11925.925926 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52472.098282 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52472.098282 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52157.464779 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52157.464779 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,80 +145,72 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117800 # number of writebacks -system.l2c.writebacks::total 117800 # number of writebacks +system.l2c.writebacks::writebacks 76064 # number of writebacks +system.l2c.writebacks::total 76064 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.inst 16914 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 291468 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 308382 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 117029 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 117029 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16914 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 408497 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 425411 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16914 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 408497 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 425411 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 677644000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 11668187500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 12345831500 # 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number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 16382770000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17060414000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809666500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 809666500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114488498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1114488498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.144884 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.680851 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.389089 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.175120 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.175120 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40034.215681 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41968.750000 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40285.591605 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 273879 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289022 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 115423 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 115423 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 389302 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 404445 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 389302 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 404445 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 606782500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10958767000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11565549500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1142000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1142000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4653345000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4653345000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 606782500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15612112000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16218894500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 606782500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15612112000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16218894500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810071000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 810071000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114787998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1114787998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924858998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1924858998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248824 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.136188 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.642857 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.642857 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383575 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383575 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166910 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166910 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40070.164432 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40013.170050 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.156210 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42296.296296 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42296.296296 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40315.578351 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40315.578351 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -231,14 +219,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.266745 # Cycle average of tags in use +system.iocache.tagsinuse 1.268378 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708341003000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.266745 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079172 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079172 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338896000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.268378 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079274 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079274 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -249,12 +237,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721838806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721838806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741776804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741776804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741776804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741776804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5721900806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5721900806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5741838804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5741838804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5741838804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5741838804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -273,17 +261,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137703.090248 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137609.989311 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137609.989311 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.582355 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137704.582355 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137611.475231 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137611.475231 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64649068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6171.159603 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -299,12 +287,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560986994 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3560986994 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571928992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571928992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561047996 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3561047996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3571989994 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3571989994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3571989994 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3571989994 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -315,12 +303,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85699.532971 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85701.001059 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85701.001059 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -338,22 +326,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10017178 # DTB read hits -system.cpu.dtb.read_misses 45828 # DTB read misses -system.cpu.dtb.read_acv 561 # DTB read access violations -system.cpu.dtb.read_accesses 954843 # DTB read accesses -system.cpu.dtb.write_hits 6639084 # DTB write hits -system.cpu.dtb.write_misses 10800 # DTB write misses -system.cpu.dtb.write_acv 415 # DTB write access violations -system.cpu.dtb.write_accesses 340295 # DTB write accesses -system.cpu.dtb.data_hits 16656262 # DTB hits -system.cpu.dtb.data_misses 56628 # DTB misses -system.cpu.dtb.data_acv 976 # DTB access violations -system.cpu.dtb.data_accesses 1295138 # DTB accesses -system.cpu.itb.fetch_hits 1345400 # ITB hits -system.cpu.itb.fetch_misses 36691 # ITB misses -system.cpu.itb.fetch_acv 1385 # ITB acv -system.cpu.itb.fetch_accesses 1382091 # ITB accesses +system.cpu.dtb.read_hits 9957395 # DTB read hits +system.cpu.dtb.read_misses 44300 # DTB read misses +system.cpu.dtb.read_acv 564 # DTB read access violations +system.cpu.dtb.read_accesses 948872 # DTB read accesses +system.cpu.dtb.write_hits 6634412 # DTB write hits +system.cpu.dtb.write_misses 10394 # DTB write misses +system.cpu.dtb.write_acv 384 # DTB write access violations +system.cpu.dtb.write_accesses 338929 # DTB write accesses +system.cpu.dtb.data_hits 16591807 # DTB hits +system.cpu.dtb.data_misses 54694 # DTB misses +system.cpu.dtb.data_acv 948 # DTB access violations +system.cpu.dtb.data_accesses 1287801 # DTB accesses +system.cpu.itb.fetch_hits 1332166 # ITB hits +system.cpu.itb.fetch_misses 40283 # ITB misses +system.cpu.itb.fetch_acv 1114 # ITB acv +system.cpu.itb.fetch_accesses 1372449 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -366,147 +354,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 115937106 # number of cpu cycles simulated +system.cpu.numCycles 114963877 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14171679 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11793956 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477051 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10388735 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5970315 # Number of BTB hits +system.cpu.BPredUnit.lookups 13985774 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11671873 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 444413 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10112209 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5892039 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 956584 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 68437 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29509897 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 72276663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14171679 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6926899 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13625760 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2211095 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36451359 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33988 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254368 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 318126 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9001683 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320234 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81638301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.885328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.224856 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 933191 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 42453 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29251616 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71181997 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13985774 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6825230 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13396576 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2069716 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36268090 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34293 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 258776 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 311439 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 136 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8761444 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288106 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80878220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.880113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.220739 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68012541 83.31% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 890285 1.09% 84.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1788287 2.19% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 860446 1.05% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2806697 3.44% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 613121 0.75% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 690439 0.85% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1018441 1.25% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4958044 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67481644 83.44% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 875531 1.08% 84.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1743396 2.16% 86.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 848384 1.05% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2751006 3.40% 91.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 598052 0.74% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674963 0.83% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011492 1.25% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4893752 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81638301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122236 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.623413 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30605398 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36211579 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12459009 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962410 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1399904 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 626907 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46406 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70869283 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128122 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1399904 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31751021 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12870145 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19629693 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11657858 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4329678 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 67084686 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 509202 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1545669 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44883895 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 81279618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80782275 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 497343 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38259023 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6624872 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1702108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 250876 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12154886 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10647937 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6996260 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1317222 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 890257 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59186479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2094113 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57496699 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116770 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7805626 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4020701 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1426389 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81638301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704286 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361652 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80878220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121654 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.619168 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30302953 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36036206 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12267887 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 956730 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1314443 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 612620 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43298 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69919175 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129721 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1314443 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31429322 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12715444 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19630106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11479703 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4309200 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66239771 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6813 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505927 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1528052 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44253229 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80320067 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79838854 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 481213 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38235996 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6017225 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1699905 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 247549 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12108783 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10535735 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6944708 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1299665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 826518 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58678192 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2085341 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57178934 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7323387 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3670404 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1417353 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80878220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.706976 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364710 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56549177 69.27% 69.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11085908 13.58% 82.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5246792 6.43% 89.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3470006 4.25% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2637448 3.23% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1477237 1.81% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 737523 0.90% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 327606 0.40% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 106604 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55943146 69.17% 69.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11029219 13.64% 82.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5183069 6.41% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3467547 4.29% 93.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2613614 3.23% 96.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1475312 1.82% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 724581 0.90% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331422 0.41% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 110310 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81638301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80878220 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90136 11.38% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 378271 47.76% 59.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323650 40.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90406 11.39% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 375907 47.36% 58.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 327352 41.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39231645 68.23% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61830 0.11% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39009688 68.22% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61923 0.11% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued @@ -529,116 +517,116 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10492080 18.25% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722416 11.69% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952204 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10404436 18.20% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6713568 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952795 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57496699 # Type of FU issued -system.cpu.iq.rate 0.495930 # Inst issue rate -system.cpu.iq.fu_busy_cnt 792057 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013776 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 196846794 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68765054 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56061076 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693732 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 333965 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328206 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57917538 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363937 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 590984 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57178934 # Type of FU issued +system.cpu.iq.rate 0.497364 # Inst issue rate +system.cpu.iq.fu_busy_cnt 793665 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013880 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195448703 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67761433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55894957 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 695216 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 339032 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327938 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57602239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363079 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 589978 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1535089 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3470 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13124 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604028 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1427299 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3440 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13878 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 554882 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 170629 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 151980 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1399904 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9017933 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 616152 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64867759 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 849536 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10647937 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6996260 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1840231 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 482623 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15971 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13124 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 267386 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 425155 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 692541 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56871146 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10095387 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 625553 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1314443 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8887747 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 615033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64324837 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 661005 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10535735 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6944708 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1835122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 481853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16088 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13878 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 240769 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 420658 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 661427 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56655096 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10030988 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 523837 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3587167 # number of nop insts executed -system.cpu.iew.exec_refs 16760622 # number of memory reference insts executed -system.cpu.iew.exec_branches 9006504 # Number of branches executed -system.cpu.iew.exec_stores 6665235 # Number of stores executed -system.cpu.iew.exec_rate 0.490534 # Inst execution rate -system.cpu.iew.wb_sent 56517124 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56389282 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27888094 # num instructions producing a value -system.cpu.iew.wb_consumers 37753450 # num instructions consuming a value +system.cpu.iew.exec_nop 3561304 # number of nop insts executed +system.cpu.iew.exec_refs 16691010 # number of memory reference insts executed +system.cpu.iew.exec_branches 8986521 # Number of branches executed +system.cpu.iew.exec_stores 6660022 # Number of stores executed +system.cpu.iew.exec_rate 0.492808 # Inst execution rate +system.cpu.iew.wb_sent 56341255 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56222895 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27828941 # num instructions producing a value +system.cpu.iew.wb_consumers 37695611 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.486378 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738690 # average fanout of values written-back +system.cpu.iew.wb_rate 0.489048 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738254 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56284358 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56284358 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8468547 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667724 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 643899 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80238397 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.701464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.625122 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56255888 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56255888 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 7955379 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 613263 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79563777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.707054 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.631051 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59258262 73.85% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8767408 10.93% 84.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4647312 5.79% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2573487 3.21% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1500960 1.87% 95.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 651575 0.81% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 486922 0.61% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 501150 0.62% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851321 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58612311 73.67% 73.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8734565 10.98% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4655391 5.85% 90.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2574186 3.24% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1496332 1.88% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 659939 0.83% 96.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 486345 0.61% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 472774 0.59% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1871934 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80238397 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56284358 # Number of instructions committed -system.cpu.commit.committedOps 56284358 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79563777 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56255888 # Number of instructions committed +system.cpu.commit.committedOps 56255888 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15505080 # Number of memory references committed -system.cpu.commit.loads 9112848 # Number of loads committed -system.cpu.commit.membars 227858 # Number of memory barriers committed -system.cpu.commit.branches 8462387 # Number of branches committed +system.cpu.commit.refs 15498262 # Number of memory references committed +system.cpu.commit.loads 9108436 # Number of loads committed +system.cpu.commit.membars 227920 # Number of memory barriers committed +system.cpu.commit.branches 8459857 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52122951 # Number of committed integer instructions. -system.cpu.commit.function_calls 744427 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851321 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52095164 # Number of committed integer instructions. +system.cpu.commit.function_calls 744157 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1871934 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 142888950 # The number of ROB reads -system.cpu.rob.rob_writes 130907900 # The number of ROB writes -system.cpu.timesIdled 1275123 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34298805 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3601425271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53089851 # Number of Instructions Simulated -system.cpu.committedOps 53089851 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53089851 # Number of Instructions Simulated -system.cpu.cpi 2.183790 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.183790 # CPI: Total CPI of All Threads -system.cpu.ipc 0.457919 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.457919 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74514493 # number of integer regfile reads -system.cpu.int_regfile_writes 40703979 # number of integer regfile writes -system.cpu.fp_regfile_reads 166152 # number of floating regfile reads -system.cpu.fp_regfile_writes 167434 # number of floating regfile writes -system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads -system.cpu.misc_regfile_writes 949957 # number of misc regfile writes +system.cpu.rob.rob_reads 141652037 # The number of ROB reads +system.cpu.rob.rob_writes 129738562 # The number of ROB writes +system.cpu.timesIdled 1269768 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34085657 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3602789251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53062487 # Number of Instructions Simulated +system.cpu.committedOps 53062487 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53062487 # Number of Instructions Simulated +system.cpu.cpi 2.166575 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.166575 # CPI: Total CPI of All Threads +system.cpu.ipc 0.461558 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.461558 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74266984 # number of integer regfile reads +system.cpu.int_regfile_writes 40553865 # number of integer regfile writes +system.cpu.fp_regfile_reads 166054 # number of floating regfile reads +system.cpu.fp_regfile_writes 167450 # number of floating regfile writes +system.cpu.misc_regfile_reads 1999349 # number of misc regfile reads +system.cpu.misc_regfile_writes 950331 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -670,247 +658,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1025621 # number of replacements -system.cpu.icache.tagsinuse 509.964536 # Cycle average of tags in use -system.cpu.icache.total_refs 7915589 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1026130 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.714022 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23323095000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.964536 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996024 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996024 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7915590 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7915590 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7915590 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7915590 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7915590 # number of overall hits -system.cpu.icache.overall_hits::total 7915590 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9001683 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9001683 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9001683 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9001683 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120654 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120654 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120654 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14978.890385 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14978.890385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14978.890385 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked +system.cpu.icache.replacements 1020915 # number of replacements +system.cpu.icache.tagsinuse 509.977219 # Cycle average of tags in use +system.cpu.icache.total_refs 7681837 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1021424 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.520713 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23212946000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.977219 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996049 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996049 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7681838 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7681838 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7681838 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7681838 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7681838 # number of overall hits +system.cpu.icache.overall_hits::total 7681838 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1079605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1079605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1079605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1079605 # number of overall misses +system.cpu.icache.overall_misses::total 1079605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16072965497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16072965497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16072965497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16072965497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16072965497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16072965497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8761443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8761443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8761443 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8761443 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8761443 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8761443 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123222 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123222 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123222 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123222 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123222 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123222 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14887.820543 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14887.820543 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14887.820543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14887.820543 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1368497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 139 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9845.302158 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 238 # number of writebacks -system.cpu.icache.writebacks::total 238 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59750 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 59750 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 59750 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 59750 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 59750 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 59750 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026343 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1026343 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1026343 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1026343 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1026343 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1026343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12299507497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12299507497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12299507497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12299507497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114017 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114017 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114017 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.817785 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 236 # number of writebacks +system.cpu.icache.writebacks::total 236 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57973 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 57973 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 57973 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 57973 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 57973 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 57973 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021632 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1021632 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1021632 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1021632 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1021632 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1021632 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12173342997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12173342997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12173342997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12173342997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12173342997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12173342997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116605 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116605 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116605 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11915.585061 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11915.585061 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1402627 # number of replacements -system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use -system.cpu.dcache.total_refs 11951343 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403139 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.517576 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19459000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995944 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1401226 # number of replacements +system.cpu.dcache.tagsinuse 511.995976 # Cycle average of tags in use +system.cpu.dcache.total_refs 11915698 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401738 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.500660 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19319000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995976 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7323424 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7323424 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4214108 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4214108 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 193501 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 193501 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 220102 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220102 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11537532 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11537532 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11537532 # number of overall hits -system.cpu.dcache.overall_hits::total 11537532 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1804216 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1804216 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1942860 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1942860 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23377 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23377 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3747076 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3747076 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3747076 # number of overall misses -system.cpu.dcache.overall_misses::total 3747076 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38906858000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38906858000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58108807026 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58108807026 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 346630500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 346630500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83500 # 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miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20957.991387 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20957.991387 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29826.296079 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29826.296079 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14543.575298 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14543.575298 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25559.559314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25559.559314 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 805076325 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 99334 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9123.293381 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8104.740824 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834483 # 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840933 # number of writebacks +system.cpu.dcache.writebacks::total 840933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 715397 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 715397 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640618 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1640618 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5145 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5145 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2356015 # 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number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32542701825 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32542701825 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32542701825 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32542701825 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904540000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904540000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234101998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234101998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138641998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138641998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048740 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048740 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083836 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083836 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090783 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090783 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22203.183350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22203.183350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28252.273818 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28252.273818 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11516.146124 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11516.146124 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -919,28 +907,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211556 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74875 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105790 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182786 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73508 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73510 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149139 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820018970500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94294500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 380287500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38189985000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858683537500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211701 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74930 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105874 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182929 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73563 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73566 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149254 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1820291216500 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94615000 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 380636500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38112442500 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858878910500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815921 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694845 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815912 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -979,29 +967,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175453 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175590 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6787 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5213 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192407 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5952 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.callpal::total 192549 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320403 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.389995 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.389547 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29004913500 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2663331000 0.14% 1.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827210658000 98.30% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |