SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simout => tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/simple-timing/simerr => tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-timing/simout => tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
rename : tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/20.parser/test.py => tests/long/se/20.parser/test.py
rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/30.eon/ref/arm/linux/o3-timing/config.ini => tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
rename : tests/long/30.eon/ref/arm/linux/o3-timing/simerr => tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
rename : tests/long/30.eon/ref/arm/linux/o3-timing/simout => tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
rename : tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt => tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini => tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/30.eon/ref/arm/linux/simple-atomic/simerr => tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
rename : tests/long/30.eon/ref/arm/linux/simple-atomic/simout => tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
rename : tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/30.eon/ref/arm/linux/simple-timing/config.ini => tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
rename : tests/long/30.eon/ref/arm/linux/simple-timing/simerr => tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
rename : tests/long/30.eon/ref/arm/linux/simple-timing/simout => tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
rename : tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt => tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/30.eon/test.py => tests/long/se/30.eon/test.py
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/40.perlbmk/test.py => tests/long/se/40.perlbmk/test.py
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simout => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/50.vortex/test.py => tests/long/se/50.vortex/test.py
rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/60.bzip2/test.py => tests/long/se/60.bzip2/test.py
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/simerr => tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/simout => tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out => tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/simout => tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simerr => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.out => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pin => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sav => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.twf => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/simout => tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/test.py => tests/long/se/70.twolf/test.py
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simout => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/simout => tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simout => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/power/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/power/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/power/linux/o3-timing/simout => tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/test.py => tests/quick/se/00.hello/test.py
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simout => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

10 files changed, 5565 insertions, 0 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
new file mode 100644
index 000000000..94bfc8925
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -0,0 +1,1627 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxAlphaSystem
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+boot_cpu_frequency=500
+boot_osflags=root=/dev/hda1 console=ttyS0
+console=/dist/m5/system/binaries/console
+init_param=0
+kernel=/dist/m5/system/binaries/vmlinux
+load_addr_mask=1099511627775
+mem_mode=timing
+memories=system.physmem
+num_work_ids=16
+pal=/dist/m5/system/binaries/ts_osfpal
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+system_rev=1024
+system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[2]
+
+[system.bridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
+write_ack=false
+master=system.iobus.port[0]
+slave=system.membus.port[0]
+
+[system.cpu0]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu0.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu0.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu0.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu0.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu0.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
+
+[system.cpu0.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu0.fuPool.FUList0.opList
+
+[system.cpu0.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu0.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
+
+[system.cpu0.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu0.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu0.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
+
+[system.cpu0.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu0.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu0.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu0.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
+
+[system.cpu0.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu0.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu0.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu0.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu0.fuPool.FUList4.opList
+
+[system.cpu0.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu0.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
+
+[system.cpu0.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu0.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu0.fuPool.FUList6.opList
+
+[system.cpu0.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu0.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
+
+[system.cpu0.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu0.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu0.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu0.fuPool.FUList8.opList
+
+[system.cpu0.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.interrupts]
+type=AlphaInterrupts
+
+[system.cpu0.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=1
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu1.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu1.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu1.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu1.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu1.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu1.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
+
+[system.cpu1.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu1.fuPool.FUList0.opList
+
+[system.cpu1.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu1.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
+
+[system.cpu1.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu1.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu1.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
+
+[system.cpu1.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu1.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu1.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu1.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
+
+[system.cpu1.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu1.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu1.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu1.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu1.fuPool.FUList4.opList
+
+[system.cpu1.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu1.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
+
+[system.cpu1.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu1.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu1.fuPool.FUList6.opList
+
+[system.cpu1.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu1.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
+
+[system.cpu1.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu1.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu1.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu1.fuPool.FUList8.opList
+
+[system.cpu1.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu1.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu1.interrupts]
+type=AlphaInterrupts
+
+[system.cpu1.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.disk0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.disk0.image
+
+[system.disk0.image]
+type=CowDiskImage
+children=child
+child=system.disk0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk2]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.disk2.image
+
+[system.disk2.image]
+type=CowDiskImage
+children=child
+child=system.disk2.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=true
+width=64
+default=system.tsunami.pciconfig.pio
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
+
+[system.iocache]
+type=BaseCache
+addr_range=0:8589934591
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+is_top_level=true
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=2
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[4]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+fake_mem=false
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
+[system.simple_disk]
+type=SimpleDisk
+children=disk
+disk=system.simple_disk.disk
+system=system
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
+
+[system.tsunami]
+type=Tsunami
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+intrctrl=system.intrctrl
+system=system
+
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+cpu=system.cpu0
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[25]
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=1000
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+pio=system.iobus.port[1]
+
+[system.tsunami.ethernet]
+type=NSGigE
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=256
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=4096
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=34
+ExpansionROM=0
+HeaderType=0
+InterruptLine=30
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=52
+MinimumGrant=176
+ProgIF=0
+Revision=0
+Status=656
+SubClassCode=0
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=4107
+clock=0
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+fake_mem=false
+pio_addr=8796093677568
+pio_latency=1000
+pio_size=393216
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[9]
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848432
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[20]
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848304
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[21]
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848569
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[10]
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848451
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[12]
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848515
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[13]
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848579
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[14]
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848643
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[15]
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848707
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[16]
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848771
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[17]
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848835
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[18]
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848899
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[19]
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615850617
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[11]
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848891
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[8]
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848816
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[3]
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848696
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[4]
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848936
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[5]
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848680
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[6]
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848944
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[7]
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+pio_latency=1000
+platform=system.tsunami
+system=system
+pio=system.iobus.port[22]
+
+[system.tsunami.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=0
+disks=system.disk0 system.disk2
+io_shift=0
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+system=system
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
+pio=system.iobus.port[26]
+
+[system.tsunami.io]
+type=TsunamiIO
+frequency=976562500
+pio_addr=8804615847936
+pio_latency=1000
+platform=system.tsunami
+system=system
+time=Thu Jan  1 00:00:00 2009
+tsunami=system.tsunami
+year_is_bcd=false
+pio=system.iobus.port[23]
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=1000
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+pio=system.iobus.port[2]
+
+[system.tsunami.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.tsunami
+size=16777216
+system=system
+pio=system.iobus.default
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[24]
+
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
new file mode 100755
index 000000000..0bcb6e870
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
new file mode 100755
index 000000000..35f0311de
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -0,0 +1,13 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 06:11:48
+gem5 executing on zizzer
+command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
+Global frequency set at 1000000000000 ticks per second
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: Entering event queue @ 0.  Starting simulation...
+info: Launching CPU 1 @ 106949500
+Exiting @ tick 1897465263500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
new file mode 100644
index 000000000..d2e784a3f
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -0,0 +1,1575 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  1.897465                       # Number of seconds simulated
+sim_ticks                                1897465263500                       # Number of ticks simulated
+final_tick                               1897465263500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 131690                       # Simulator instruction rate (inst/s)
+host_tick_rate                             4451680142                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298548                       # Number of bytes of host memory used
+host_seconds                                   426.24                       # Real time elapsed on the host
+sim_insts                                    56130966                       # Number of instructions simulated
+system.physmem.bytes_read                    30408320                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1097728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10468544                       # Number of bytes written to this memory
+system.physmem.num_reads                       475130                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      163571                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       16025758                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    578523                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5517120                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      21542879                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        397795                       # number of replacements
+system.l2c.tagsinuse                     35116.884908                       # Cycle average of tags in use
+system.l2c.total_refs                         2482671                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        433561                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          5.726232                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    9252063000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                 12003.983788                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   238.395777                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 22874.505342                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.183166                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.003638                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.349037                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    1719678                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     147350                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1867028                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   826540                       # number of Writeback hits
+system.l2c.Writeback_hits::total               826540                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                     172                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                      46                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 218                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0                    28                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1                    28                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                56                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0                   168225                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                    11091                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               179316                       # number of ReadExReq hits
+system.l2c.demand_hits::0                     1887903                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      158441                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2046344                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    1887903                       # number of overall hits
+system.l2c.overall_hits::1                     158441                       # number of overall hits
+system.l2c.overall_hits::2                          0                       # number of overall hits
+system.l2c.overall_hits::total                2046344                       # number of overall hits
+system.l2c.ReadReq_misses::0                   305537                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     4057                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               309594                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  2453                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                   560                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3013                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0                  48                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1                  84                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             132                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0                 113925                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                  10735                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             124660                       # number of ReadExReq misses
+system.l2c.demand_misses::0                    419462                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                     14792                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                434254                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   419462                       # number of overall misses
+system.l2c.overall_misses::1                    14792                       # number of overall misses
+system.l2c.overall_misses::2                        0                       # number of overall misses
+system.l2c.overall_misses::total               434254                       # number of overall misses
+system.l2c.ReadReq_miss_latency           16116451000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency            3978500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency           680500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          6538718500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency            22655169500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency           22655169500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                2025215                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 151407                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2176622                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               826540                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           826540                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                2625                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                 606                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3231                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0                76                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1               112                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           188                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               282150                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                21826                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           303976                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                 2307365                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  173233                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2480598                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                2307365                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 173233                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2480598                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.150866                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.026795                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.934476                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.924092                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0         0.631579                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1         0.750000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.403775                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.491845                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.181793                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.085388                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.181793                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.085388                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   52747.951967                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   3972504.560020                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0  1621.891561                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1  7104.464286                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::0 14177.083333                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1  8101.190476                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 57394.939653                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 609102.794597                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    54010.064082                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    1531582.578421                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   54010.064082                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   1531582.578421                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                          122051                       # number of writebacks
+system.l2c.ReadReq_mshr_hits                       18                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits                        18                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                       18                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                 309576                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                3013                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses               132                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               124660                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  434236                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 434236                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency      12393243000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency     120589000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency      5280000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     5022395000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency       17415638000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency      17415638000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency    838122500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1421433998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency   2259556498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.152861                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         2.044661                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      1.147810                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      4.971947                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.736842                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.178571                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.441822                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       5.711537                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0          0.188196                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          2.506659                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         0.188196                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         2.506659                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40032.957981                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.900763                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40288.745387                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40106.389152                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40106.389152                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.iocache.replacements                     41697                       # number of replacements
+system.iocache.tagsinuse                     0.463240                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                     41713                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle              1709322874000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 0.463240                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.028953                       # Average percentage of cache occupancy
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.ReadReq_misses::1                  177                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              177                       # number of ReadReq misses
+system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41729                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41729                       # number of demand (read+write) misses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                41729                       # number of overall misses
+system.iocache.overall_misses::total            41729                       # number of overall misses
+system.iocache.ReadReq_miss_latency          20390998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency       5721236806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency         5741627804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency        5741627804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                177                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            177                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41729                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41729                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41729                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41729                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115203.378531                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137688.602378                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137593.227827                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137593.227827                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs      64620068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10458                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6179.008223                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks                       41520                       # number of writebacks
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.ReadReq_mshr_misses                177                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses               41729                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses              41729                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.ReadReq_mshr_miss_latency     11186998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3560378000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3571564998                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3571564998                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency 63203.378531                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85684.876781                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85589.518033                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85589.518033                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.read_hits                     9507417                       # DTB read hits
+system.cpu0.dtb.read_misses                     35968                       # DTB read misses
+system.cpu0.dtb.read_acv                          598                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  640032                       # DTB read accesses
+system.cpu0.dtb.write_hits                    6191307                       # DTB write hits
+system.cpu0.dtb.write_misses                     8160                       # DTB write misses
+system.cpu0.dtb.write_acv                         353                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 218604                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15698724                       # DTB hits
+system.cpu0.dtb.data_misses                     44128                       # DTB misses
+system.cpu0.dtb.data_acv                          951                       # DTB access violations
+system.cpu0.dtb.data_accesses                  858636                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1059111                       # ITB hits
+system.cpu0.itb.fetch_misses                    28345                       # ITB misses
+system.cpu0.itb.fetch_acv                         951                       # ITB acv
+system.cpu0.itb.fetch_accesses                1087456                       # ITB accesses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.numCycles                       112078637                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.BPredUnit.lookups                13676513                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted          11471993                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            481224                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups             12342117                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 6355141                       # Number of BTB hits
+system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.BPredUnit.usedRAS                  915334                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              37832                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          28007609                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      69419364                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   13676513                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           7270475                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     13464854                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                2130456                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles              34838342                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles               29311                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       192876                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       330870                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles           82                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  8508842                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               295697                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          78241728                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.887242                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.203788                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                64776874     82.79%     82.79% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  958993      1.23%     84.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1895458      2.42%     86.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  896557      1.15%     87.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2826529      3.61%     91.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  644193      0.82%     92.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  736181      0.94%     92.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1019927      1.30%     94.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4487016      5.73%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total            78241728                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.122026                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.619381                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                29114965                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             34547748                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 12317154                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               921824                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1340036                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              563514                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                37992                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              67952438                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               114909                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1340036                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                30246504                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               12447336                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      18631420                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 11494424                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              4082006                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              64196257                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 6719                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                464674                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1470831                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands           42946380                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             77900777                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        77469173                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           431604                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             36477108                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 6469264                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1576496                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        238440                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 11483101                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            10008373                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6527102                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1185571                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          771360                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  56320474                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            2007436                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 54875963                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           110266                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        7429207                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      3754226                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1369428                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     78241728                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.701364                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.347589                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           54100520     69.15%     69.15% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10639232     13.60%     82.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            5191485      6.64%     89.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            3321136      4.24%     93.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2520069      3.22%     96.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1468713      1.88%     98.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             637402      0.81%     99.54% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             263268      0.34%     99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              99903      0.13%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       78241728                       # Number of insts issued each cycle
+system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  61581      8.74%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                342929     48.66%     57.40% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               300261     42.60%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.FU_type_0::No_OpClass             3329      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             37711302     68.72%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               60327      0.11%     68.84% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.84% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              15682      0.03%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1654      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9937545     18.11%     86.98% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            6268980     11.42%     98.40% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            877144      1.60%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total              54875963                       # Type of FU issued
+system.cpu0.iq.rate                          0.489620                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     704772                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.012843                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         188187092                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         65472775                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     53463452                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             621599                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            297101                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       294471                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              55250754                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 326652                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          544032                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.squashedLoads      1411765                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        14119                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        13054                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       526523                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread0.rescheduledLoads        19033                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       166880                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu0.iew.iewSquashCycles               1340036                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                8692237                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               606269                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           61830785                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           830784                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             10008373                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6527102                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1772467                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                482817                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                10549                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         13054                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        346528                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       358003                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              704531                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             54241616                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9570533                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           634346                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu0.iew.exec_nop                      3502875                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    15784325                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8657029                       # Number of branches executed
+system.cpu0.iew.exec_stores                   6213792                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.483960                       # Inst execution rate
+system.cpu0.iew.wb_sent                      53872827                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     53757923                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 26542591                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 35724968                       # num instructions consuming a value
+system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_rate                      0.479645                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.742970                       # average fanout of values written-back
+system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.commit.commitCommittedInsts      53656716                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts        8078010                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         638008                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           642783                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     76901692                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.697731                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.609209                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     56673915     73.70%     73.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      8488315     11.04%     84.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      4528829      5.89%     90.62% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2497024      3.25%     93.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1465718      1.91%     95.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       614414      0.80%     96.58% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       447034      0.58%     97.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       489019      0.64%     97.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1697424      2.21%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total     76901692                       # Number of insts commited each cycle
+system.cpu0.commit.count                     53656716                       # Number of instructions committed
+system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu0.commit.refs                      14597187                       # Number of memory references committed
+system.cpu0.commit.loads                      8596608                       # Number of loads committed
+system.cpu0.commit.membars                     217615                       # Number of memory barriers committed
+system.cpu0.commit.branches                   8092300                       # Number of branches committed
+system.cpu0.commit.fp_insts                    291990                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 49637924                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              704482                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1697424                       # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu0.rob.rob_reads                   136748495                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  124811050                       # The number of ROB writes
+system.cpu0.timesIdled                        1231942                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       33836909                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3682845519                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   50542242                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total             50542242                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.217524                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.217524                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.450953                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.450953                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                71124780                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               38876207                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   143910                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  146325                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1863327                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                888204                       # number of misc regfile writes
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu0.icache.replacements                970482                       # number of replacements
+system.cpu0.icache.tagsinuse               510.008508                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 7483994                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                970994                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  7.707559                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           23358720000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0           510.008508                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.996110                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::0            7483994                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        7483994                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::0             7483994                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         7483994                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::0            7483994                       # number of overall hits
+system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::total        7483994                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::0          1024848                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1024848                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::0           1024848                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1024848                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::0          1024848                       # number of overall misses
+system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1024848                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency   15319794498                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency    15319794498                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency   15319794498                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::0        8508842                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      8508842                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::0         8508842                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      8508842                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::0        8508842                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      8508842                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::0      0.120445                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::0       0.120445                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::0      0.120445                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::0 14948.357706                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::0 14948.357706                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::0 14948.357706                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1225998                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              103                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 11902.893204                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks                     218                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits            53716                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits             53716                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits            53716                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses         971132                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses          971132                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses         971132                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency  11617050998                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency  11617050998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency  11617050998                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.114132                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::0     0.114132                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::0     0.114132                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11962.381013                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11962.381013                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11962.381013                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements               1339905                       # number of replacements
+system.cpu0.dcache.tagsinuse               503.729057                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                11343106                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1340416                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  8.462377                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0           504.729057                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.985799                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::0            6978274                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6978274                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::0           3967577                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3967577                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::0       182488                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       182488                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::0        208558                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       208558                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::0            10945851                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10945851                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::0           10945851                       # number of overall hits
+system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10945851                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::0          1696520                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1696520                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::0         1808915                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1808915                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::0        21731                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21731                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::0          693                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          693                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::0           3505435                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3505435                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::0          3505435                       # number of overall misses
+system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3505435                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency   37036233000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency  55166183811                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency    327139500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency      6516000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency    92202416811                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency   92202416811                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::0        8674794                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8674794                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::0       5776492                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5776492                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::0       204219                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       204219                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::0       209251                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       209251                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::0        14451286                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     14451286                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::0       14451286                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     14451286                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::0      0.195569                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::0     0.313151                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.106410                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::0     0.003312                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::0       0.242569                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::0      0.242569                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 21830.708156                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 30496.835844                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15054.047214                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0  9402.597403                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::0 26302.703320                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::0 26302.703320                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs    886352311                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       210500                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           100011                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              9                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8862.548230                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 23388.888889                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks                  790429                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits           651194                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits         1524352                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits         4898                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits           2175546                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits          2175546                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses        1045326                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses        284563                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses        16833                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses          693                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses         1329889                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses        1329889                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency  24217800500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency   8294565311                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    195726500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency      4430000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency  32512365811                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency  32512365811                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    916795000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1253240498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency   2170035498                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.120502                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.049262                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.082426                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.003312                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::0     0.092026                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::0     0.092026                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23167.701272                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29148.432196                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11627.547080                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  6392.496392                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 24447.428177                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 24447.428177                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.read_hits                     1326048                       # DTB read hits
+system.cpu1.dtb.read_misses                     10245                       # DTB read misses
+system.cpu1.dtb.read_acv                            4                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  331667                       # DTB read accesses
+system.cpu1.dtb.write_hits                     775032                       # DTB write hits
+system.cpu1.dtb.write_misses                     3356                       # DTB write misses
+system.cpu1.dtb.write_acv                          50                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 128144                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2101080                       # DTB hits
+system.cpu1.dtb.data_misses                     13601                       # DTB misses
+system.cpu1.dtb.data_acv                           54                       # DTB access violations
+system.cpu1.dtb.data_accesses                  459811                       # DTB accesses
+system.cpu1.itb.fetch_hits                     367550                       # ITB hits
+system.cpu1.itb.fetch_misses                     7752                       # ITB misses
+system.cpu1.itb.fetch_acv                         129                       # ITB acv
+system.cpu1.itb.fetch_accesses                 375302                       # ITB accesses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.numCycles                         9966962                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.BPredUnit.lookups                 1746608                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           1443175                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect             66232                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups              1579747                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                  700902                       # Number of BTB hits
+system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.BPredUnit.usedRAS                  120007                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect               5197                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles           3352188                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                       8389538                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    1746608                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches            820909                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      1600088                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 340649                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles               3953742                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles               24318                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        65300                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        48169                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1052111                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                37387                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples           9268453                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.905171                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.248228                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                 7668365     82.74%     82.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  115994      1.25%     83.99% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  231226      2.49%     86.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  132329      1.43%     87.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  251751      2.72%     90.63% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   85931      0.93%     91.55% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  105894      1.14%     92.70% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                   73622      0.79%     93.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                  603341      6.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total             9268453                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.175240                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.841735                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 3426888                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              4059985                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  1487039                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                74425                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                220115                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved               74752                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 4586                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts               8123817                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                13801                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                220115                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 3563676                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 426586                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       3211249                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  1411283                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               435542                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts               7548530                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  102                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 46052                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents                92764                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands            5048861                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups              9245845                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups         9192898                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            52947                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              4017246                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1031615                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            305905                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         22528                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  1292369                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             1416426                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores             841512                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           141179                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           90021                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                   6602199                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             325316                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                  6284355                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            22621                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1273450                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       716539                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        249793                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples      9268453                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.678037                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.328780                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0            6498051     70.11%     70.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1227525     13.24%     83.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             582679      6.29%     89.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             391581      4.22%     93.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             294983      3.18%     97.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             158395      1.71%     98.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6              72456      0.78%     99.54% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              32178      0.35%     99.89% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              10605      0.11%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total        9268453                       # Number of insts issued each cycle
+system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                   2859      1.97%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                 82047     56.45%     58.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                60446     41.59%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.FU_type_0::No_OpClass             3978      0.06%      0.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              3890788     61.91%     61.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               10226      0.16%     62.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              10071      0.16%     62.30% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.30% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.30% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.30% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1988      0.03%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             1381194     21.98%     84.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite             794695     12.65%     96.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            191415      3.05%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total               6284355                       # Type of FU issued
+system.cpu1.iq.rate                          0.630519                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     145352                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.023129                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          21926150                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes          8163461                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses      6082297                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              78986                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes             39141                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses        37853                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses               6384800                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                  40929                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           61528                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.squashedLoads       262809                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         6760                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         1750                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       113415                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread0.rescheduledLoads          366                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        22210                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu1.iew.iewSquashCycles                220115                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 309272                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                12037                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts            7192077                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            99271                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              1416426                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts              841512                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            303434                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  3996                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 4977                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          1750                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         48213                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        60062                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              108275                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts              6205529                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              1339876                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts            78826                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu1.iew.exec_nop                       264562                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     2121617                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                  906286                       # Number of branches executed
+system.cpu1.iew.exec_stores                    781741                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.622610                       # Inst execution rate
+system.cpu1.iew.wb_sent                       6147670                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                      6120150                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  2958458                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  4045224                       # num instructions consuming a value
+system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_rate                      0.614044                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.731346                       # average fanout of values written-back
+system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.commit.commitCommittedInsts       5812223                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts        1307029                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls          75523                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           100285                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples      9048338                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.642353                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.547343                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0      6777327     74.90%     74.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1099919     12.16%     87.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       394591      4.36%     91.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       244546      2.70%     94.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       155405      1.72%     95.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        74689      0.83%     96.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6        76341      0.84%     97.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7        67787      0.75%     98.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       157733      1.74%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total      9048338                       # Number of insts commited each cycle
+system.cpu1.commit.count                      5812223                       # Number of instructions committed
+system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu1.commit.refs                       1881714                       # Number of memory references committed
+system.cpu1.commit.loads                      1153617                       # Number of loads committed
+system.cpu1.commit.membars                      20508                       # Number of memory barriers committed
+system.cpu1.commit.branches                    821256                       # Number of branches committed
+system.cpu1.commit.fp_insts                     36401                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  5437919                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls               89388                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events               157733                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu1.rob.rob_reads                    15919184                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   14457399                       # The number of ROB writes
+system.cpu1.timesIdled                          81947                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         698509                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3784960163                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    5588724                       # Number of Instructions Simulated
+system.cpu1.committedInsts_total              5588724                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.783406                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.783406                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.560725                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.560725                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                 8091693                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                4410635                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    24636                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   23087                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 284786                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                134830                       # number of misc regfile writes
+system.cpu1.icache.replacements                110610                       # number of replacements
+system.cpu1.icache.tagsinuse               452.934793                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                  935676                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                111121                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                  8.420335                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1874818206000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0           452.934793                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.884638                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::0             935676                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         935676                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::0              935676                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          935676                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::0             935676                       # number of overall hits
+system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::total         935676                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::0           116435                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       116435                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::0            116435                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        116435                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::0           116435                       # number of overall misses
+system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::total       116435                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency    1751730499                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency     1751730499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency    1751730499                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::0        1052111                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1052111                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::0         1052111                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1052111                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::0        1052111                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1052111                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::0      0.110668                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::0       0.110668                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::0      0.110668                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.707339                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::0 15044.707339                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::0 15044.707339                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs        93999                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               13                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  7230.692308                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks                      37                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits             5243                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits              5243                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits             5243                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses         111192                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses          111192                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses         111192                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency   1333669999                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency   1333669999                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency   1333669999                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.105685                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::0     0.105685                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::0     0.105685                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11994.298142                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11994.298142                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11994.298142                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.replacements                 62429                       # number of replacements
+system.cpu1.dcache.tagsinuse               392.995073                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 1698421                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                 62755                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 27.064314                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1874613639500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0           392.995073                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.767569                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::0            1125916                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1125916                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::0            549554                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        549554                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::0        16796                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        16796                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::0         14923                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        14923                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::0             1675470                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         1675470                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::0            1675470                       # number of overall hits
+system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        1675470                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::0           106694                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       106694                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::0          157811                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       157811                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::0         1480                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         1480                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::0          700                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          700                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::0            264505                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        264505                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::0           264505                       # number of overall misses
+system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       264505                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency    1790096000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency   5171682833                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency     19414000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency      8395500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency     6961778833                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency    6961778833                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::0        1232610                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1232610                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::0        707365                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total       707365                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::0        18276                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        18276                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::0        15623                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        15623                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::0         1939975                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      1939975                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::0        1939975                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      1939975                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::0      0.086559                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::0     0.223097                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.080981                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.044806                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::0       0.136345                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::0      0.136345                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 16777.850676                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 32771.371026                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13117.567568                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11993.571429                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::0 26320.027345                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::0 26320.027345                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs     86579997                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             6823                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12689.432361                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks                   35856                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits            62883                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits          134026                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits          295                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits            196909                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits           196909                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses          43811                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses         23785                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses         1185                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses          699                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses           67596                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses          67596                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency    556154000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency    752491985                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     11636500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency      6289000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency   1308645985                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency   1308645985                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     19117500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    320801000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency    339918500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.035543                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.033625                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.064839                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.044742                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::0     0.034844                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0     0.034844                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.391819                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31637.249737                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  9819.831224                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  8997.138770                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 19359.813968                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 19359.813968                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                    6372                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    199307                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   71537     40.62%     40.62% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    237      0.13%     40.75% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1922      1.09%     41.84% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                      8      0.00%     41.85% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 102421     58.15%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              176125                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    70172     49.24%     49.24% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     237      0.17%     49.41% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1922      1.35%     50.76% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                       8      0.01%     50.76% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   70164     49.24%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               142503                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1858853057000     97.97%     97.97% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               90805500      0.00%     97.97% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              391568500      0.02%     97.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30                4023000      0.00%     97.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            38125490000      2.01%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1897464944000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.980919                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.685055                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      3.72%      3.72% # number of syscalls executed
+system.cpu0.kern.syscall::3                        18      8.37%     12.09% # number of syscalls executed
+system.cpu0.kern.syscall::4                         3      1.40%     13.49% # number of syscalls executed
+system.cpu0.kern.syscall::6                        32     14.88%     28.37% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.47%     28.84% # number of syscalls executed
+system.cpu0.kern.syscall::17                        8      3.72%     32.56% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.65%     37.21% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.79%     40.00% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.47%     40.47% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.40%     41.86% # number of syscalls executed
+system.cpu0.kern.syscall::33                        6      2.79%     44.65% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.93%     45.58% # number of syscalls executed
+system.cpu0.kern.syscall::45                       33     15.35%     60.93% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.40%     62.33% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.65%     66.98% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.65%     71.63% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.47%     72.09% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.79%     74.88% # number of syscalls executed
+system.cpu0.kern.syscall::71                       23     10.70%     85.58% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.40%     86.98% # number of syscalls executed
+system.cpu0.kern.syscall::74                        6      2.79%     89.77% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.47%     90.23% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.40%     91.63% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      4.19%     95.81% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.93%     96.74% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.93%     97.67% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.47%     98.14% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.93%     99.07% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.93%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   215                       # number of syscalls executed
+system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  105      0.06%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3840      2.08%      2.14% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      50      0.03%      2.16% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.17% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               169189     91.54%     93.71% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6337      3.43%     97.14% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.14% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     2      0.00%     97.14% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.00%     97.15% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.15% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4768      2.58%     99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 369      0.20%     99.93% # number of callpals executed
+system.cpu0.kern.callpal::imb                     135      0.07%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                184818                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7264                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1248                       # number of protection mode switches
+system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
+system.cpu0.kern.mode_good::kernel               1247                      
+system.cpu0.kern.mode_good::user                 1248                      
+system.cpu0.kern.mode_good::idle                    0                      
+system.cpu0.kern.mode_switch_good::kernel     0.171669                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1895604498000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1860438000      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    3841                       # number of times the context was actually changed
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                    2274                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     38564                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   10256     33.36%     33.36% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1920      6.25%     39.61% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    105      0.34%     39.95% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  18460     60.05%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               30741                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    10244     45.72%     45.72% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1920      8.57%     54.28% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     105      0.47%     54.75% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   10139     45.25%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                22408                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1871092276500     98.61%     98.61% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              343292500      0.02%     98.63% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               42130500      0.00%     98.63% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            25986985000      1.37%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1897464684500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.998830                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.549242                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3                        12     10.81%     10.81% # number of syscalls executed
+system.cpu1.kern.syscall::4                         1      0.90%     11.71% # number of syscalls executed
+system.cpu1.kern.syscall::6                        10      9.01%     20.72% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.90%     21.62% # number of syscalls executed
+system.cpu1.kern.syscall::17                        7      6.31%     27.93% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.70%     30.63% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.70%     33.33% # number of syscalls executed
+system.cpu1.kern.syscall::33                        5      4.50%     37.84% # number of syscalls executed
+system.cpu1.kern.syscall::45                       21     18.92%     56.76% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.70%     59.46% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      0.90%     60.36% # number of syscalls executed
+system.cpu1.kern.syscall::71                       31     27.93%     88.29% # number of syscalls executed
+system.cpu1.kern.syscall::74                       10      9.01%     97.30% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.70%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   111                       # number of syscalls executed
+system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                    8      0.03%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  393      1.24%      1.27% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.01%      1.28% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.02%      1.30% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                26187     82.50%     83.80% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2413      7.60%     91.40% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.41% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     5      0.02%     91.42% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     91.43% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2528      7.96%     99.40% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 146      0.46%     99.86% # number of callpals executed
+system.cpu1.kern.callpal::imb                      45      0.14%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::total                 31743                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel              869                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                492                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2054                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                522                      
+system.cpu1.kern.mode_good::user                  492                      
+system.cpu1.kern.mode_good::idle                   30                      
+system.cpu1.kern.mode_switch_good::kernel     0.600690                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::idle      0.014606                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     1.615296                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        2061638000      0.11%      0.11% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           848590000      0.04%      0.15% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1893876047000     99.85%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     394                       # number of times the context was actually changed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
new file mode 100644
index 000000000..6c5842787
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
@@ -0,0 +1,113 @@
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+
Got Configuration 623
+
memsize 8000000 pages 4000 
+
First free page after ROM 0xFFFFFC0000018000
+
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+
CPU Clock at 2000 MHz IntrClockFrequency=1024 
+
Booting with 2 processor(s) 
+
KSP: 0x20043FE8 PTBR 0x20
+
KSP: 0x20043FE8 PTBR 0x20
+
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
+
Memory cluster 0 [0 - 392]
+
Memory cluster 1 [392 - 15992]
+
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 
+
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
+
Bootstraping CPU 1 with sp=0xFFFFFC0000076000
+
unix_boot_mem ends at FFFFFC0000078000 
+
k_argc = 0 
+
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
CallbackFixup 0 18000, t7=FFFFFC000070C000
+
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
+
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
+
Command line: root=/dev/hda1 console=ttyS0
+
memcluster 0, usage 1, start        0, end      392
+
memcluster 1, usage 0, start      392, end    16384
+
freeing pages 1069:16384
+
reserving pages 1069:1070
+
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
+
SMP: 2 CPUs probed -- cpu_present_mask = 3
+
Built 1 zonelists
+
Kernel command line: root=/dev/hda1 console=ttyS0
+
PID hash table entries: 1024 (order: 10, 32768 bytes)
+
Using epoch = 1900
+
Console: colour dummy device 80x25
+
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
+
Mount-cache hash table entries: 512
+
SMP starting up secondaries.
+
Slave CPU 1 console command START

+SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
+
Brought up 2 CPUs
+
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
+
NET: Registered protocol family 16
+
EISA bus registered
+
pci: enabling save/restore of SRM state
+
SCSI subsystem initialized
+
srm_env: version 0.0.5 loaded successfully
+
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+
Initializing Cryptographic API
+
rtc: Standard PC (1900) epoch (1900) detected
+
Real Time Clock Driver v1.12
+
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
+
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
io scheduler noop registered
+
io scheduler anticipatory registered
+
io scheduler deadline registered
+
io scheduler cfq registered
+
loop: loaded (max 8 devices)
+
nbd: registered device at major 43
+
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
PCI: Setting latency timer of device 0000:00:01.0 to 64
+
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
+
eth0: enabling optical transceiver
+
eth0: using 64 bit addressing.
+
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
tun: Universal TUN/TAP device driver, 1.6
+
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+
PIIX4: IDE controller at PCI slot 0000:00:00.0
+
PIIX4: chipset revision 0
+
PIIX4: 100% native mode on irq 31
+
PCI: Setting latency timer of device 0000:00:00.0 to 64
+
    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
+
    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
+
hda: M5 IDE Disk, ATA DISK drive
+
hdb: M5 IDE Disk, ATA DISK drive
+
ide0 at 0x8410-0x8417,0x8422 on irq 31
+
hda: max request size: 128KiB
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
+
hda: cache flushes not supported
+
 hda: hda1
+
hdb: max request size: 128KiB
+
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
hdb: cache flushes not supported
+
 hdb: unknown partition table
+
mice: PS/2 mouse device common for all mice
+
NET: Registered protocol family 2
+
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP: Hash tables configured (established 16384 bind 16384)
+
TCP reno registered
+
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
+
ip_tables: (C) 2000-2002 Netfilter core team
+
arp_tables: (C) 2002 David S. Miller
+
TCP bic registered
+
Initializing IPsec netlink socket
+
NET: Registered protocol family 1
+
NET: Registered protocol family 17
+
NET: Registered protocol family 15
+
Bridge firewalling registered
+
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
+
All bugs added by David S. Miller <davem@redhat.com>
+
VFS: Mounted root (ext2 filesystem) readonly.
+
Freeing unused kernel memory: 224k freed
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
new file mode 100644
index 000000000..b0a37466e
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -0,0 +1,1191 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxAlphaSystem
+children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+boot_cpu_frequency=500
+boot_osflags=root=/dev/hda1 console=ttyS0
+console=/dist/m5/system/binaries/console
+init_param=0
+kernel=/dist/m5/system/binaries/vmlinux
+load_addr_mask=1099511627775
+mem_mode=timing
+memories=system.physmem
+num_work_ids=16
+pal=/dist/m5/system/binaries/ts_osfpal
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+system_rev=1024
+system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[2]
+
+[system.bridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
+write_ack=false
+master=system.iobus.port[0]
+slave=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.disk0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.disk0.image
+
+[system.disk0.image]
+type=CowDiskImage
+children=child
+child=system.disk0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk2]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.disk2.image
+
+[system.disk2.image]
+type=CowDiskImage
+children=child
+child=system.disk2.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=true
+width=64
+default=system.tsunami.pciconfig.pio
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
+
+[system.iocache]
+type=BaseCache
+addr_range=0:8589934591
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+is_top_level=true
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[4]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+fake_mem=false
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
+[system.simple_disk]
+type=SimpleDisk
+children=disk
+disk=system.simple_disk.disk
+system=system
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.tsunami]
+type=Tsunami
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+intrctrl=system.intrctrl
+system=system
+
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+cpu=system.cpu
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[25]
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=1000
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+pio=system.iobus.port[1]
+
+[system.tsunami.ethernet]
+type=NSGigE
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=256
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=4096
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=34
+ExpansionROM=0
+HeaderType=0
+InterruptLine=30
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=52
+MinimumGrant=176
+ProgIF=0
+Revision=0
+Status=656
+SubClassCode=0
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=4107
+clock=0
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+fake_mem=false
+pio_addr=8796093677568
+pio_latency=1000
+pio_size=393216
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[9]
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848432
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[20]
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848304
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[21]
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848569
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[10]
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848451
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[12]
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848515
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[13]
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848579
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[14]
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848643
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[15]
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848707
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[16]
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848771
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[17]
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848835
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[18]
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848899
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[19]
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615850617
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[11]
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848891
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[8]
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848816
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[3]
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848696
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[4]
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848936
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[5]
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848680
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[6]
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+fake_mem=false
+pio_addr=8804615848944
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[7]
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+pio_latency=1000
+platform=system.tsunami
+system=system
+pio=system.iobus.port[22]
+
+[system.tsunami.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=0
+disks=system.disk0 system.disk2
+io_shift=0
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+system=system
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
+pio=system.iobus.port[26]
+
+[system.tsunami.io]
+type=TsunamiIO
+frequency=976562500
+pio_addr=8804615847936
+pio_latency=1000
+platform=system.tsunami
+system=system
+time=Thu Jan  1 00:00:00 2009
+tsunami=system.tsunami
+year_is_bcd=false
+pio=system.iobus.port[23]
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=1000
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+pio=system.iobus.port[2]
+
+[system.tsunami.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.tsunami
+size=16777216
+system=system
+pio=system.iobus.default
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[24]
+
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
new file mode 100755
index 000000000..0bcb6e870
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
new file mode 100755
index 000000000..2911b29fc
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -0,0 +1,12 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 06:11:15
+gem5 executing on zizzer
+command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
+Global frequency set at 1000000000000 ticks per second
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 1858873594500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
new file mode 100644
index 000000000..de8941321
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -0,0 +1,916 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  1.858874                       # Number of seconds simulated
+sim_ticks                                1858873594500                       # Number of ticks simulated
+final_tick                               1858873594500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 134152                       # Simulator instruction rate (inst/s)
+host_tick_rate                             4696460042                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295432                       # Number of bytes of host memory used
+host_seconds                                   395.80                       # Real time elapsed on the host
+sim_insts                                    53097697                       # Number of instructions simulated
+system.physmem.bytes_read                    29819840                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1062784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10193408                       # Number of bytes written to this memory
+system.physmem.num_reads                       465935                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      159272                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       16041887                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    571735                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5483648                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      21525535                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        391354                       # number of replacements
+system.l2c.tagsinuse                     34898.086140                       # Cycle average of tags in use
+system.l2c.total_refs                         2410581                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        424231                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          5.682237                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    5619831000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                 12293.296692                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 22604.789448                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.187581                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.344922                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    1801188                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1801188                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   835090                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835090                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                      16                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  16                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0                     2                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0                   183163                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               183163                       # number of ReadExReq hits
+system.l2c.demand_hits::0                     1984351                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1984351                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    1984351                       # number of overall hits
+system.l2c.overall_hits::1                          0                       # number of overall hits
+system.l2c.overall_hits::total                1984351                       # number of overall hits
+system.l2c.ReadReq_misses::0                   308072                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               308072                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                    33                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                33                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                 116926                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             116926                       # number of ReadExReq misses
+system.l2c.demand_misses::0                    424998                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                424998                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   424998                       # number of overall misses
+system.l2c.overall_misses::1                        0                       # number of overall misses
+system.l2c.overall_misses::total               424998                       # number of overall misses
+system.l2c.ReadReq_miss_latency           16035098000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency             425000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          6133668000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency            22168766000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency           22168766000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                2109260                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2109260                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               835090                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           835090                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                  49                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              49                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0                 2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               300089                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           300089                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                 2409349                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2409349                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                2409349                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2409349                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.146057                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.673469                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.389638                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.176395                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.176395                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   52049.838999                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 12878.787879                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52457.691189                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    52162.047821                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   52162.047821                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                          117760                       # number of writebacks
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                 308072                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                  33                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               116926                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  424998                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 424998                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency      12331827500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency       1380000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     4711722000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency       17043549500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency      17043549500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency    810479000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1115452498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency   1925931498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.146057                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.673469                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.389638                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0          0.176395                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         0.176395                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40029.043535                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 41818.181818                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40296.614953                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40102.658130                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40102.658130                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.iocache.replacements                     41685                       # number of replacements
+system.iocache.tagsinuse                     1.268274                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle              1708338694000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 1.268274                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.079267                       # Average percentage of cache occupancy
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.ReadReq_misses::1                  173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                41725                       # number of overall misses
+system.iocache.overall_misses::total            41725                       # number of overall misses
+system.iocache.ReadReq_miss_latency          19939998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency       5722643806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency         5742583804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency        5742583804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115260.104046                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137722.463564                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137629.330234                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137629.330234                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs      64634068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10468                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6174.442874                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks                       41512                       # number of writebacks
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.ReadReq_mshr_miss_latency     10943998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3561790996                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3572734994                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3572734994                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85718.882268                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85625.763787                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85625.763787                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     10138302                       # DTB read hits
+system.cpu.dtb.read_misses                      46569                       # DTB read misses
+system.cpu.dtb.read_acv                           588                       # DTB read access violations
+system.cpu.dtb.read_accesses                   971478                       # DTB read accesses
+system.cpu.dtb.write_hits                     6627002                       # DTB write hits
+system.cpu.dtb.write_misses                     12216                       # DTB write misses
+system.cpu.dtb.write_acv                          416                       # DTB write access violations
+system.cpu.dtb.write_accesses                  347261                       # DTB write accesses
+system.cpu.dtb.data_hits                     16765304                       # DTB hits
+system.cpu.dtb.data_misses                      58785                       # DTB misses
+system.cpu.dtb.data_acv                          1004                       # DTB access violations
+system.cpu.dtb.data_accesses                  1318739                       # DTB accesses
+system.cpu.itb.fetch_hits                     1327158                       # ITB hits
+system.cpu.itb.fetch_misses                     39816                       # ITB misses
+system.cpu.itb.fetch_acv                         1096                       # ITB acv
+system.cpu.itb.fetch_accesses                 1366974                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.numCycles                        116293341                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 14403200                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           12045652                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             530716                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              12993662                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  6702662                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                   972407                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               45058                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           29094387                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       73505774                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14403200                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            7675069                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      14268794                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2359863                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               36645005                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                31889                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        259043                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       335706                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          129                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9051868                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                321893                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           82174946                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.894503                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.211429                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 67906152     82.64%     82.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1023009      1.24%     83.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2022244      2.46%     86.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   965640      1.18%     87.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2953506      3.59%     91.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   686113      0.83%     91.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   790817      0.96%     92.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1067854      1.30%     94.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4759611      5.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total             82174946                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.123852                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.632072                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 30353273                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              36299982                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  13051372                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                972104                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1498214                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               610003                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42096                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               71896046                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                128197                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1498214                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 31555942                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12820674                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       19773044                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  12199083                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4327987                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               67967172                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7022                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 504365                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1538985                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            45476353                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              82567749                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         82088652                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            479097                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38265070                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  7211275                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1700634                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         251496                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12093975                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10722948                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6992313                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1255970                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           835280                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   59689379                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2116105                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57965210                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            118570                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8314088                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4277616                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1448303                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      82174946                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.705388                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.352124                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            56717955     69.02%     69.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            11192734     13.62%     82.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5489796      6.68%     89.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3501881      4.26%     93.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2637968      3.21%     96.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1562716      1.90%     98.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              689256      0.84%     99.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              274867      0.33%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              107773      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        82174946                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   67060      8.71%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 379426     49.28%     57.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                323507     42.01%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass              7281      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39583689     68.29%     68.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                62189      0.11%     68.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               25607      0.04%     68.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10615864     18.31%     86.77% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6714571     11.58%     98.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             952373      1.64%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total               57965210                       # Type of FU issued
+system.cpu.iq.rate                           0.498440                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      769993                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013284                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          198301844                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          69800593                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     56410393                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              692084                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             332994                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       328299                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               58364794                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  363128                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           575597                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      1608607                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        13533                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14401                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       599018                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads        18904                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        170936                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                1498214                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8974617                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                617389                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            65429620                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            865390                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10722948                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6992313                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1869565                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 485054                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 15735                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14401                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         385242                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       382803                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               768045                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              57270091                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10215279                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            695118                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                       3624136                       # number of nop insts executed
+system.cpu.iew.exec_refs                     16869985                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  9097351                       # Number of branches executed
+system.cpu.iew.exec_stores                    6654706                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.492462                       # Inst execution rate
+system.cpu.iew.wb_sent                       56872608                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56738692                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28028831                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  37767423                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       0.487893                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.742143                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       56292492                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts         9013620                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          667802                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            700532                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     80676732                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.697754                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.611305                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     59494729     73.74%     73.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8894659     11.03%     84.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4715834      5.85%     90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2613071      3.24%     93.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1534221      1.90%     95.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       644957      0.80%     96.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       475888      0.59%     97.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       517029      0.64%     97.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1786344      2.21%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     80676732                       # Number of insts commited each cycle
+system.cpu.commit.count                      56292492                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       15507636                       # Number of memory references committed
+system.cpu.commit.loads                       9114341                       # Number of loads committed
+system.cpu.commit.membars                      227905                       # Number of memory barriers committed
+system.cpu.commit.branches                    8463183                       # Number of branches committed
+system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  52130666                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               744656                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               1786344                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    143945413                       # The number of ROB reads
+system.cpu.rob.rob_writes                   132113260                       # The number of ROB writes
+system.cpu.timesIdled                         1256827                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        34118395                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3601447413                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    53097697                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              53097697                       # Number of Instructions Simulated
+system.cpu.cpi                               2.190177                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.190177                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.456584                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.456584                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 75078413                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40965985                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166494                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167403                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 1996876                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 949968                       # number of misc regfile writes
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu.icache.replacements                1004954                       # number of replacements
+system.cpu.icache.tagsinuse                509.962774                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7985922                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1005463                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.942532                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            23358245000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            509.962774                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.996021                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0             7985923                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7985923                       # number of ReadReq hits
+system.cpu.icache.demand_hits::0              7985923                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7985923                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0             7985923                       # number of overall hits
+system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::total         7985923                       # number of overall hits
+system.cpu.icache.ReadReq_misses::0           1065945                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1065945                       # number of ReadReq misses
+system.cpu.icache.demand_misses::0            1065945                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1065945                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0           1065945                       # number of overall misses
+system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::total       1065945                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency    15930410995                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency     15930410995                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency    15930410995                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0         9051868                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9051868                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0          9051868                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9051868                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0         9051868                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9051868                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0       0.117760                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0        0.117760                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::0       0.117760                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::0 14944.871447                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::0 14944.871447                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 14944.871447                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      1290996                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               122                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 10581.934426                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                      235                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits             60269                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits              60269                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits             60269                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses         1005676                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses          1005676                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses         1005676                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency  12050431496                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency  12050431496                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency  12050431496                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.111101                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.111101                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.111101                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.419284                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11982.419284                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11982.419284                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1403374                       # number of replacements
+system.cpu.dcache.tagsinuse                511.996006                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 12090411                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1403886                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   8.612103                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               19221000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0            511.996006                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999992                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0             7456106                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7456106                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0            4221921                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4221921                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0        192075                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       192075                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0         220104                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       220104                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0             11678027                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11678027                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0            11678027                       # number of overall hits
+system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11678027                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::0           1809770                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1809770                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0          1936125                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1936125                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0        22580                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22580                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::0            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::0            3745895                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3745895                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0           3745895                       # number of overall misses
+system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3745895                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    38933932500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   57800126852                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency    338100500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency        28500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency     96734059352                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    96734059352                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0         9265876                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9265876                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0        6158046                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6158046                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0       214655                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       214655                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0       220106                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       220106                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0         15423922                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15423922                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0        15423922                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15423922                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0       0.195316                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0      0.314406                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.105192                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::0     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::0        0.242863                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0       0.242863                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::0 21513.193665                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 29853.509898                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14973.449956                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0        14250                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 25824.017852                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 25824.017852                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    917367309                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       193500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            103073                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  8900.170840                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   834855                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            722036                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1637277                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits         5104                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            2359313                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           2359313                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1087734                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         298848                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses        17476                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1386582                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1386582                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  24802725500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   8508331309                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    206132500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  33311056809                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  33311056809                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency    905005000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1234795498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency   2139800498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.117391                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048530                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.081414                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.089898                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.089898                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22802.197504                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28470.430818                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11795.176242                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 24023.863579                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 24023.863579                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                     6436                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211595                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74877     40.96%     40.96% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     245      0.13%     41.09% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1882      1.03%     42.12% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105819     57.88%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182823                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73510     49.29%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      245      0.16%     49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1882      1.26%     50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73514     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149151                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1820223133000     97.92%     97.92% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                94250000      0.01%     97.93% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               384615500      0.02%     97.95% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             38170735500      2.05%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1858872734000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981743                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694715                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
+system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
+system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
+system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
+system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
+system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
+system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
+system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
+system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
+system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
+system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
+system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
+system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
+system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
+system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
+system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
+system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
+system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
+system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
+system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
+system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
+system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
+system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
+system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
+system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
+system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
+system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
+system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
+system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
+system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
+system.cpu.kern.syscall::total                    326                       # number of syscalls executed
+system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
+system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175482     91.19%     93.39% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6787      3.53%     96.92% # number of callpals executed
+system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
+system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
+system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
+system.cpu.kern.callpal::rti                     5217      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
+system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
+system.cpu.kern.callpal::total                 192442                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5953                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2106                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1907                      
+system.cpu.kern.mode_good::user                  1737                      
+system.cpu.kern.mode_good::idle                   170                      
+system.cpu.kern.mode_switch_good::kernel     0.320343                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle       0.080722                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      1.401064                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29154617000      1.57%      1.57% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2680769000      0.14%      1.71% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1827037340000     98.29%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
new file mode 100644
index 000000000..1b4012ef1
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
@@ -0,0 +1,108 @@
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+
Got Configuration 623
+
memsize 8000000 pages 4000 
+
First free page after ROM 0xFFFFFC0000018000
+
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+
CPU Clock at 2000 MHz IntrClockFrequency=1024 
+
Booting with 1 processor(s) 
+
KSP: 0x20043FE8 PTBR 0x20
+
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
+
Memory cluster 0 [0 - 392]
+
Memory cluster 1 [392 - 15992]
+
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 
+
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
+
unix_boot_mem ends at FFFFFC0000076000 
+
k_argc = 0 
+
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
CallbackFixup 0 18000, t7=FFFFFC000070C000
+
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
+
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
+
Command line: root=/dev/hda1 console=ttyS0
+
memcluster 0, usage 1, start        0, end      392
+
memcluster 1, usage 0, start      392, end    16384
+
freeing pages 1069:16384
+
reserving pages 1069:1070
+
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
+
SMP: 1 CPUs probed -- cpu_present_mask = 1
+
Built 1 zonelists
+
Kernel command line: root=/dev/hda1 console=ttyS0
+
PID hash table entries: 1024 (order: 10, 32768 bytes)
+
Using epoch = 1900
+
Console: colour dummy device 80x25
+
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
+
Mount-cache hash table entries: 512
+
SMP mode deactivated.
+
Brought up 1 CPUs
+
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
+
NET: Registered protocol family 16
+
EISA bus registered
+
pci: enabling save/restore of SRM state
+
SCSI subsystem initialized
+
srm_env: version 0.0.5 loaded successfully
+
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+
Initializing Cryptographic API
+
rtc: Standard PC (1900) epoch (1900) detected
+
Real Time Clock Driver v1.12
+
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
+
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
io scheduler noop registered
+
io scheduler anticipatory registered
+
io scheduler deadline registered
+
io scheduler cfq registered
+
loop: loaded (max 8 devices)
+
nbd: registered device at major 43
+
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
PCI: Setting latency timer of device 0000:00:01.0 to 64
+
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
+
eth0: enabling optical transceiver
+
eth0: using 64 bit addressing.
+
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
tun: Universal TUN/TAP device driver, 1.6
+
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+
PIIX4: IDE controller at PCI slot 0000:00:00.0
+
PIIX4: chipset revision 0
+
PIIX4: 100% native mode on irq 31
+
PCI: Setting latency timer of device 0000:00:00.0 to 64
+
    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
+
    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
+
hda: M5 IDE Disk, ATA DISK drive
+
hdb: M5 IDE Disk, ATA DISK drive
+
ide0 at 0x8410-0x8417,0x8422 on irq 31
+
hda: max request size: 128KiB
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
+
hda: cache flushes not supported
+
 hda: hda1
+
hdb: max request size: 128KiB
+
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
hdb: cache flushes not supported
+
 hdb: unknown partition table
+
mice: PS/2 mouse device common for all mice
+
NET: Registered protocol family 2
+
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
TCP: Hash tables configured (established 16384 bind 16384)
+
TCP reno registered
+
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
+
ip_tables: (C) 2000-2002 Netfilter core team
+
arp_tables: (C) 2002 David S. Miller
+
TCP bic registered
+
Initializing IPsec netlink socket
+
NET: Registered protocol family 1
+
NET: Registered protocol family 17
+
NET: Registered protocol family 15
+
Bridge firewalling registered
+
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
+
All bugs added by David S. Miller <davem@redhat.com>
+
VFS: Mounted root (ext2 filesystem) readonly.
+
Freeing unused kernel memory: 224k freed
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...