Stats: Update stats for use of two-level builder

This patch updates the name of the l2 stats.

1 files changed, 192 insertions, 192 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index ab9c5cd0a..14c60d4c9 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -38,198 +38,198 @@ system.physmem.bw_total::cpu.inst              519335                       # To
 system.physmem.bw_total::cpu.data            13323249                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide          1420330                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               19289275                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        338398                       # number of replacements
-system.l2c.tagsinuse                     65348.140689                       # Cycle average of tags in use
-system.l2c.total_refs                         2559915                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        403567                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.343222                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    4870006000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        53844.889123                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           5363.726417                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6139.525149                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.821608                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.081844                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.093682                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.997133                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.inst             1007783                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              827771                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1835554                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          841020                       # number of Writeback hits
-system.l2c.Writeback_hits::total               841020                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               31                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  31                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data              3                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            185546                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               185546                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.inst              1007783                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1013317                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2021100                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.inst             1007783                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1013317                       # number of overall hits
-system.l2c.overall_hits::total                2021100                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.inst             15155                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data            273854                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               289009                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data             54                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                54                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          115395                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115395                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.inst              15155                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             389249                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                404404                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.inst             15155                       # number of overall misses
-system.l2c.overall_misses::cpu.data            389249                       # number of overall misses
-system.l2c.overall_misses::total               404404                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.inst    807128998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data  14259763500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    15066892498                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       376500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       376500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6225363497                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6225363497                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.inst    807128998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data  20485126997                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21292255995                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.inst    807128998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data  20485126997                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21292255995                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.inst         1022938                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1101625                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2124563                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       841020                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           841020                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data           85                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              85                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             5                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        300941                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           300941                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.inst          1022938                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1402566                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2425504                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.inst         1022938                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1402566                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2425504                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.014815                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.248591                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.136032                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.635294                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.635294                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.383447                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.383447                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.inst        0.014815                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.277526                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.166730                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.inst       0.014815                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.277526                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.166730                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.264467                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52070.678172                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52132.952600                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data  6972.222222                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6972.222222                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 53948.294961                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53948.294961                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53258.264467                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52627.307962                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52650.952995                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53258.264467                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52627.307962                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52650.952995                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               75968                       # number of writebacks
-system.l2c.writebacks::total                    75968                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.inst        15154                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data       273854                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          289008                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data           54                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           54                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       115395                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        115395                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         15154                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        389249                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           404403                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        15154                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       389249                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          404403                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    621904998                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data  10983272500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11605177498                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      2245000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      2245000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data        80000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        80000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4831334497                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4831334497                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    621904998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data  15814606997                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16436511995                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    621904998                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data  15814606997                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16436511995                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data   1333882500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1333882500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1884635500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1884635500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data   3218518000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   3218518000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.248591                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.136032                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.635294                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.635294                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383447                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.383447                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.277526                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.166729                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.277526                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.166729                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40155.211960                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41574.074074                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41867.797539                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40628.510277                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40643.892343                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40628.510277                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40643.892343                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                        338398                       # number of replacements
+system.cpu.l2cache.tagsinuse                     65348.140689                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                         2559915                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                        403567                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                          6.343222                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                    4870006000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks        53844.889123                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst           5363.726417                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data           6139.525149                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks           0.821608                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst             0.081844                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data             0.093682                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total                0.997133                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst             1007783                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data              827771                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total                1835554                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          841020                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total               841020                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data               31                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total                  31                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data              3                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            185546                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total               185546                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst              1007783                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data              1013317                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total                 2021100                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst             1007783                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data             1013317                       # number of overall hits
+system.cpu.l2cache.overall_hits::total                2021100                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst             15155                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data            273854                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total               289009                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data             54                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total                54                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          115395                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total             115395                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst              15155                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data             389249                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total                404404                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst             15155                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data            389249                       # number of overall misses
+system.cpu.l2cache.overall_misses::total               404404                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    807128998                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  14259763500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    15066892498                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       376500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       376500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6225363497                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   6225363497                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    807128998                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  20485126997                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     21292255995                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    807128998                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  20485126997                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    21292255995                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1022938                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data         1101625                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total            2124563                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       841020                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           841020                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           85                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total              85                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total             5                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        300941                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           300941                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          1022938                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          1402566                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total             2425504                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1022938                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1402566                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total            2425504                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst       0.014815                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data       0.248591                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total          0.136032                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.635294                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total       0.635294                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383447                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total        0.383447                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst        0.014815                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data        0.277526                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total           0.166730                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst       0.014815                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data       0.277526                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total          0.166730                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.264467                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52070.678172                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52132.952600                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  6972.222222                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  6972.222222                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53948.294961                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53948.294961                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.264467                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52627.307962                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52650.952995                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.264467                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52627.307962                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52650.952995                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets                      0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                              0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                             0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks               75968                       # number of writebacks
+system.cpu.l2cache.writebacks::total                    75968                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total                 1                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15154                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273854                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          289008                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           54                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           54                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115395                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        115395                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         15154                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        389249                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total           404403                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15154                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389249                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          404403                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    621904998                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10983272500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  11605177498                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2245000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2245000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        80000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        80000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4831334497                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4831334497                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    621904998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15814606997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  16436511995                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    621904998                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15814606997                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  16436511995                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333882500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333882500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1884635500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1884635500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3218518000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3218518000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248591                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136032                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.635294                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.635294                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383447                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383447                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277526                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total      0.166729                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277526                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.166729                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40155.211960                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41574.074074                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41867.797539                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40628.510277                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40643.892343                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40628.510277                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40643.892343                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.tagsinuse                     1.309507                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.