diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
| commit | b1a58933e07d7af0eb5f43942f8ad9bc93f28039 (patch) | |
| tree | 21f36b849ba0aed06ec18ed45aef46feeacd7532 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 630068be6f7b6dc5c612867c764c37e41fd90a4a (diff) | |
| download | gem5-b1a58933e07d7af0eb5f43942f8ad9bc93f28039.tar.xz | |
stats: update stats for icache change not allowing dirty data
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
6 files changed, 2011 insertions, 2003 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 1c28eff64..028711e47 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1005,7 +1005,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 11f244941..acdd4bc1c 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 11:07:21 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 22:30:48 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 112168000 -Exiting @ tick 1900530800500 because m5_exit instruction encountered +Exiting @ tick 1900530295500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 3f76d2026..a7a1d7396 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.900531 # Number of seconds simulated -sim_ticks 1900530800500 # Number of ticks simulated -final_tick 1900530800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.900530 # Number of seconds simulated +sim_ticks 1900530295500 # Number of ticks simulated +final_tick 1900530295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119697 # Simulator instruction rate (inst/s) -host_op_rate 119697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3968630665 # Simulator tick rate (ticks/s) -host_mem_usage 303044 # Number of bytes of host memory used -host_seconds 478.89 # Real time elapsed on the host -sim_insts 57321719 # Number of instructions simulated -sim_ops 57321719 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 875648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24657536 # Number of bytes read from this memory +host_inst_rate 128893 # Simulator instruction rate (inst/s) +host_op_rate 128893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4273489918 # Simulator tick rate (ticks/s) +host_mem_usage 307500 # Number of bytes of host memory used +host_seconds 444.73 # Real time elapsed on the host +sim_insts 57321882 # Number of instructions simulated +sim_ops 57321882 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 875200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24658176 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 107456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 693056 # Number of bytes read from this memory -system.physmem.bytes_read::total 28984512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 875648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 107456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 983104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7921792 # Number of bytes written to this memory -system.physmem.bytes_written::total 7921792 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385274 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 108032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 692736 # Number of bytes read from this memory +system.physmem.bytes_read::total 28984960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 875200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 108032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 983232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7922432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7922432 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385284 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1679 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10829 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452883 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123778 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123778 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 460739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12974026 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1688 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10824 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452890 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123788 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123788 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 460503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12974366 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1394777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 364664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15250746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 460739 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4168200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4168200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4168200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 460739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12974026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 364496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15250986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 460503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4168538 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4168538 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4168538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 460503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12974366 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1394777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19418945 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 345959 # number of replacements -system.l2c.tagsinuse 65264.030293 # Cycle average of tags in use -system.l2c.total_refs 2564962 # Total number of references to valid blocks. -system.l2c.sampled_refs 411131 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.238795 # Average number of references to valid blocks. +system.physmem.bw_total::cpu1.inst 56843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19419523 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 345965 # number of replacements +system.l2c.tagsinuse 65264.028554 # Cycle average of tags in use +system.l2c.total_refs 2565305 # Total number of references to valid blocks. +system.l2c.sampled_refs 411137 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.239538 # Average number of references to valid blocks. system.l2c.warmup_cycle 6370050000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53566.099176 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5313.179425 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6099.564968 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 209.813021 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 75.373703 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.817354 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.081073 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093072 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003201 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 53566.065326 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5313.128544 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6099.641645 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 209.824884 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 75.368156 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.817353 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.081072 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.093073 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003202 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.001150 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.995850 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 777532 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 689515 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 314287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 100987 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1882321 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 806312 # number of Writeback hits -system.l2c.Writeback_hits::total 806312 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 440 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 616 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 81 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 128023 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 44351 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172374 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 777532 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 817538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 314287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 145338 # number of demand (read+write) hits -system.l2c.demand_hits::total 2054695 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 777532 # number of overall hits -system.l2c.overall_hits::cpu0.data 817538 # number of overall hits -system.l2c.overall_hits::cpu1.inst 314287 # number of overall hits -system.l2c.overall_hits::cpu1.data 145338 # number of overall hits -system.l2c.overall_hits::total 2054695 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13684 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272967 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1696 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 861 # number of ReadReq misses +system.l2c.ReadReq_hits::cpu0.inst 778193 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 689575 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 314248 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 100958 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1882974 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 806039 # number of Writeback hits +system.l2c.Writeback_hits::total 806039 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 439 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 613 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 128167 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 44386 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172553 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 778193 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 817742 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 314248 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 145344 # number of demand (read+write) hits +system.l2c.demand_hits::total 2055527 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 778193 # number of overall hits +system.l2c.overall_hits::cpu0.data 817742 # number of overall hits +system.l2c.overall_hits::cpu1.inst 314248 # number of overall hits +system.l2c.overall_hits::cpu1.data 145344 # number of overall hits +system.l2c.overall_hits::total 2055527 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13677 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272973 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1705 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 853 # number of ReadReq misses system.l2c.ReadReq_misses::total 289208 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2867 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1568 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4435 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 726 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2871 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1574 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4445 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 724 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 747 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1473 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113091 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 10063 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123154 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13684 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386058 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1696 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10924 # number of demand (read+write) misses -system.l2c.demand_misses::total 412362 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13684 # number of overall misses -system.l2c.overall_misses::cpu0.data 386058 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1696 # number of overall misses -system.l2c.overall_misses::cpu1.data 10924 # number of overall misses -system.l2c.overall_misses::total 412362 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 728665998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14214168999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 90803000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 47077499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15080715496 # number of ReadReq miss cycles +system.l2c.SCUpgradeReq_misses::total 1471 # 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number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14214430499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 91270500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 46668499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15080752496 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 19661414 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 22245414 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2793000 # number of SCUpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 19818914 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 22402914 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2792500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000 # 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Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1711281170000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.465240 # Average occupied blocks per requestor +system.iocache.occ_blocks::tsunami.ide 0.465235 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.029077 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses @@ -366,12 +366,12 @@ system.iocache.overall_misses::tsunami.ide 41730 # system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21238998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21238998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7637775806 # 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number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1078.170885 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1074.524609 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -416,12 +416,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41730 system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476916000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5476916000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5488898000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5488898000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5488898000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5488898000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476969000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5476969000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5488951000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5488951000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5488951000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5488951000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -432,12 +432,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131809.997112 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131809.997112 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8334313 # DTB read hits -system.cpu0.dtb.read_misses 29661 # DTB read misses -system.cpu0.dtb.read_acv 416 # DTB read access violations -system.cpu0.dtb.read_accesses 650050 # DTB read accesses -system.cpu0.dtb.write_hits 5360515 # DTB write hits -system.cpu0.dtb.write_misses 6017 # DTB write misses -system.cpu0.dtb.write_acv 275 # DTB write access violations -system.cpu0.dtb.write_accesses 211537 # DTB write accesses -system.cpu0.dtb.data_hits 13694828 # DTB hits -system.cpu0.dtb.data_misses 35678 # DTB misses -system.cpu0.dtb.data_acv 691 # DTB access violations -system.cpu0.dtb.data_accesses 861587 # DTB accesses -system.cpu0.itb.fetch_hits 972456 # ITB hits -system.cpu0.itb.fetch_misses 29747 # ITB misses -system.cpu0.itb.fetch_acv 802 # ITB acv -system.cpu0.itb.fetch_accesses 1002203 # ITB accesses +system.cpu0.dtb.read_hits 8334041 # DTB read hits +system.cpu0.dtb.read_misses 29708 # DTB read misses +system.cpu0.dtb.read_acv 432 # DTB read access violations +system.cpu0.dtb.read_accesses 650283 # DTB read accesses +system.cpu0.dtb.write_hits 5360343 # DTB write hits +system.cpu0.dtb.write_misses 6029 # DTB write misses +system.cpu0.dtb.write_acv 281 # DTB write access violations +system.cpu0.dtb.write_accesses 211361 # DTB write accesses +system.cpu0.dtb.data_hits 13694384 # DTB hits +system.cpu0.dtb.data_misses 35737 # DTB misses +system.cpu0.dtb.data_acv 713 # DTB access violations +system.cpu0.dtb.data_accesses 861644 # DTB accesses +system.cpu0.itb.fetch_hits 975254 # ITB hits +system.cpu0.itb.fetch_misses 26821 # ITB misses +system.cpu0.itb.fetch_acv 801 # ITB acv +system.cpu0.itb.fetch_accesses 1002075 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,143 +483,143 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 107494535 # number of cpu cycles simulated +system.cpu0.numCycles 107505653 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 11769770 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 9862090 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 345528 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8388023 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5075121 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11783453 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9875598 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 345606 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8356965 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5072042 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 768289 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 29261 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 25151812 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 60423976 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11769770 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5843410 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11477495 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1678868 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36441754 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 35468 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 189532 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 310248 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7504127 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 232204 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 74712100 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.808758 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.135218 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 768478 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 29315 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 25158431 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60438649 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11783453 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5840520 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11478099 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1678793 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36446213 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 35059 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 187963 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 310129 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7506544 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 232672 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74721559 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.808852 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.135528 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63234605 84.64% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 741221 0.99% 85.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1559530 2.09% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686170 0.92% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2492076 3.34% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 531561 0.71% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 568906 0.76% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 718608 0.96% 94.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4179423 5.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63243460 84.64% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 740935 0.99% 85.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1559450 2.09% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686263 0.92% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2492339 3.34% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 528695 0.71% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568727 0.76% 93.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 718688 0.96% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4183002 5.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74712100 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.109492 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.562112 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26235752 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36073897 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10433111 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 896014 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1073325 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 504398 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 32602 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 59387121 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 93497 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1073325 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27172169 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15317742 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17291837 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9793019 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4064006 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 56407383 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7139 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 656540 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1492805 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 37953017 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 68861567 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 68508934 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 352633 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33050954 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4902063 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1333181 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 200244 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10589201 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8773580 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5638577 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132250 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 738910 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50116652 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1669804 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 48856794 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 108488 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5944129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3041029 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1132337 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 74712100 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.653934 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.297915 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74721559 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109608 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.562190 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26241114 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36078495 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10432905 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 895868 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1073176 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 504459 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32663 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 59394337 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 93513 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1073176 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27177088 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15322085 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17293060 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9793199 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4062949 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56409108 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7164 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 656382 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1492215 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 37953965 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 68862069 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 68509500 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 352569 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33051447 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4902518 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1333146 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 200213 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10586539 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8773665 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5638420 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132750 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 738704 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50116530 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1671338 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 48856724 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 108345 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5942974 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3041199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1133867 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74721559 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.653850 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.297886 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52667189 70.49% 70.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10185163 13.63% 84.13% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4563652 6.11% 90.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2983683 3.99% 94.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2257783 3.02% 97.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1142078 1.53% 98.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 582516 0.78% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 283628 0.38% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 46408 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52677257 70.50% 70.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10184833 13.63% 84.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4563049 6.11% 90.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2984127 3.99% 94.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2257312 3.02% 97.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1142410 1.53% 98.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 582471 0.78% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 283512 0.38% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 46588 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74712100 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74721559 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 73121 11.93% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 287582 46.92% 58.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 252262 41.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 73394 11.97% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 287556 46.90% 58.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 252163 41.13% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 33934109 69.46% 69.47% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 53582 0.11% 69.58% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.58% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33933939 69.46% 69.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 53607 0.11% 69.57% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.57% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued @@ -646,116 +646,116 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8675974 17.76% 87.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5426955 11.11% 98.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 742930 1.52% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8676123 17.76% 87.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5426873 11.11% 98.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 742938 1.52% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 48856794 # Type of FU issued -system.cpu0.iq.rate 0.454505 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 612965 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012546 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 172645923 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57499135 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 47860626 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 501218 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 243758 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 236014 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 49202996 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 262296 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 518056 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 48856724 # Type of FU issued +system.cpu0.iq.rate 0.454457 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 613113 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012549 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 172655307 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57499462 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 47860573 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 501158 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 243682 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 236026 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 49203092 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 262278 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 518007 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1116510 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2510 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12661 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 476371 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1116542 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2532 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12656 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 476196 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18849 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 94368 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18844 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 94055 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1073325 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10798667 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 779958 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 54837290 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 559703 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8773580 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5638577 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1469305 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 544312 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 8344 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12661 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186183 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 327984 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 514167 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 48431427 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8385093 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 425367 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1073176 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10803844 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 780020 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54838073 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 560128 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8773665 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5638420 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1470903 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 544426 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 8361 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12656 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186168 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 328100 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 514268 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 48431034 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8384906 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 425690 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3050834 # number of nop insts executed -system.cpu0.iew.exec_refs 13764236 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7758760 # Number of branches executed -system.cpu0.iew.exec_stores 5379143 # Number of stores executed -system.cpu0.iew.exec_rate 0.450548 # Inst execution rate -system.cpu0.iew.wb_sent 48183951 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48096640 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24100280 # num instructions producing a value -system.cpu0.iew.wb_consumers 32401803 # num instructions consuming a value +system.cpu0.iew.exec_nop 3050205 # number of nop insts executed +system.cpu0.iew.exec_refs 13763900 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7759085 # Number of branches executed +system.cpu0.iew.exec_stores 5378994 # Number of stores executed +system.cpu0.iew.exec_rate 0.450498 # Inst execution rate +system.cpu0.iew.wb_sent 48183963 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48096599 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24100955 # num instructions producing a value +system.cpu0.iew.wb_consumers 32404442 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.447433 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743794 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.447387 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743755 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 48294177 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 48294177 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6449436 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 537467 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 480768 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 73638775 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.655825 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.560295 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 48294855 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 48294855 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6449755 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 537471 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 480800 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73648383 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.655749 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560255 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55222738 74.99% 74.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7735232 10.50% 85.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4278280 5.81% 91.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2283958 3.10% 94.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1242509 1.69% 96.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 524248 0.71% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 435052 0.59% 97.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 385141 0.52% 97.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1531617 2.08% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55233499 75.00% 75.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7733418 10.50% 85.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4278651 5.81% 91.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2283988 3.10% 94.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1242605 1.69% 96.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 524240 0.71% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 434900 0.59% 97.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 385505 0.52% 97.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1531577 2.08% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 73638775 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 48294177 # Number of instructions committed -system.cpu0.commit.committedOps 48294177 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73648383 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48294855 # Number of instructions committed +system.cpu0.commit.committedOps 48294855 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12819276 # Number of memory references committed -system.cpu0.commit.loads 7657070 # Number of loads committed +system.cpu0.commit.refs 12819347 # Number of memory references committed +system.cpu0.commit.loads 7657123 # Number of loads committed system.cpu0.commit.membars 181890 # Number of memory barriers committed -system.cpu0.commit.branches 7325526 # Number of branches committed +system.cpu0.commit.branches 7325688 # Number of branches committed system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 44748110 # Number of committed integer instructions. -system.cpu0.commit.function_calls 610965 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1531617 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 44748779 # Number of committed integer instructions. +system.cpu0.commit.function_calls 610967 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1531577 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126666255 # The number of ROB reads -system.cpu0.rob.rob_writes 110560293 # The number of ROB writes -system.cpu0.timesIdled 1221795 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32782435 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693291566 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 45532520 # Number of Instructions Simulated -system.cpu0.committedOps 45532520 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 45532520 # Number of Instructions Simulated -system.cpu0.cpi 2.360830 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.360830 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.423580 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.423580 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 63860317 # number of integer regfile reads -system.cpu0.int_regfile_writes 34945795 # number of integer regfile writes -system.cpu0.fp_regfile_reads 117013 # number of floating regfile reads -system.cpu0.fp_regfile_writes 117648 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1550179 # number of misc regfile reads -system.cpu0.misc_regfile_writes 750147 # number of misc regfile writes +system.cpu0.rob.rob_reads 126676900 # The number of ROB reads +system.cpu0.rob.rob_writes 110562172 # The number of ROB writes +system.cpu0.timesIdled 1222053 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32784094 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693280483 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 45533193 # Number of Instructions Simulated +system.cpu0.committedOps 45533193 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 45533193 # Number of Instructions Simulated +system.cpu0.cpi 2.361039 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.361039 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423542 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423542 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 63859411 # number of integer regfile reads +system.cpu0.int_regfile_writes 34945756 # number of integer regfile writes +system.cpu0.fp_regfile_reads 117042 # number of floating regfile reads +system.cpu0.fp_regfile_writes 117632 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1550181 # number of misc regfile reads +system.cpu0.misc_regfile_writes 750158 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -787,247 +787,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 790628 # number of replacements -system.cpu0.icache.tagsinuse 510.000717 # Cycle average of tags in use -system.cpu0.icache.total_refs 6669453 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 791140 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.430180 # Average number of references to valid blocks. +system.cpu0.icache.replacements 791282 # number of replacements +system.cpu0.icache.tagsinuse 510.000823 # Cycle average of tags in use +system.cpu0.icache.total_refs 6671308 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 791794 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.425560 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.000717 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 510.000823 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6669453 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6669453 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6669453 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6669453 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6669453 # number of overall hits -system.cpu0.icache.overall_hits::total 6669453 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 834673 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 834673 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 834673 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 834673 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 834673 # number of overall misses -system.cpu0.icache.overall_misses::total 834673 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13767352493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13767352493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13767352493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13767352493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13767352493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13767352493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7504126 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7504126 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7504126 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7504126 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7504126 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7504126 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111229 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111229 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111229 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111229 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111229 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111229 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16494.306744 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16494.306744 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1480996 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 6671308 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6671308 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6671308 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6671308 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6671308 # number of overall hits +system.cpu0.icache.overall_hits::total 6671308 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 835236 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 835236 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 835236 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 835236 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 835236 # number of overall misses +system.cpu0.icache.overall_misses::total 835236 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13775160993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13775160993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13775160993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13775160993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13775160993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13775160993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7506544 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7506544 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7506544 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7506544 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7506544 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7506544 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111268 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111268 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111268 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111268 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111268 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111268 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16492.537430 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16492.537430 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16492.537430 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16492.537430 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1463996 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 158 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 9141.950617 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 9265.797468 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 247 # number of writebacks -system.cpu0.icache.writebacks::total 247 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43336 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43336 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43336 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43336 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43336 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43336 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791337 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 791337 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 791337 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 791337 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 791337 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 791337 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10689365997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10689365997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10689365997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10689365997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10689365997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10689365997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105454 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105454 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105454 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43249 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43249 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43249 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791987 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 791987 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 791987 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 791987 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 791987 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 791987 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10696262996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10696262996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10696262996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10696262996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10696262996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10696262996 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105506 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105506 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105506 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13505.604254 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1206208 # number of replacements -system.cpu0.dcache.tagsinuse 505.878050 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9822290 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1206649 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.140139 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1206262 # number of replacements +system.cpu0.dcache.tagsinuse 505.874752 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9821312 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1206702 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.138971 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.878050 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.988043 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.988043 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6113680 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6113680 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3377171 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3377171 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150549 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 150549 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171656 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171656 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9490851 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9490851 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9490851 # number of overall hits -system.cpu0.dcache.overall_hits::total 9490851 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1478314 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1478314 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1593619 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1593619 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18637 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18637 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4699 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4699 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3071933 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3071933 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3071933 # number of overall misses -system.cpu0.dcache.overall_misses::total 3071933 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41272950000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41272950000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65317405497 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 65317405497 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315155000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 315155000 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 169186 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 176355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12562784 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12562784 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12562784 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12562784 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194720 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.194720 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320597 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.320597 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16898.821008 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14596.211154 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14596.211154 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34696.633989 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34696.633989 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 716919646 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 65430 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 65391 # 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number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14905 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4699 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4699 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212049 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1212049 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212049 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1212049 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25942792600 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25942792600 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8699231964 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8699231964 # 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mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088098 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026645 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026645 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096479 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096479 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771 # 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number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1212118 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25944695097 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25944695097 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8701407966 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8701407966 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186837501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186837501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 53961001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 53961001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34646103063 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34646103063 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34646103063 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34646103063 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918480000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918480000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327721998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327721998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246201998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246201998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126818 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126818 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050157 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050157 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088025 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088025 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026639 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026639 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096485 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096485 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26947.156257 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26947.156257 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34900.701375 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34900.701375 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.112968 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.112968 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11485.951682 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11485.951682 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1039,22 +1037,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2499316 # DTB read hits -system.cpu1.dtb.read_misses 12569 # DTB read misses +system.cpu1.dtb.read_hits 2497958 # DTB read hits +system.cpu1.dtb.read_misses 12385 # DTB read misses system.cpu1.dtb.read_acv 105 # DTB read access violations -system.cpu1.dtb.read_accesses 313735 # DTB read accesses -system.cpu1.dtb.write_hits 1734639 # DTB write hits -system.cpu1.dtb.write_misses 3525 # DTB write misses -system.cpu1.dtb.write_acv 140 # DTB write access violations -system.cpu1.dtb.write_accesses 132367 # DTB write accesses -system.cpu1.dtb.data_hits 4233955 # DTB hits -system.cpu1.dtb.data_misses 16094 # DTB misses -system.cpu1.dtb.data_acv 245 # DTB access violations -system.cpu1.dtb.data_accesses 446102 # DTB accesses -system.cpu1.itb.fetch_hits 489806 # ITB hits -system.cpu1.itb.fetch_misses 8851 # ITB misses -system.cpu1.itb.fetch_acv 360 # ITB acv -system.cpu1.itb.fetch_accesses 498657 # ITB accesses +system.cpu1.dtb.read_accesses 312687 # DTB read accesses +system.cpu1.dtb.write_hits 1734137 # DTB write hits +system.cpu1.dtb.write_misses 3404 # DTB write misses +system.cpu1.dtb.write_acv 137 # DTB write access violations +system.cpu1.dtb.write_accesses 131810 # DTB write accesses +system.cpu1.dtb.data_hits 4232095 # DTB hits +system.cpu1.dtb.data_misses 15789 # DTB misses +system.cpu1.dtb.data_acv 242 # DTB access violations +system.cpu1.dtb.data_accesses 444497 # DTB accesses +system.cpu1.itb.fetch_hits 488697 # ITB hits +system.cpu1.itb.fetch_misses 8773 # ITB misses +system.cpu1.itb.fetch_acv 366 # ITB acv +system.cpu1.itb.fetch_accesses 497470 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1067,144 +1065,144 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 22717311 # number of cpu cycles simulated +system.cpu1.numCycles 22715640 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 3442703 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2849702 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 108899 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 2361843 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1192387 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3441563 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2848590 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 108508 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2344214 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1191088 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 236332 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 10679 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 9037199 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16321027 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3442703 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1428719 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2924126 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 526603 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 8306285 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 28121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 87140 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 64229 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1963514 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 75345 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 20778311 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.785484 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.154367 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 236176 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 10617 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 9035553 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16314409 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3441563 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1427264 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2922038 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 525528 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 8308395 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 28029 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 86548 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 64086 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1962045 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 75286 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 20775175 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.785284 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.154306 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 17854185 85.93% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 203613 0.98% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 301133 1.45% 88.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 225724 1.09% 89.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 404540 1.95% 91.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 151692 0.73% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 164507 0.79% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 309022 1.49% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1163895 5.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 17853137 85.93% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 203247 0.98% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 300737 1.45% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 225181 1.08% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 403762 1.94% 91.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151742 0.73% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 164996 0.79% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 308573 1.49% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1163800 5.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 20778311 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.151545 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.718440 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8812255 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8762880 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2709089 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 172906 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 321180 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 151088 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 10133 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 16020033 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 29351 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 321180 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 9094333 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 882455 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6951469 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2594850 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 934022 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 14843152 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 114 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 83650 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 279958 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 9660007 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 17630674 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 17422680 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 207994 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 8331005 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1328994 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 594043 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 64597 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2775458 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2641121 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1825529 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 246953 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 159017 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12975245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 664400 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 12700763 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 35708 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1746535 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 829425 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 468662 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 20778311 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.611251 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.284414 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 20775175 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.151506 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.718202 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8809071 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8765539 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2707216 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 172890 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 320458 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 151147 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 10158 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 16014026 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 29482 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 320458 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 9091295 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 884150 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6951341 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2592964 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 934965 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14837454 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 127 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 84091 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 280482 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9656446 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 17623003 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17415204 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 207799 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 8330618 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1325820 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 594023 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 64559 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2775443 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2639269 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1825014 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 248716 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 160479 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12970444 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 664664 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12696455 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 35550 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1743951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 828101 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 468923 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 20775175 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.611136 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.284217 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 15115816 72.75% 72.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2653114 12.77% 85.52% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1112593 5.35% 90.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 724594 3.49% 94.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 603153 2.90% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 287847 1.39% 98.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 182303 0.88% 99.52% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 88112 0.42% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10779 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15113498 72.75% 72.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2653136 12.77% 85.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1113601 5.36% 90.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 723121 3.48% 94.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 602829 2.90% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 288191 1.39% 98.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 181892 0.88% 99.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 88125 0.42% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10782 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 20778311 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 20775175 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3869 1.53% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 134765 53.16% 54.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 114892 45.32% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3857 1.52% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 134714 53.16% 54.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 114823 45.31% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7927502 62.42% 62.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 20764 0.16% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10543 0.08% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7925481 62.42% 62.45% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 20760 0.16% 62.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10544 0.08% 62.69% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued @@ -1230,357 +1228,355 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2623377 20.66% 83.35% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1764952 13.90% 97.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 349391 2.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2621698 20.65% 83.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1764339 13.90% 97.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 349399 2.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 12700763 # Type of FU issued -system.cpu1.iq.rate 0.559079 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 253526 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 46169663 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15243166 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 12341001 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 299407 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 145151 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 140846 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 12794667 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 156799 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 115193 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12696455 # Type of FU issued +system.cpu1.iq.rate 0.558930 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 253394 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019958 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 46157750 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15236198 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 12337265 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 299278 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 145041 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 140795 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12790304 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 156722 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 115188 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 347930 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 808 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2222 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 153073 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 346106 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 806 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2268 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 152574 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 370 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 11635 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 376 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 11381 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 321180 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 537224 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 73444 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 14366092 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 206312 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2641121 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1825529 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 596088 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 55197 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6016 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2222 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 53937 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 130013 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 183950 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 12579473 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2523314 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 121289 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 320458 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 536973 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 73252 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 14361364 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 205800 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2639269 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1825014 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 596393 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 55379 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 5710 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2268 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 53644 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 129908 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 183552 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12575424 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2521777 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 121030 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 726447 # number of nop insts executed -system.cpu1.iew.exec_refs 4269906 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1887172 # Number of branches executed -system.cpu1.iew.exec_stores 1746592 # Number of stores executed -system.cpu1.iew.exec_rate 0.553740 # Inst execution rate -system.cpu1.iew.wb_sent 12515990 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 12481847 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5700900 # num instructions producing a value -system.cpu1.iew.wb_consumers 8040202 # num instructions consuming a value +system.cpu1.iew.exec_nop 726256 # number of nop insts executed +system.cpu1.iew.exec_refs 4267761 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1886646 # Number of branches executed +system.cpu1.iew.exec_stores 1745984 # Number of stores executed +system.cpu1.iew.exec_rate 0.553602 # Inst execution rate +system.cpu1.iew.wb_sent 12512047 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 12478060 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5698826 # num instructions producing a value +system.cpu1.iew.wb_consumers 8037620 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.549442 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709049 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.549316 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709019 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 12433159 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 12433159 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1857667 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 195738 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 173364 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 20457131 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.607767 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.554530 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 12432644 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 12432644 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1853978 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 195741 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 172939 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 20454717 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.607813 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.554325 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 15844350 77.45% 77.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2122437 10.38% 87.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 810532 3.96% 91.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 497134 2.43% 94.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 362445 1.77% 95.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 133722 0.65% 96.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 129038 0.63% 97.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 154146 0.75% 98.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 403327 1.97% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 15840554 77.44% 77.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2123906 10.38% 87.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 810748 3.96% 91.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 497113 2.43% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 362163 1.77% 95.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133438 0.65% 96.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 130960 0.64% 97.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 152379 0.74% 98.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 403456 1.97% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 20457131 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 12433159 # Number of instructions committed -system.cpu1.commit.committedOps 12433159 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 20454717 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 12432644 # Number of instructions committed +system.cpu1.commit.committedOps 12432644 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3965647 # Number of memory references committed -system.cpu1.commit.loads 2293191 # Number of loads committed -system.cpu1.commit.membars 64658 # Number of memory barriers committed -system.cpu1.commit.branches 1777478 # Number of branches committed +system.cpu1.commit.refs 3965603 # Number of memory references committed +system.cpu1.commit.loads 2293163 # Number of loads committed +system.cpu1.commit.membars 64660 # Number of memory barriers committed +system.cpu1.commit.branches 1777364 # Number of branches committed system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 11488003 # Number of committed integer instructions. +system.cpu1.commit.int_insts 11487490 # Number of committed integer instructions. system.cpu1.commit.function_calls 194670 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 403327 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 403456 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 34238592 # The number of ROB reads -system.cpu1.rob.rob_writes 28901418 # The number of ROB writes -system.cpu1.timesIdled 230949 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1939000 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3778341690 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 11789199 # Number of Instructions Simulated -system.cpu1.committedOps 11789199 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 11789199 # Number of Instructions Simulated -system.cpu1.cpi 1.926960 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.926960 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.518952 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.518952 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 16196586 # number of integer regfile reads -system.cpu1.int_regfile_writes 8796247 # number of integer regfile writes -system.cpu1.fp_regfile_reads 73611 # number of floating regfile reads -system.cpu1.fp_regfile_writes 74214 # number of floating regfile writes -system.cpu1.misc_regfile_reads 699711 # number of misc regfile reads -system.cpu1.misc_regfile_writes 299448 # number of misc regfile writes -system.cpu1.icache.replacements 315447 # number of replacements -system.cpu1.icache.tagsinuse 471.003081 # Cycle average of tags in use -system.cpu1.icache.total_refs 1635327 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 315959 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.175757 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 34231845 # The number of ROB reads +system.cpu1.rob.rob_writes 28892260 # The number of ROB writes +system.cpu1.timesIdled 230897 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1940465 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3778342351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11788689 # Number of Instructions Simulated +system.cpu1.committedOps 11788689 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 11788689 # Number of Instructions Simulated +system.cpu1.cpi 1.926901 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.926901 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.518968 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.518968 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 16191128 # number of integer regfile reads +system.cpu1.int_regfile_writes 8793643 # number of integer regfile writes +system.cpu1.fp_regfile_reads 73550 # number of floating regfile reads +system.cpu1.fp_regfile_writes 74224 # number of floating regfile writes +system.cpu1.misc_regfile_reads 699686 # number of misc regfile reads +system.cpu1.misc_regfile_writes 299450 # number of misc regfile writes +system.cpu1.icache.replacements 315418 # number of replacements +system.cpu1.icache.tagsinuse 471.006638 # Cycle average of tags in use +system.cpu1.icache.total_refs 1633897 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 315930 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.171706 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 471.003081 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919928 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919928 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1635327 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1635327 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1635327 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1635327 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1635327 # number of overall hits -system.cpu1.icache.overall_hits::total 1635327 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 328187 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 328187 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 328187 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 328187 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 328187 # number of overall misses -system.cpu1.icache.overall_misses::total 328187 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323842998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5323842998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5323842998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5323842998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5323842998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5323842998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1963514 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1963514 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1963514 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1963514 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1963514 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1963514 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167143 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.167143 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167143 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.167143 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167143 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.167143 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16221.980145 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16221.980145 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 228998 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 471.006638 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919935 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919935 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1633897 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1633897 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1633897 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1633897 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1633897 # number of overall hits +system.cpu1.icache.overall_hits::total 1633897 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 328148 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 328148 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 328148 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 328148 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 328148 # number of overall misses +system.cpu1.icache.overall_misses::total 328148 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323185498 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5323185498 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5323185498 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5323185498 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5323185498 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5323185498 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1962045 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1962045 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1962045 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1962045 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1962045 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1962045 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167248 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.167248 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167248 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.167248 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167248 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.167248 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.904439 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.904439 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 16221.904439 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 16221.904439 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 248998 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 37 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6189.135135 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5928.523810 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 38 # number of writebacks -system.cpu1.icache.writebacks::total 38 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12173 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12173 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12173 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12173 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12173 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12173 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316014 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316014 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316014 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316014 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316014 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316014 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183208998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183208998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183208998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4183208998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183208998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4183208998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.160943 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.160943 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.160943 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12162 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12162 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12162 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12162 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12162 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12162 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315986 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 315986 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 315986 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 315986 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 315986 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 315986 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183764998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183764998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183764998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4183764998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183764998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4183764998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.161049 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.161049 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.161049 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13240.349250 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 159076 # number of replacements -system.cpu1.dcache.tagsinuse 488.854290 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3388834 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 159588 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 21.234892 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 159031 # number of replacements +system.cpu1.dcache.tagsinuse 488.853384 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3387429 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 159543 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 21.232075 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 42819944000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 488.854290 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.954794 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.954794 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2022458 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2022458 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1251052 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1251052 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49972 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 49972 # number of LoadLockedReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 488.853384 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.954792 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.954792 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2021122 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2021122 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1250999 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1250999 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49956 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 49956 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3273510 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3273510 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3273510 # number of overall hits -system.cpu1.dcache.overall_hits::total 3273510 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 307183 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 307183 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 360837 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 360837 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8700 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8700 # 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number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471935334 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471935334 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78208000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78208000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52884501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52884501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3233201398 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3233201398 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3233201398 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3233201398 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18624000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18624000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400633000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400633000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419257000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419257000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047358 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047358 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038543 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038543 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130883 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130883 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094076 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094076 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043752 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043752 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15971.870394 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15971.870394 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23692.361357 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23692.361357 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10188.639917 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10188.639917 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10478.403210 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10478.403210 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1590,31 +1586,31 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 167510 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 167511 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 84509 58.04% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 145601 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 84510 58.04% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 145602 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862592276000 98.01% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96187500 0.01% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 394889000 0.02% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 155178500 0.01% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37157854000 1.96% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900396385000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1862592154000 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96215500 0.01% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 394866000 0.02% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 155183500 0.01% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37157983500 1.96% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900396402500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681016 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810063 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681008 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810058 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed @@ -1654,7 +1650,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # nu system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed -system.cpu0.kern.callpal::swpipl 138810 90.43% 92.75% # number of callpals executed +system.cpu0.kern.callpal::swpipl 138811 90.43% 92.75% # number of callpals executed system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed @@ -1663,44 +1659,44 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.90% # nu system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 153507 # number of callpals executed +system.cpu0.kern.callpal::total 153508 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1099 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1098 -system.cpu0.kern.mode_good::user 1098 +system.cpu0.kern.mode_good::kernel 1099 +system.cpu0.kern.mode_good::user 1099 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.164126 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.164275 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.281972 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897963397000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1861803000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.282193 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1897960603000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1864923000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3077 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 74467 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 24565 38.36% 38.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 3.00% 41.36% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 74469 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 24566 38.36% 38.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 3.00% 41.37% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 37108 57.95% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 64035 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 23886 48.07% 48.07% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 37109 57.95% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 64037 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 23887 48.07% 48.07% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 23447 47.18% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 49695 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870827437000 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343518500 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 182737500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29176221000 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900529914000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.972359 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 23448 47.18% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 49697 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870827131500 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343570500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 182754500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29175936000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900529392500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.972360 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.631858 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.776060 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.631868 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.776067 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed @@ -1730,9 +1726,9 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # nu system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed -system.cpu1.kern.callpal::swpipl 57992 87.22% 90.51% # number of callpals executed +system.cpu1.kern.callpal::swpipl 57994 87.22% 90.51% # number of callpals executed system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.11% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.12% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed @@ -1740,7 +1736,7 @@ system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # nu system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 66490 # number of callpals executed +system.cpu1.kern.callpal::total 66492 # number of callpals executed system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches system.cpu1.kern.mode_switch::user 641 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches @@ -1751,9 +1747,9 @@ system.cpu1.kern.mode_switch_good::kernel 0.473336 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 7877043500 0.41% 0.41% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 912149500 0.05% 0.46% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1891740713000 99.54% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 7877089500 0.41% 0.41% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 911545000 0.05% 0.46% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1891740750000 99.54% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1825 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index b1df0f096..353ee4820 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -581,7 +581,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index a30a37ba8..f67dea3de 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 11:00:25 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 22:30:38 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1865402113500 because m5_exit instruction encountered +Exiting @ tick 1864423957500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index a9a5c3cb0..0374f29ea 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,142 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.865402 # Number of seconds simulated -sim_ticks 1865402113500 # Number of ticks simulated -final_tick 1865402113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.864424 # Number of seconds simulated +sim_ticks 1864423957500 # Number of ticks simulated +final_tick 1864423957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131129 # Simulator instruction rate (inst/s) -host_op_rate 131129 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4607058697 # Simulator tick rate (ticks/s) -host_mem_usage 298956 # Number of bytes of host memory used -host_seconds 404.90 # Real time elapsed on the host -sim_insts 53094243 # Number of instructions simulated -sim_ops 53094243 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 967424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877312 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28497024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 967424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516928 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516928 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15116 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388708 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445266 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117452 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117452 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13336166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1421832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15276612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4029656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4029656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4029656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13336166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1421832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19306267 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 338323 # number of replacements -system.l2c.tagsinuse 65346.781313 # Cycle average of tags in use -system.l2c.total_refs 2566599 # Total number of references to valid blocks. -system.l2c.sampled_refs 403491 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.360982 # Average number of references to valid blocks. +host_inst_rate 128916 # Simulator instruction rate (inst/s) +host_op_rate 128916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4527170908 # Simulator tick rate (ticks/s) +host_mem_usage 303408 # Number of bytes of host memory used +host_seconds 411.83 # Real time elapsed on the host +sim_insts 53091408 # Number of instructions simulated +sim_ops 53091408 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 967616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24878144 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652032 # Number of bytes read from this memory +system.physmem.bytes_read::total 28497792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517760 # Number of bytes written to this memory +system.physmem.bytes_written::total 7517760 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15119 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388721 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445278 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117465 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117465 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13343609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1422440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15285039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4032216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4032216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4032216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13343609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1422440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19317254 # 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number of overall miss cycles -system.l2c.overall_miss_latency::total 21256999995 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 1025810 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1103183 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2128993 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 843192 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 843192 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 185872 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185872 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1009873 # 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number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 805852997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20453712996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21259565993 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 805852997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20453712996 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21259565993 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1024994 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1102957 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2127951 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 842689 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 842689 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 301119 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301119 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1025810 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1404302 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2430112 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1025810 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1404302 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2430112 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014738 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.248232 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.135728 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.583333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.583333 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383078 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383078 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014738 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.277146 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.166377 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014738 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.277146 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.166377 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53296.732240 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52075.900601 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52139.772213 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 10234.693878 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 10234.693878 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 53666.473030 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53666.473030 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52575.343470 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52547.321786 # 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miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.588235 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.588235 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.382993 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382993 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014752 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.277192 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166457 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014752 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.277192 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166457 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53293.631175 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52076.375069 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52140.068506 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 7940 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7940 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53669.125260 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53669.125260 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53293.631175 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52548.493830 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52576.358439 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53293.631175 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52548.493830 # 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number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15772049497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16393015495 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 620965998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15772049497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16393015495 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810224030 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 810224030 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103797000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1103797000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1914021030 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1914021030 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248232 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.135727 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.583333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.583333 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383078 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383078 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.166377 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.166377 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41077.330026 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40077.717322 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.011898 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42142.857143 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.468800 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.468800 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.inst 15120 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 288979 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 50 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 50 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 15120 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 389235 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 404355 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 15120 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 389235 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 404355 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 621011997 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10975832000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11596843997 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2105000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2105000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4797954496 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4797954496 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 621011997 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15773786496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16394798493 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 621011997 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15773786496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16394798493 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809342530 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 809342530 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103231500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1103231500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1912574030 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1912574030 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248295 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.135802 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.588235 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.588235 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.382993 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.382993 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277192 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166456 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277192 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166456 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41072.222024 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40078.405311 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.403929 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42100 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42100 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.377340 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.377340 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41072.222024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40525.097938 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40545.556486 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41072.222024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40525.097938 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40545.556486 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -219,14 +231,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.294799 # Cycle average of tags in use +system.iocache.tagsinuse 1.287077 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1711277767000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.294799 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.080925 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.080925 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1711278506000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.287077 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.080442 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.080442 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -237,12 +249,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7641897806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7641897806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7662570804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7662570804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7662570804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7662570804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7639838806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7639838806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7660511804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7660511804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7660511804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7660511804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -261,17 +273,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183911.672266 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183911.672266 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183644.596860 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183644.596860 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7656000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183862.119898 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183862.119898 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183595.249946 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183595.249946 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183595.249946 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183595.249946 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7420000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7143 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7102 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1071.818564 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1044.776119 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -287,12 +299,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5481043992 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5481043992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5492719992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5492719992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5492719992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5492719992 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5478984000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5478984000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5490660000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5490660000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5490660000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5490660000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -303,12 +315,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131908.066808 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131908.066808 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131858.490566 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131858.490566 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131591.611744 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131591.611744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131591.611744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131591.611744 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -326,22 +338,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9972402 # DTB read hits -system.cpu.dtb.read_misses 43929 # DTB read misses -system.cpu.dtb.read_acv 494 # DTB read access violations -system.cpu.dtb.read_accesses 957886 # DTB read accesses -system.cpu.dtb.write_hits 6649938 # DTB write hits -system.cpu.dtb.write_misses 10071 # DTB write misses -system.cpu.dtb.write_acv 391 # DTB write access violations -system.cpu.dtb.write_accesses 340693 # DTB write accesses -system.cpu.dtb.data_hits 16622340 # DTB hits -system.cpu.dtb.data_misses 54000 # DTB misses -system.cpu.dtb.data_acv 885 # DTB access violations -system.cpu.dtb.data_accesses 1298579 # DTB accesses -system.cpu.itb.fetch_hits 1343669 # ITB hits -system.cpu.itb.fetch_misses 37345 # ITB misses -system.cpu.itb.fetch_acv 1146 # ITB acv -system.cpu.itb.fetch_accesses 1381014 # ITB accesses +system.cpu.dtb.read_hits 9968108 # DTB read hits +system.cpu.dtb.read_misses 43556 # DTB read misses +system.cpu.dtb.read_acv 496 # DTB read access violations +system.cpu.dtb.read_accesses 957960 # DTB read accesses +system.cpu.dtb.write_hits 6640476 # DTB write hits +system.cpu.dtb.write_misses 10042 # DTB write misses +system.cpu.dtb.write_acv 402 # DTB write access violations +system.cpu.dtb.write_accesses 340316 # DTB write accesses +system.cpu.dtb.data_hits 16608584 # DTB hits +system.cpu.dtb.data_misses 53598 # DTB misses +system.cpu.dtb.data_acv 898 # DTB access violations +system.cpu.dtb.data_accesses 1298276 # DTB accesses +system.cpu.itb.fetch_hits 1341124 # ITB hits +system.cpu.itb.fetch_misses 40235 # ITB misses +system.cpu.itb.fetch_acv 1160 # ITB acv +system.cpu.itb.fetch_accesses 1381359 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -354,143 +366,143 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122571263 # number of cpu cycles simulated +system.cpu.numCycles 122531860 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14075987 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11741614 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 452517 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10126525 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5926302 # Number of BTB hits +system.cpu.BPredUnit.lookups 14045558 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11719354 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 447776 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10129156 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5920510 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 942334 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45003 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31564050 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71567580 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14075987 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6868636 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13486844 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2151091 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 41804632 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33708 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 276041 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 314295 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 187 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8859322 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 305645 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 88896899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.805063 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.137281 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 939631 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44501 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31544288 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71453130 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14045558 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6860141 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13465921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2135846 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 41803348 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 276891 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 309124 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8845261 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 302298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 88840406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.804286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.136255 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75410055 84.83% 84.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 885656 1.00% 85.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1762066 1.98% 87.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 856601 0.96% 88.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2772547 3.12% 91.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 605003 0.68% 92.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 676052 0.76% 93.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1014878 1.14% 94.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4914041 5.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75374485 84.84% 84.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 882693 0.99% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1758870 1.98% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 855110 0.96% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2773745 3.12% 91.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 603499 0.68% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 673337 0.76% 93.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1014466 1.14% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4904201 5.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 88896899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.114839 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.583885 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32604567 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 41610698 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12250426 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1057078 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1374129 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 617310 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43428 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70293890 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 133239 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1374129 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33752767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16324711 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21058224 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11548980 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4838086 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66572257 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7187 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 753146 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1801877 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44498273 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80714962 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80226097 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 488865 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38261328 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6236937 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1703640 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251709 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12757763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10570492 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6981683 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1316603 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 922104 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58981346 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2097651 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57326676 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120953 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7579711 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3887654 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1429592 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 88896899 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.644867 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.291957 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 88840406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114628 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.583139 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32595578 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 41593167 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12233698 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1054489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1363473 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 614789 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43441 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70185288 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 133206 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1363473 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33740803 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16340010 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21029757 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11532133 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4834228 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66486071 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 750706 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1800875 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44431145 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80611615 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80123142 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 488473 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38259358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6171779 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1702958 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251555 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12743501 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10564267 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6974375 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1310956 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921637 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58920823 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2093860 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57272597 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 128544 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7527772 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3875760 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1425872 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 88840406 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.644668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.291770 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 62967728 70.83% 70.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 12048856 13.55% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5390899 6.06% 90.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3449544 3.88% 94.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2613461 2.94% 97.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1329807 1.50% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 686975 0.77% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 354371 0.40% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 55258 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 62934632 70.84% 70.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 12040664 13.55% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5383860 6.06% 90.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3443587 3.88% 94.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2613267 2.94% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1328836 1.50% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 686879 0.77% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 354518 0.40% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 54163 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 88896899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 88840406 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 75491 10.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 363771 48.19% 58.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 315594 41.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73519 9.73% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 364094 48.19% 57.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 318003 42.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39127581 68.25% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61956 0.11% 68.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39090989 68.25% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61973 0.11% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued @@ -517,116 +529,116 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10418296 18.17% 86.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6729507 11.74% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952802 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10411715 18.18% 86.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6718707 11.73% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952679 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57326676 # Type of FU issued -system.cpu.iq.rate 0.467701 # Inst issue rate -system.cpu.iq.fu_busy_cnt 754856 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 203729346 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68333375 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56036726 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 696713 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 339202 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327718 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57709702 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 364539 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 594776 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57272597 # Type of FU issued +system.cpu.iq.rate 0.467410 # Inst issue rate +system.cpu.iq.fu_busy_cnt 755616 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013193 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 203573547 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68217667 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55990659 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 696212 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 338599 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327577 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57656594 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 364328 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 594908 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1456655 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2870 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14252 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 588832 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1450991 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2769 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14176 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 581838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18348 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 104302 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18337 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 105015 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1374129 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11393417 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 869281 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64652535 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684492 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10570492 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6981683 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1845589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 621506 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12714 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14252 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 241539 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 423865 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 665404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56791406 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10044983 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 535269 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1363473 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11404151 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 871964 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64586243 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684405 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10564267 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6974375 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841535 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 624319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12765 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14176 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 237440 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 422569 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 660009 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56745623 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10040371 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 526973 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3573538 # number of nop insts executed -system.cpu.iew.exec_refs 16720258 # number of memory reference insts executed -system.cpu.iew.exec_branches 9005988 # Number of branches executed -system.cpu.iew.exec_stores 6675275 # Number of stores executed -system.cpu.iew.exec_rate 0.463334 # Inst execution rate -system.cpu.iew.wb_sent 56476627 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56364444 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27797872 # num instructions producing a value -system.cpu.iew.wb_consumers 37663953 # num instructions consuming a value +system.cpu.iew.exec_nop 3571560 # number of nop insts executed +system.cpu.iew.exec_refs 16706164 # number of memory reference insts executed +system.cpu.iew.exec_branches 8999941 # Number of branches executed +system.cpu.iew.exec_stores 6665793 # Number of stores executed +system.cpu.iew.exec_rate 0.463109 # Inst execution rate +system.cpu.iew.wb_sent 56430087 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56318236 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27772479 # num instructions producing a value +system.cpu.iew.wb_consumers 37631426 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.459850 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738050 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459621 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738013 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56288834 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56288834 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8251602 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 668059 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 621198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 87522770 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.643134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.558246 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56285915 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56285915 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 8189376 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 616441 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 87476933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.643437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.558745 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 66254825 75.70% 75.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8962066 10.24% 85.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4828588 5.52% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2603942 2.98% 94.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1449491 1.66% 96.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 603705 0.69% 96.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 515511 0.59% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 488925 0.56% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1815717 2.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66214375 75.69% 75.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8956758 10.24% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4831410 5.52% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2600718 2.97% 94.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1447358 1.65% 96.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 605400 0.69% 96.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 515608 0.59% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 488345 0.56% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1816961 2.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 87522770 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56288834 # Number of instructions committed -system.cpu.commit.committedOps 56288834 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 87476933 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56285915 # Number of instructions committed +system.cpu.commit.committedOps 56285915 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15506688 # Number of memory references committed -system.cpu.commit.loads 9113837 # Number of loads committed -system.cpu.commit.membars 227975 # Number of memory barriers committed -system.cpu.commit.branches 8463674 # Number of branches committed +system.cpu.commit.refs 15505813 # Number of memory references committed +system.cpu.commit.loads 9113276 # Number of loads committed +system.cpu.commit.membars 227944 # Number of memory barriers committed +system.cpu.commit.branches 8463135 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52126817 # Number of committed integer instructions. -system.cpu.commit.function_calls 744625 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1815717 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52124087 # Number of committed integer instructions. +system.cpu.commit.function_calls 744545 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1816961 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149996318 # The number of ROB reads -system.cpu.rob.rob_writes 130455868 # The number of ROB writes -system.cpu.timesIdled 1387986 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33674364 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3608226532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53094243 # Number of Instructions Simulated -system.cpu.committedOps 53094243 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53094243 # Number of Instructions Simulated -system.cpu.cpi 2.308560 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.308560 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433170 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433170 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74446052 # number of integer regfile reads -system.cpu.int_regfile_writes 40661007 # number of integer regfile writes -system.cpu.fp_regfile_reads 166346 # number of floating regfile reads -system.cpu.fp_regfile_writes 166939 # number of floating regfile writes -system.cpu.misc_regfile_reads 1998850 # number of misc regfile reads -system.cpu.misc_regfile_writes 950370 # number of misc regfile writes +system.cpu.rob.rob_reads 149884134 # The number of ROB reads +system.cpu.rob.rob_writes 130314855 # The number of ROB writes +system.cpu.timesIdled 1389359 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33691454 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3606309626 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53091408 # Number of Instructions Simulated +system.cpu.committedOps 53091408 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53091408 # Number of Instructions Simulated +system.cpu.cpi 2.307941 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.307941 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433287 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433287 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74386687 # number of integer regfile reads +system.cpu.int_regfile_writes 40627933 # number of integer regfile writes +system.cpu.fp_regfile_reads 166209 # number of floating regfile reads +system.cpu.fp_regfile_writes 166935 # number of floating regfile writes +system.cpu.misc_regfile_reads 1998011 # number of misc regfile reads +system.cpu.misc_regfile_writes 950291 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -658,247 +670,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1025209 # number of replacements -system.cpu.icache.tagsinuse 509.960172 # Cycle average of tags in use -system.cpu.icache.total_refs 7772148 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1025718 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.577276 # Average number of references to valid blocks. +system.cpu.icache.replacements 1024388 # number of replacements +system.cpu.icache.tagsinuse 509.959478 # Cycle average of tags in use +system.cpu.icache.total_refs 7759501 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1024896 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.571013 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 23722278000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.960172 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996016 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996016 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7772149 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7772149 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7772149 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7772149 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7772149 # number of overall hits -system.cpu.icache.overall_hits::total 7772149 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1087170 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1087170 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1087170 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1087170 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1087170 # number of overall misses -system.cpu.icache.overall_misses::total 1087170 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528418489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17528418489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17528418489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17528418489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17528418489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17528418489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8859319 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8859319 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8859319 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8859319 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8859319 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8859319 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122715 # 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number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1025966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1025966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1025966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1025966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13510508994 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13510508994 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13510508994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13510508994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13510508994 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13510508994 # 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number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1025143 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1025143 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13492714994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13492714994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13492714994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13492714994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13492714994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13492714994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115897 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115897 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115897 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13161.788154 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13161.788154 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13161.788154 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13161.788154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13161.788154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13161.788154 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214102 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214102 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 220148 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220148 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15265430 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15265430 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15265430 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15265430 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200981 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200981 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319624 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109401 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109401 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000018 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000018 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.248694 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.248694 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.248694 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.248694 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26700.025689 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26700.025689 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38101.573374 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38101.573374 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18449.502498 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18449.502498 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14125 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14125 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32608.776087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32608.776087 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 732928021 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.248835 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.248835 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.248835 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.248835 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26703.910944 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26703.910944 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38074.550353 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38074.550353 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18301.754686 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18301.754686 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32594.899300 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32594.899300 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32594.899300 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32594.899300 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 731758024 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72145 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72544 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10159.096556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10087.092303 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842954 # number of writebacks -system.cpu.dcache.writebacks::total 842954 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 743747 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 743747 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667534 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1667534 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5230 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5230 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2411281 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2411281 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2411281 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2411281 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085838 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1085838 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300600 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300600 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18187 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 842689 # number of writebacks +system.cpu.dcache.writebacks::total 842689 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 745053 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 745053 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1667452 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2412505 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2412505 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2412505 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2412505 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085528 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1085528 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300544 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300544 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18217 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18217 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386438 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386438 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386438 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386438 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28239740000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28239740000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9650792448 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9650792448 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 273508500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 273508500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37890532448 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37890532448 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37890532448 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37890532448 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 905949500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 905949500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1225663998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1225663998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2131613498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2131613498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084945 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084945 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386072 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386072 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386072 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386072 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28234901500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28234901500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9648960448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9648960448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 269943500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 269943500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 85500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 85500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37883861948 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37883861948 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37883861948 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37883861948 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904971500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904971500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1224983998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1224983998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2129955498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2129955498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085086 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085086 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000018 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090791 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26007.323376 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26007.323376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32105.097964 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32105.097964 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15038.681476 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15038.681476 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090798 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090798 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090798 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090798 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26010.293148 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26010.293148 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32104.984455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32104.984455 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14818.219246 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14818.219246 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 21375 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 21375 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27331.813894 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27331.813894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27331.813894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27331.813894 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -907,28 +917,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211694 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74899 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 247 0.14% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1887 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105884 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182917 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73532 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 247 0.17% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149203 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1825754390000 97.87% 97.87% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 99081000 0.01% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 381309500 0.02% 97.90% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 39166410000 2.10% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865401190500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211669 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74897 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1886 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105867 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182893 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73530 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1886 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73533 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149192 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1824783514500 97.87% 97.87% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 98568000 0.01% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384878500 0.02% 97.90% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39156084500 2.10% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1864423045500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694505 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815687 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694579 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815734 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -967,29 +977,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175564 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175546 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6791 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192535 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches +system.cpu.kern.callpal::total 192513 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches system.cpu.kern.mode_switch::user 1736 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2110 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches system.cpu.kern.mode_good::kernel 1906 system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320013 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080569 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.388940 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29632954500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2782152500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832986075500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.389059 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29626491000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2782272500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832014274000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |