diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
| commit | d6283445744d5be2a9ac33f0adbc729d48e22c40 (patch) | |
| tree | 67910602fd144f50fa86b1c8a90e0e4f0e66ee90 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | cf5935445f23d0ba2f41debc50952fe45d7c9f4a (diff) | |
| download | gem5-d6283445744d5be2a9ac33f0adbc729d48e22c40.tar.xz | |
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 3020 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1466 |
2 files changed, 2243 insertions, 2243 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index a7a1d7396..082ffde7c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.900530 # Number of seconds simulated -sim_ticks 1900530295500 # Number of ticks simulated -final_tick 1900530295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903503 # Number of seconds simulated +sim_ticks 1903503020500 # Number of ticks simulated +final_tick 1903503020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128893 # Simulator instruction rate (inst/s) -host_op_rate 128893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4273489918 # Simulator tick rate (ticks/s) -host_mem_usage 307500 # Number of bytes of host memory used -host_seconds 444.73 # Real time elapsed on the host -sim_insts 57321882 # Number of instructions simulated -sim_ops 57321882 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 875200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24658176 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 108032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 692736 # Number of bytes read from this memory -system.physmem.bytes_read::total 28984960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 875200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 108032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 983232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7922432 # Number of bytes written to this memory -system.physmem.bytes_written::total 7922432 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385284 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1688 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10824 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452890 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123788 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123788 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 460503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12974366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1394777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56843 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 364496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15250986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 460503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517346 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4168538 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4168538 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4168538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 460503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12974366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1394777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19419523 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 345965 # number of replacements -system.l2c.tagsinuse 65264.028554 # Cycle average of tags in use -system.l2c.total_refs 2565305 # Total number of references to valid blocks. -system.l2c.sampled_refs 411137 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.239538 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6370050000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53566.065326 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5313.128544 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6099.641645 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 209.824884 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 75.368156 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.817353 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.081072 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093073 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003202 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001150 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995850 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 778193 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 689575 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 314248 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 100958 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1882974 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 806039 # number of Writeback hits -system.l2c.Writeback_hits::total 806039 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 439 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 613 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 128167 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 44386 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172553 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 778193 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 817742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 314248 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 145344 # number of demand (read+write) hits -system.l2c.demand_hits::total 2055527 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 778193 # number of overall hits -system.l2c.overall_hits::cpu0.data 817742 # number of overall hits -system.l2c.overall_hits::cpu1.inst 314248 # number of overall hits -system.l2c.overall_hits::cpu1.data 145344 # number of overall hits -system.l2c.overall_hits::total 2055527 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13677 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272973 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1705 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 853 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289208 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2871 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1574 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4445 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 724 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 747 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1471 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113108 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 10072 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123180 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13677 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386081 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1705 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10925 # number of demand (read+write) misses -system.l2c.demand_misses::total 412388 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13677 # number of overall misses -system.l2c.overall_misses::cpu0.data 386081 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1705 # number of overall misses -system.l2c.overall_misses::cpu1.data 10925 # number of overall misses -system.l2c.overall_misses::total 412388 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 728382998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14214430499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 91270500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 46668499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15080752496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 19818914 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 22402914 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2792500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3106500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6061979997 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 549631499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6611611496 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 728382998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20276410496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 91270500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 596299998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21692363992 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 728382998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20276410496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 91270500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 596299998 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21692363992 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 791870 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 962548 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 315953 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 101811 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2172182 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 806039 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 806039 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3045 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2013 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5058 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 778 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1554 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 241275 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 54458 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295733 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 791870 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1203823 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 315953 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 156269 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2467915 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 791870 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1203823 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 315953 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 156269 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2467915 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.017272 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.283594 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005396 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.008378 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133142 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942857 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781918 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.878806 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.932990 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.960154 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.946589 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.468793 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.184950 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.416524 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.017272 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.320712 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005396 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.069911 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.167100 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.017272 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.320712 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005396 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.069911 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.167100 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53256.050157 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.661029 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53531.085044 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 54711.018757 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52145.004620 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 900.034831 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12591.432020 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5040.025647 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3857.044199 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 420.348059 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2111.828688 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.617507 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54570.244142 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53674.391102 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53256.050157 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52518.540141 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 53531.085044 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 54581.235515 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52601.831266 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53256.050157 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52518.540141 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 53531.085044 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 54581.235515 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52601.831266 # average overall miss latency +host_inst_rate 196271 # Simulator instruction rate (inst/s) +host_op_rate 196271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6657053225 # Simulator tick rate (ticks/s) +host_mem_usage 303260 # Number of bytes of host memory used +host_seconds 285.94 # Real time elapsed on the host +sim_insts 56121257 # Number of instructions simulated +sim_ops 56121257 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 882432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24721216 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 100416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 648960 # Number of bytes read from this memory +system.physmem.bytes_read::total 29002688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 882432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 100416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 982848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7936064 # Number of bytes written to this memory +system.physmem.bytes_written::total 7936064 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13788 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386269 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1569 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10140 # Number of read requests responded to by this memory +system.physmem.num_reads::total 453167 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124001 # Number of write requests responded to by this memory +system.physmem.num_writes::total 124001 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 463583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12987222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 340929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15236481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 463583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4169189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4169189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4169189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 463583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12987222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 340929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19405670 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 346253 # number of replacements +system.l2c.tagsinuse 65331.229324 # Cycle average of tags in use +system.l2c.total_refs 2603754 # Total number of references to valid blocks. +system.l2c.sampled_refs 411399 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.329024 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6380524000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53709.821247 # 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number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119320.213483 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183813.746775 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183813.746775 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183538.648550 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183538.648550 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183538.648550 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183538.648550 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7685000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119392.034091 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183736.710772 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183736.710772 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183465.318347 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183465.318347 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183465.318347 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183465.318347 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7744000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7152 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7100 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1074.524609 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1090.704225 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476969000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5476969000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5488951000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5488951000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5488951000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5488951000 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11860000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11860000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473770000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5473770000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5485630000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5485630000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5485630000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5485630000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131809.997112 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131809.997112 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131733.009241 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131733.009241 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131461.608512 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131461.608512 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131461.608512 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131461.608512 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8334041 # DTB read hits -system.cpu0.dtb.read_misses 29708 # DTB read misses -system.cpu0.dtb.read_acv 432 # DTB read access violations -system.cpu0.dtb.read_accesses 650283 # DTB read accesses -system.cpu0.dtb.write_hits 5360343 # DTB write hits -system.cpu0.dtb.write_misses 6029 # DTB write misses -system.cpu0.dtb.write_acv 281 # DTB write access violations -system.cpu0.dtb.write_accesses 211361 # DTB write accesses -system.cpu0.dtb.data_hits 13694384 # DTB hits -system.cpu0.dtb.data_misses 35737 # DTB misses -system.cpu0.dtb.data_acv 713 # DTB access violations -system.cpu0.dtb.data_accesses 861644 # DTB accesses -system.cpu0.itb.fetch_hits 975254 # ITB hits -system.cpu0.itb.fetch_misses 26821 # ITB misses -system.cpu0.itb.fetch_acv 801 # ITB acv -system.cpu0.itb.fetch_accesses 1002075 # ITB accesses +system.cpu0.dtb.read_hits 9362822 # DTB read hits +system.cpu0.dtb.read_misses 32776 # DTB read misses +system.cpu0.dtb.read_acv 407 # DTB read access violations +system.cpu0.dtb.read_accesses 655429 # DTB read accesses +system.cpu0.dtb.write_hits 6177998 # DTB write hits +system.cpu0.dtb.write_misses 6927 # DTB write misses +system.cpu0.dtb.write_acv 263 # DTB write access violations +system.cpu0.dtb.write_accesses 211643 # DTB write accesses +system.cpu0.dtb.data_hits 15540820 # DTB hits +system.cpu0.dtb.data_misses 39703 # DTB misses +system.cpu0.dtb.data_acv 670 # DTB access violations +system.cpu0.dtb.data_accesses 867072 # DTB accesses +system.cpu0.itb.fetch_hits 1071612 # ITB hits +system.cpu0.itb.fetch_misses 26818 # ITB misses +system.cpu0.itb.fetch_acv 827 # ITB acv +system.cpu0.itb.fetch_accesses 1098430 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,279 +483,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 107505653 # number of cpu cycles simulated +system.cpu0.numCycles 120285579 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 11783453 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 9875598 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 345606 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8356965 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5072042 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13328375 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11156715 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 403301 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9703007 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5627426 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 768478 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 29315 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 25158431 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 60438649 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11783453 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5840520 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11478099 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1678793 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36446213 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 35059 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 187963 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 310129 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7506544 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 232672 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 74721559 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.808852 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.135528 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 881916 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 36485 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 30082863 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 67323144 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13328375 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6509342 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12704270 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1925792 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 41150259 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29396 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 190626 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 307717 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 171 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8274450 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 278264 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 85724819 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.785340 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.113356 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63243460 84.64% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 740935 0.99% 85.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1559450 2.09% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686263 0.92% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2492339 3.34% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 528695 0.71% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 568727 0.76% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 718688 0.96% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4183002 5.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 73020549 85.18% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 838460 0.98% 86.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1676934 1.96% 88.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 765061 0.89% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2646040 3.09% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 584012 0.68% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 626464 0.73% 93.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 965763 1.13% 94.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4601536 5.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74721559 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.109608 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.562190 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26241114 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36078495 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10432905 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 895868 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1073176 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 504459 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 32663 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 59394337 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 93513 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1073176 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27177088 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15322085 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17293060 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9793199 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4062949 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 56409108 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7164 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 656382 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1492215 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 37953965 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 68862069 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 68509500 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 352569 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33051447 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4902518 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1333146 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 200213 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10586539 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8773665 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5638420 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132750 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 738704 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50116530 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1671338 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 48856724 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 108345 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5942974 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3041199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1133867 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 74721559 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.653850 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.297886 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 85724819 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.110806 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559694 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 31004655 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 40959879 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11547285 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 992195 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1220804 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 569651 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 39042 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 66162079 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 119714 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1220804 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 32084617 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 16798713 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 20265121 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10859034 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4496528 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 62667463 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6952 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 714166 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1644224 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 41889226 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 75909055 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 75455060 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 453995 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36387256 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5501970 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1564601 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238699 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11969460 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9870474 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6474014 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1213478 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 815744 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 55487857 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1996787 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54121133 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 111429 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6732221 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3352698 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1361171 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 85724819 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.631336 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.279357 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52677257 70.50% 70.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10184833 13.63% 84.13% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4563049 6.11% 90.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2984127 3.99% 94.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2257312 3.02% 97.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1142410 1.53% 98.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 582471 0.78% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 283512 0.38% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 46588 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 61209229 71.40% 71.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 11417613 13.32% 84.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5048858 5.89% 90.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3283375 3.83% 94.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2508461 2.93% 97.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1248570 1.46% 98.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 634570 0.74% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 321579 0.38% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52564 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74721559 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 85724819 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 73394 11.97% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 287556 46.90% 58.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 252163 41.13% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 72995 10.68% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 324242 47.46% 58.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 285988 41.86% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 33933939 69.46% 69.47% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 53607 0.11% 69.57% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8676123 17.76% 87.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5426873 11.11% 98.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 742938 1.52% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4465 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37158612 68.66% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60272 0.11% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 18564 0.03% 68.81% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.81% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.81% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.81% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9761868 18.04% 86.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6247803 11.54% 98.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 867318 1.60% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 48856724 # Type of FU issued -system.cpu0.iq.rate 0.454457 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 613113 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012549 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 172655307 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57499462 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 47860573 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 501158 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 243682 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 236026 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 49203092 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 262278 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 518007 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54121133 # Type of FU issued +system.cpu0.iq.rate 0.449939 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 683225 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012624 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 194116788 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 63916247 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 52959668 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 644951 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 312925 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 303605 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 54462198 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 337695 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 568272 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1116542 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2532 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12656 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 476196 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1280116 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2462 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12570 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 515440 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18844 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 94055 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18537 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 100807 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1073176 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10803844 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 780020 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 54838073 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 560128 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8773665 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5638420 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1470903 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 544426 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 8361 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12656 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186168 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 328100 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 514268 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 48431034 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8384906 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 425690 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1220804 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 12124657 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 860720 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 60917526 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 643294 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9870474 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6474014 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1758330 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 617908 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 8871 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12570 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 212626 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 388253 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 600879 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 53642657 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9419598 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 478476 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3050205 # number of nop insts executed -system.cpu0.iew.exec_refs 13763900 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7759085 # Number of branches executed -system.cpu0.iew.exec_stores 5378994 # Number of stores executed -system.cpu0.iew.exec_rate 0.450498 # Inst execution rate -system.cpu0.iew.wb_sent 48183963 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48096599 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24100955 # num instructions producing a value -system.cpu0.iew.wb_consumers 32404442 # num instructions consuming a value +system.cpu0.iew.exec_nop 3432882 # number of nop insts executed +system.cpu0.iew.exec_refs 15618436 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8560068 # Number of branches executed +system.cpu0.iew.exec_stores 6198838 # Number of stores executed +system.cpu0.iew.exec_rate 0.445961 # Inst execution rate +system.cpu0.iew.wb_sent 53356597 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53263273 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26352404 # num instructions producing a value +system.cpu0.iew.wb_consumers 35613133 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.447387 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743755 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.442807 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.739963 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 48294855 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 48294855 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6449755 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 537471 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 480800 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 73648383 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.655749 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.560255 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 53500498 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 53500498 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 7330810 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 635616 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 562628 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 84504015 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.633112 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.546448 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55233499 75.00% 75.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7733418 10.50% 85.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4278651 5.81% 91.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2283988 3.10% 94.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1242605 1.69% 96.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 524240 0.71% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 434900 0.59% 97.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 385505 0.52% 97.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1531577 2.08% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 64274948 76.06% 76.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8494337 10.05% 86.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4620943 5.47% 91.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2493253 2.95% 94.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1382716 1.64% 96.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 578306 0.68% 96.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 482831 0.57% 97.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 448312 0.53% 97.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1728369 2.05% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 73648383 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 48294855 # Number of instructions committed -system.cpu0.commit.committedOps 48294855 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 84504015 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 53500498 # Number of instructions committed +system.cpu0.commit.committedOps 53500498 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12819347 # Number of memory references committed -system.cpu0.commit.loads 7657123 # Number of loads committed -system.cpu0.commit.membars 181890 # Number of memory barriers committed -system.cpu0.commit.branches 7325688 # Number of branches committed -system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 44748779 # Number of committed integer instructions. -system.cpu0.commit.function_calls 610967 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1531577 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14548932 # Number of memory references committed +system.cpu0.commit.loads 8590358 # Number of loads committed +system.cpu0.commit.membars 216685 # Number of memory barriers committed +system.cpu0.commit.branches 8083038 # Number of branches committed +system.cpu0.commit.fp_insts 301061 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49495422 # Number of committed integer instructions. +system.cpu0.commit.function_calls 700509 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1728369 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126676900 # The number of ROB reads -system.cpu0.rob.rob_writes 110562172 # The number of ROB writes -system.cpu0.timesIdled 1222053 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32784094 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693280483 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 45533193 # Number of Instructions Simulated -system.cpu0.committedOps 45533193 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 45533193 # Number of Instructions Simulated -system.cpu0.cpi 2.361039 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.361039 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.423542 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.423542 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 63859411 # number of integer regfile reads -system.cpu0.int_regfile_writes 34945756 # number of integer regfile writes -system.cpu0.fp_regfile_reads 117042 # number of floating regfile reads -system.cpu0.fp_regfile_writes 117632 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1550181 # number of misc regfile reads -system.cpu0.misc_regfile_writes 750158 # number of misc regfile writes +system.cpu0.rob.rob_reads 143428116 # The number of ROB reads +system.cpu0.rob.rob_writes 122883641 # The number of ROB writes +system.cpu0.timesIdled 1359099 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 34560760 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3686357913 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 50400239 # Number of Instructions Simulated +system.cpu0.committedOps 50400239 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 50400239 # Number of Instructions Simulated +system.cpu0.cpi 2.386607 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.386607 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.419005 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.419005 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 70355564 # number of integer regfile reads +system.cpu0.int_regfile_writes 38486142 # number of integer regfile writes +system.cpu0.fp_regfile_reads 150309 # number of floating regfile reads +system.cpu0.fp_regfile_writes 151918 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1870359 # number of misc regfile reads +system.cpu0.misc_regfile_writes 881938 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -787,245 +787,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 791282 # number of replacements -system.cpu0.icache.tagsinuse 510.000823 # Cycle average of tags in use -system.cpu0.icache.total_refs 6671308 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 791794 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.425560 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.000823 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6671308 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6671308 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6671308 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6671308 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6671308 # number of overall hits -system.cpu0.icache.overall_hits::total 6671308 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 835236 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 835236 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 835236 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 835236 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 835236 # number of overall misses -system.cpu0.icache.overall_misses::total 835236 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13775160993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13775160993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13775160993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13775160993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13775160993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13775160993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7506544 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7506544 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7506544 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7506544 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7506544 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7506544 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111268 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111268 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111268 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111268 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111268 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111268 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16492.537430 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16492.537430 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16492.537430 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16492.537430 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1463996 # number of cycles access was blocked +system.cpu0.icache.replacements 978272 # number of replacements +system.cpu0.icache.tagsinuse 509.990128 # Cycle average of tags in use +system.cpu0.icache.total_refs 7239988 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 978784 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.396921 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23947377000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.990128 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996074 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996074 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 7239988 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7239988 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7239988 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7239988 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7239988 # number of overall hits +system.cpu0.icache.overall_hits::total 7239988 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1034461 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1034461 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1034461 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1034461 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1034461 # number of overall misses +system.cpu0.icache.overall_misses::total 1034461 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16768248492 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 16768248492 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 16768248492 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 16768248492 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 16768248492 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 16768248492 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8274449 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8274449 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8274449 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8274449 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8274449 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8274449 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125019 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125019 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125019 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125019 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125019 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125019 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16209.647819 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16209.647819 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16209.647819 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16209.647819 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16209.647819 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16209.647819 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1517995 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 158 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 159 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 9265.797468 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 9547.138365 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43249 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43249 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43249 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791987 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 791987 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 791987 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 791987 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 791987 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 791987 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10696262996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10696262996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10696262996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10696262996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10696262996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10696262996 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105506 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105506 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105506 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13505.604254 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 55484 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 55484 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 55484 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 55484 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 55484 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 55484 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 978977 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 978977 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 978977 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 978977 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 978977 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 978977 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12951368495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12951368495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12951368495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12951368495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12951368495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12951368495 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118313 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.118313 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118313 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.118313 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13229.492108 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13229.492108 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13229.492108 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13229.492108 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1206262 # number of replacements -system.cpu0.dcache.tagsinuse 505.874752 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9821312 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1206702 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.138971 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.874752 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.988037 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.988037 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6113380 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6113380 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3377082 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3377082 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150588 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 150588 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171660 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171660 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9490462 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9490462 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9490462 # number of overall hits -system.cpu0.dcache.overall_hits::total 9490462 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1478592 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1478592 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1593723 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1593723 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18660 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18660 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4698 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4698 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3072315 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3072315 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3072315 # number of overall misses -system.cpu0.dcache.overall_misses::total 3072315 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41280324500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41280324500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65318664554 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 65318664554 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315332000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 315332000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68573000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 68573000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 106598989054 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 106598989054 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 106598989054 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 106598989054 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591972 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7591972 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970805 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4970805 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169248 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 169248 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176358 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 176358 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12562777 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12562777 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12562777 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12562777 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194757 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.194757 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110252 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110252 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026639 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026639 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244557 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.244557 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244557 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.244557 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.671615 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.671615 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40984.954446 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40984.954446 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16898.821008 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16898.821008 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14596.211154 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14596.211154 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34696.633989 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34696.633989 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 716919646 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 65391 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10963.582848 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 1336500 # number of replacements +system.cpu0.dcache.tagsinuse 506.465908 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11143271 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1336941 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.334901 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 23748000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 506.465908 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.989191 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.989191 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6824660 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6824660 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3928020 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3928020 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181318 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 181318 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208014 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208014 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10752680 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10752680 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10752680 # number of overall hits +system.cpu0.dcache.overall_hits::total 10752680 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1708787 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1708787 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1807599 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1807599 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22179 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22179 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 632 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 632 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3516386 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3516386 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3516386 # number of overall misses +system.cpu0.dcache.overall_misses::total 3516386 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46211851500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 46211851500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69878054952 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 69878054952 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 400322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 400322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6190000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 6190000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 116089906452 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 116089906452 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 116089906452 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 116089906452 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8533447 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8533447 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5735619 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5735619 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203497 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203497 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208646 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 208646 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14269066 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14269066 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14269066 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14269066 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.200246 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.200246 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.315153 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.315153 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.108989 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.108989 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003029 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003029 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246434 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.246434 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.246434 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.246434 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27043.658162 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27043.658162 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38657.940700 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38657.940700 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18049.596465 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18049.596465 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9794.303797 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9794.303797 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33013.982666 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33013.982666 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33013.982666 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33013.982666 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 743236979 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 140000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 67742 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10971.583050 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 28000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 693314 # number of writebacks -system.cpu0.dcache.writebacks::total 693314 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515793 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 515793 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344404 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1344404 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1860197 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1860197 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1860197 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1860197 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962799 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 962799 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249319 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249319 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14898 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14898 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4698 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4698 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212118 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1212118 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212118 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1212118 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25944695097 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25944695097 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8701407966 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8701407966 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186837501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186837501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 53961001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 53961001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34646103063 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 34646103063 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34646103063 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 34646103063 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918480000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918480000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327721998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327721998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246201998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246201998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126818 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126818 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050157 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050157 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088025 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088025 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026639 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026639 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096485 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096485 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26947.156257 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26947.156257 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34900.701375 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34900.701375 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.112968 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.112968 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11485.951682 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11485.951682 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 787469 # number of writebacks +system.cpu0.dcache.writebacks::total 787469 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 665447 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 665447 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1525035 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1525035 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4877 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4877 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2190482 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2190482 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2190482 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2190482 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043340 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1043340 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 282564 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 282564 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 632 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 632 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1325904 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1325904 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1325904 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1325904 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27425552538 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27425552538 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9314976366 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9314976366 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 247730500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 247730500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4222000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4222000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36740528904 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 36740528904 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36740528904 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 36740528904 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454814000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454814000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2057449498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2057449498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3512263498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3512263498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122265 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122265 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085023 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085023 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003029 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003029 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092922 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092922 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092922 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092922 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26286.304118 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26286.304118 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32965.899287 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32965.899287 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14318.026818 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14318.026818 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6680.379747 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6680.379747 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27709.795659 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27709.795659 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27709.795659 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27709.795659 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1037,22 +1037,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2497958 # DTB read hits -system.cpu1.dtb.read_misses 12385 # DTB read misses -system.cpu1.dtb.read_acv 105 # DTB read access violations -system.cpu1.dtb.read_accesses 312687 # DTB read accesses -system.cpu1.dtb.write_hits 1734137 # DTB write hits -system.cpu1.dtb.write_misses 3404 # DTB write misses -system.cpu1.dtb.write_acv 137 # DTB write access violations -system.cpu1.dtb.write_accesses 131810 # DTB write accesses -system.cpu1.dtb.data_hits 4232095 # DTB hits -system.cpu1.dtb.data_misses 15789 # DTB misses -system.cpu1.dtb.data_acv 242 # DTB access violations -system.cpu1.dtb.data_accesses 444497 # DTB accesses -system.cpu1.itb.fetch_hits 488697 # ITB hits -system.cpu1.itb.fetch_misses 8773 # ITB misses -system.cpu1.itb.fetch_acv 366 # ITB acv -system.cpu1.itb.fetch_accesses 497470 # ITB accesses +system.cpu1.dtb.read_hits 1316259 # DTB read hits +system.cpu1.dtb.read_misses 12259 # DTB read misses +system.cpu1.dtb.read_acv 114 # DTB read access violations +system.cpu1.dtb.read_accesses 313045 # DTB read accesses +system.cpu1.dtb.write_hits 810694 # DTB write hits +system.cpu1.dtb.write_misses 3210 # DTB write misses +system.cpu1.dtb.write_acv 140 # DTB write access violations +system.cpu1.dtb.write_accesses 130863 # DTB write accesses +system.cpu1.dtb.data_hits 2126953 # DTB hits +system.cpu1.dtb.data_misses 15469 # DTB misses +system.cpu1.dtb.data_acv 254 # DTB access violations +system.cpu1.dtb.data_accesses 443908 # DTB accesses +system.cpu1.itb.fetch_hits 378821 # ITB hits +system.cpu1.itb.fetch_misses 8734 # ITB misses +system.cpu1.itb.fetch_acv 397 # ITB acv +system.cpu1.itb.fetch_accesses 387555 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1065,518 +1065,518 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 22715640 # number of cpu cycles simulated +system.cpu1.numCycles 10995031 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 3441563 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2848590 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 108508 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 2344214 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1191088 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1761936 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1452774 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 65512 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 889011 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 565473 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 236176 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 10617 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 9035553 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16314409 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3441563 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1427264 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2922038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 525528 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 8308395 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 28029 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 86548 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 64086 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1962045 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 75286 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 20775175 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.785284 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.154306 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 118681 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 6179 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3538328 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8413663 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1761936 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 684154 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1515563 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 337074 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 4688566 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24381 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 85396 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48035 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1081640 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 43091 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 10121394 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.831275 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.201855 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 17853137 85.93% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 203247 0.98% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 300737 1.45% 88.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 225181 1.08% 89.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 403762 1.94% 91.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 151742 0.73% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 164996 0.79% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 308573 1.49% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1163800 5.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 8605831 85.03% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 83210 0.82% 85.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 170185 1.68% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 136768 1.35% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 220692 2.18% 91.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 89992 0.89% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 103416 1.02% 92.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 63845 0.63% 93.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 647455 6.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 20775175 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.151506 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.718202 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8809071 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8765539 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2707216 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 172890 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 320458 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 151147 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 10158 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 16014026 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 29482 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 320458 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 9091295 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 884150 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6951341 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2592964 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 934965 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 14837454 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 127 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 84091 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 280482 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 9656446 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 17623003 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 17415204 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 207799 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 8330618 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1325820 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 594023 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 64559 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2775443 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2639269 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1825014 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 248716 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 160479 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12970444 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 664664 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 12696455 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 35550 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1743951 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 828101 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 468923 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 20775175 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.611136 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.284217 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 10121394 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.160248 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.765224 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3636179 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4783124 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1407347 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 79113 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 215630 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 78857 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5594 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8201368 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 16988 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 215630 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3774532 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 581193 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3715501 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1338240 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 496296 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7575516 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 44770 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 149873 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 5044245 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9199948 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9159980 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 39968 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4092104 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 952133 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 317142 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 23346 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1397635 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1414528 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 877825 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 136527 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 116556 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6675821 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 314231 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6372058 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 25577 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1212482 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 668533 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 238569 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 10121394 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.629563 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.309947 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 15113498 72.75% 72.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2653136 12.77% 85.52% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1113601 5.36% 90.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 723121 3.48% 94.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 602829 2.90% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 288191 1.39% 98.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 181892 0.88% 99.52% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 88125 0.42% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10782 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 7322432 72.35% 72.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1274873 12.60% 84.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 565463 5.59% 90.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 381432 3.77% 94.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 276297 2.73% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 150290 1.48% 98.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 93014 0.92% 99.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 53503 0.53% 99.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4090 0.04% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 20775175 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 10121394 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3857 1.52% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 134714 53.16% 54.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 114823 45.31% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2751 1.84% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 83898 56.09% 57.93% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 62938 42.07% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7925481 62.42% 62.45% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 20760 0.16% 62.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10544 0.08% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2621698 20.65% 83.35% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1764339 13.90% 97.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 349399 2.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2823 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3945332 61.92% 61.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 9935 0.16% 62.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 7188 0.11% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1411 0.02% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1374762 21.57% 83.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 831632 13.05% 96.88% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 198975 3.12% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 12696455 # Type of FU issued -system.cpu1.iq.rate 0.558930 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 253394 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019958 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 46157750 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15236198 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 12337265 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 299278 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 145041 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 140795 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 12790304 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 156722 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 115188 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6372058 # Type of FU issued +system.cpu1.iq.rate 0.579540 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 149587 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023475 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 22982123 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8175044 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6195827 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 58550 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 29266 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 28229 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6488697 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 30125 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 71376 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 346106 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 806 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2268 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 152574 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 250758 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 518 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1865 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 114138 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 376 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 11381 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 364 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 10621 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 320458 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 536973 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 73252 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 14361364 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 205800 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2639269 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1825014 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 596393 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 55379 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 5710 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2268 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 53644 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 129908 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 183552 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 12575424 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2521777 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 121030 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 215630 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 327250 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 19053 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7270048 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 103390 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1414528 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 877825 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 292634 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6157 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4769 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1865 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 31136 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 75519 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 106655 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6299419 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1333225 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 72638 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 726256 # number of nop insts executed -system.cpu1.iew.exec_refs 4267761 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1886646 # Number of branches executed -system.cpu1.iew.exec_stores 1745984 # Number of stores executed -system.cpu1.iew.exec_rate 0.553602 # Inst execution rate -system.cpu1.iew.wb_sent 12512047 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 12478060 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5698826 # num instructions producing a value -system.cpu1.iew.wb_consumers 8037620 # num instructions consuming a value +system.cpu1.iew.exec_nop 279996 # number of nop insts executed +system.cpu1.iew.exec_refs 2150860 # number of memory reference insts executed +system.cpu1.iew.exec_branches 922163 # Number of branches executed +system.cpu1.iew.exec_stores 817635 # Number of stores executed +system.cpu1.iew.exec_rate 0.572933 # Inst execution rate +system.cpu1.iew.wb_sent 6254968 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6224056 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2925555 # num instructions producing a value +system.cpu1.iew.wb_consumers 4065237 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.549316 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709019 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.566079 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.719652 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 12432644 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 12432644 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1853978 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 195741 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 172939 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 20454717 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.607813 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.554325 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5954935 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 5954935 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1244518 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 75662 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 99560 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9905764 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.601159 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.526173 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 15840554 77.44% 77.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2123906 10.38% 87.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 810748 3.96% 91.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 497113 2.43% 94.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 362163 1.77% 95.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 133438 0.65% 96.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 130960 0.64% 97.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 152379 0.74% 98.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 403456 1.97% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 7610675 76.83% 76.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1117297 11.28% 88.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 392466 3.96% 92.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 237967 2.40% 94.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 150669 1.52% 96.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 70627 0.71% 96.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 80896 0.82% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 63718 0.64% 98.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 181449 1.83% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 20454717 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 12432644 # Number of instructions committed -system.cpu1.commit.committedOps 12432644 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 9905764 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 5954935 # Number of instructions committed +system.cpu1.commit.committedOps 5954935 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3965603 # Number of memory references committed -system.cpu1.commit.loads 2293163 # Number of loads committed -system.cpu1.commit.membars 64660 # Number of memory barriers committed -system.cpu1.commit.branches 1777364 # Number of branches committed -system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 11487490 # Number of committed integer instructions. -system.cpu1.commit.function_calls 194670 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 403456 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1927457 # Number of memory references committed +system.cpu1.commit.loads 1163770 # Number of loads committed +system.cpu1.commit.membars 20047 # Number of memory barriers committed +system.cpu1.commit.branches 840841 # Number of branches committed +system.cpu1.commit.fp_insts 27263 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5573216 # Number of committed integer instructions. +system.cpu1.commit.function_calls 89926 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 181449 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 34231845 # The number of ROB reads -system.cpu1.rob.rob_writes 28892260 # The number of ROB writes -system.cpu1.timesIdled 230897 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1940465 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3778342351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 11788689 # Number of Instructions Simulated -system.cpu1.committedOps 11788689 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 11788689 # Number of Instructions Simulated -system.cpu1.cpi 1.926901 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.926901 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.518968 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.518968 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 16191128 # number of integer regfile reads -system.cpu1.int_regfile_writes 8793643 # number of integer regfile writes -system.cpu1.fp_regfile_reads 73550 # number of floating regfile reads -system.cpu1.fp_regfile_writes 74224 # number of floating regfile writes -system.cpu1.misc_regfile_reads 699686 # number of misc regfile reads -system.cpu1.misc_regfile_writes 299450 # number of misc regfile writes -system.cpu1.icache.replacements 315418 # number of replacements -system.cpu1.icache.tagsinuse 471.006638 # Cycle average of tags in use -system.cpu1.icache.total_refs 1633897 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 315930 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.171706 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 471.006638 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919935 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919935 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1633897 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1633897 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1633897 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1633897 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1633897 # number of overall hits -system.cpu1.icache.overall_hits::total 1633897 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 328148 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 328148 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 328148 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 328148 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 328148 # number of overall misses -system.cpu1.icache.overall_misses::total 328148 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323185498 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5323185498 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5323185498 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5323185498 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5323185498 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5323185498 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1962045 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1962045 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1962045 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1962045 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1962045 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1962045 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167248 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.167248 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167248 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.167248 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167248 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.167248 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.904439 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.904439 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16221.904439 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16221.904439 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 248998 # number of cycles access was blocked +system.cpu1.rob.rob_reads 16822912 # The number of ROB reads +system.cpu1.rob.rob_writes 14613272 # The number of ROB writes +system.cpu1.timesIdled 86532 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 873637 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3796008743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5721018 # Number of Instructions Simulated +system.cpu1.committedOps 5721018 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 5721018 # Number of Instructions Simulated +system.cpu1.cpi 1.921866 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.921866 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.520328 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.520328 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8196384 # number of integer regfile reads +system.cpu1.int_regfile_writes 4468767 # number of integer regfile writes +system.cpu1.fp_regfile_reads 18086 # number of floating regfile reads +system.cpu1.fp_regfile_writes 17123 # number of floating regfile writes +system.cpu1.misc_regfile_reads 275818 # number of misc regfile reads +system.cpu1.misc_regfile_writes 138963 # number of misc regfile writes +system.cpu1.icache.replacements 112877 # number of replacements +system.cpu1.icache.tagsinuse 455.325853 # Cycle average of tags in use +system.cpu1.icache.total_refs 961616 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 113389 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.480682 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1880828738000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 455.325853 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.889308 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.889308 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 961616 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 961616 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 961616 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 961616 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 961616 # number of overall hits +system.cpu1.icache.overall_hits::total 961616 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 120024 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 120024 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 120024 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 120024 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 120024 # number of overall misses +system.cpu1.icache.overall_misses::total 120024 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1993076499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1993076499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1993076499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1993076499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1993076499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1993076499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1081640 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1081640 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1081640 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1081640 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1081640 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1081640 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110965 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.110965 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110965 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.110965 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110965 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.110965 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16605.649695 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 16605.649695 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16605.649695 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 16605.649695 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16605.649695 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 16605.649695 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 288999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 50 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5928.523810 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5779.980000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12162 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12162 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12162 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12162 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12162 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12162 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315986 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 315986 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 315986 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 315986 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 315986 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 315986 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183764998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183764998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183764998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4183764998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183764998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4183764998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.161049 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.161049 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.161049 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13240.349250 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6586 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6586 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6586 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6586 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6586 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6586 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 113438 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 113438 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 113438 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 113438 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 113438 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 113438 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550619499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1550619499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1550619499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1550619499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1550619499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1550619499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.104876 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.104876 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.104876 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.104876 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13669.312744 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13669.312744 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13669.312744 # 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Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.954792 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2021122 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2021122 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1250999 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1250999 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49956 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 49956 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3272121 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3272121 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3272121 # number of overall hits -system.cpu1.dcache.overall_hits::total 3272121 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 307358 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 307358 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 360875 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 360875 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8692 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8692 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5047 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5047 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 668233 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 668233 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 668233 # number of overall misses -system.cpu1.dcache.overall_misses::total 668233 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6376981500 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2328480 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2328480 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611874 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1611874 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58648 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 58648 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53648 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 53648 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3940354 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3940354 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3940354 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169587 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.169587 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20747.732286 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20747.732286 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31381.517972 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 31381.517972 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.096180 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13967.096180 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13554.586883 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13554.586883 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.825890 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.825890 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1103263 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1103263 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 554602 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 554602 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16904 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16904 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15090 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15090 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1657865 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1657865 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1657865 # number of overall hits +system.cpu1.dcache.overall_hits::total 1657865 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 120863 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 120863 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 188065 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 188065 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1871 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1871 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 714 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 308928 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 308928 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 308928 # number of overall misses +system.cpu1.dcache.overall_misses::total 308928 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2422870500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2422870500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7680920661 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7680920661 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 31721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 31721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8263500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 8263500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10103791161 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10103791161 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10103791161 # 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miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.157072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.157072 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.157072 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20046.420327 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20046.420327 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40841.840114 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 40841.840114 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16954.035275 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16954.035275 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11573.529412 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11573.529412 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32705.974081 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 32705.974081 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32705.974081 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 32705.974081 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 54269989 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6761 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6147 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8470.268895 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8828.695136 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 112725 # number of writebacks -system.cpu1.dcache.writebacks::total 112725 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 197085 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 197085 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298748 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 298748 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1016 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1016 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 495833 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 495833 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 495833 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 495833 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110273 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 110273 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62127 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62127 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7676 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7676 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5047 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5047 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172400 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172400 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172400 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172400 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1761266064 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1761266064 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471935334 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471935334 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78208000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78208000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52884501 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52884501 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3233201398 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3233201398 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3233201398 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3233201398 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18624000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18624000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400633000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400633000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419257000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419257000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047358 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047358 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038543 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038543 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130883 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130883 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094076 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094076 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043752 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043752 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15971.870394 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15971.870394 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23692.361357 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23692.361357 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10188.639917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10188.639917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10478.403210 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10478.403210 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 44452 # number of writebacks +system.cpu1.dcache.writebacks::total 44452 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 76735 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 76735 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 160629 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 160629 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 625 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 625 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 237364 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 237364 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 237364 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 237364 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 44128 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 44128 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 27436 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 27436 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1246 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1246 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 712 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 712 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 71564 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 71564 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 71564 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 71564 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 680335003 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 680335003 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 908440847 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 908440847 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 14899501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 14899501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6048501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6048501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1588775850 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1588775850 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1588775850 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1588775850 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26654500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26654500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 549434000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 549434000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 576088500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 576088500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036049 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036049 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066365 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066365 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.045052 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.045052 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.036386 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.036386 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036386 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.036386 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15417.308806 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15417.308806 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33111.271577 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33111.271577 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11957.865971 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.865971 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8495.085674 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8495.085674 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22200.769242 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22200.769242 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22200.769242 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22200.769242 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1585,171 +1585,171 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 167511 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 84510 58.04% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 145602 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862592154000 98.01% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96215500 0.01% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 394866000 0.02% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 155183500 0.01% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37157983500 1.96% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900396402500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6363 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 198040 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71346 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 130 0.07% 40.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.10% 41.77% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.77% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102331 58.23% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 175740 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69979 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 130 0.09% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.36% 50.72% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 69973 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142015 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862552849000 97.86% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 68272000 0.00% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 582924500 0.03% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4256000 0.00% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40116611000 2.11% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903324912500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980840 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681008 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810058 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed -system.cpu0.kern.syscall::6 28 13.33% 25.71% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.48% 26.19% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.48% 26.67% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.29% 30.95% # number of syscalls executed -system.cpu0.kern.syscall::19 5 2.38% 33.33% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 35.24% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.95% 36.19% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.90% 38.10% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.33% 41.43% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 42.38% # number of syscalls executed -system.cpu0.kern.syscall::45 35 16.67% 59.05% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.90% 60.95% # number of syscalls executed -system.cpu0.kern.syscall::48 6 2.86% 63.81% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.29% 68.10% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.48% 68.57% # number of syscalls executed -system.cpu0.kern.syscall::59 4 1.90% 70.48% # number of syscalls executed -system.cpu0.kern.syscall::71 32 15.24% 85.71% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.43% 87.14% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.29% 91.43% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.48% 91.90% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.48% 92.38% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.33% 95.71% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 96.67% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 97.62% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.95% 98.57% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.48% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 210 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.683791 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808097 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 5 2.35% 2.35% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.45% 10.80% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.41% 12.21% # number of syscalls executed +system.cpu0.kern.syscall::6 28 13.15% 25.35% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 25.82% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.47% 26.29% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.23% 30.52% # number of syscalls executed +system.cpu0.kern.syscall::19 5 2.35% 32.86% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.88% 34.74% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.94% 35.68% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.88% 37.56% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.29% 40.85% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.94% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::45 38 17.84% 59.62% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.88% 61.50% # number of syscalls executed +system.cpu0.kern.syscall::48 6 2.82% 64.32% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.23% 68.54% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 69.01% # number of syscalls executed +system.cpu0.kern.syscall::59 4 1.88% 70.89% # number of syscalls executed +system.cpu0.kern.syscall::71 32 15.02% 85.92% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.41% 87.32% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.23% 91.55% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 92.02% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.47% 92.49% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.29% 95.77% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.94% 96.71% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.94% 97.65% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.94% 98.59% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.06% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.94% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 213 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 439 0.29% 0.29% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed -system.cpu0.kern.callpal::swpipl 138811 90.43% 92.75% # number of callpals executed -system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed -system.cpu0.kern.callpal::rdusp 6 0.00% 96.90% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.90% # number of callpals executed -system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed -system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 153508 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1099 # number of protection mode switches +system.cpu0.kern.callpal::wripir 103 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3753 2.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::tbi 37 0.02% 2.11% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.12% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169151 91.71% 93.83% # number of callpals executed +system.cpu0.kern.callpal::rdps 6371 3.45% 97.28% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.28% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.28% # number of callpals executed +system.cpu0.kern.callpal::rdusp 6 0.00% 97.29% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.29% # number of callpals executed +system.cpu0.kern.callpal::rti 4525 2.45% 99.74% # number of callpals executed +system.cpu0.kern.callpal::callsys 331 0.18% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 146 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 184440 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6935 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1104 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1099 -system.cpu0.kern.mode_good::user 1099 +system.cpu0.kern.mode_good::kernel 1104 +system.cpu0.kern.mode_good::user 1104 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.164275 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.159193 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.282193 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897960603000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1864923000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.274661 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1900909928000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1870692000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3077 # number of times the context was actually changed +system.cpu0.kern.swap_context 3754 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 74469 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 24566 38.36% 38.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 3.00% 41.37% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 37109 57.95% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 64037 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 23887 48.07% 48.07% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 23448 47.18% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 49697 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870827131500 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343570500 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 182754500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29175936000 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900529392500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.972360 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2268 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39512 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10294 33.41% 33.41% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 6.25% 39.66% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 103 0.33% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18486 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30809 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10284 45.72% 45.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 8.56% 54.28% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 103 0.46% 54.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10181 45.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22494 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1876458068500 98.58% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533952000 0.03% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 54130500 0.00% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 26455983000 1.39% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903502134000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999029 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.631868 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.776067 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed -system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed -system.cpu1.kern.syscall::6 14 12.07% 25.86% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.17% 31.03% # number of syscalls executed -system.cpu1.kern.syscall::19 5 4.31% 35.34% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.72% 37.07% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.72% 38.79% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.72% 40.52% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.45% 43.97% # number of syscalls executed -system.cpu1.kern.syscall::45 19 16.38% 60.34% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.72% 62.07% # number of syscalls executed -system.cpu1.kern.syscall::48 4 3.45% 65.52% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.86% 66.38% # number of syscalls executed -system.cpu1.kern.syscall::59 3 2.59% 68.97% # number of syscalls executed -system.cpu1.kern.syscall::71 22 18.97% 87.93% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.03% 93.97% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.72% 95.69% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.72% 97.41% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.72% 99.14% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.86% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 116 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.550741 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.730111 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 3 2.65% 2.65% # number of syscalls executed +system.cpu1.kern.syscall::3 12 10.62% 13.27% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.88% 14.16% # number of syscalls executed +system.cpu1.kern.syscall::6 14 12.39% 26.55% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.31% 31.86% # number of syscalls executed +system.cpu1.kern.syscall::19 5 4.42% 36.28% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.77% 38.05% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.77% 39.82% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.77% 41.59% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.54% 45.13% # number of syscalls executed +system.cpu1.kern.syscall::45 16 14.16% 59.29% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.77% 61.06% # number of syscalls executed +system.cpu1.kern.syscall::48 4 3.54% 64.60% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.88% 65.49% # number of syscalls executed +system.cpu1.kern.syscall::59 3 2.65% 68.14% # number of syscalls executed +system.cpu1.kern.syscall::71 22 19.47% 87.61% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.19% 93.81% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.77% 95.58% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.77% 97.35% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.77% 99.12% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 113 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 340 0.51% 0.51% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.51% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed -system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed -system.cpu1.kern.callpal::swpipl 57994 87.22% 90.51% # number of callpals executed -system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.12% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed -system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed -system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # number of callpals executed -system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 478 1.50% 1.53% # number of callpals executed +system.cpu1.kern.callpal::tbi 16 0.05% 1.58% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.60% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26108 81.82% 83.42% # number of callpals executed +system.cpu1.kern.callpal::rdps 2389 7.49% 90.91% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 90.91% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 90.92% # number of callpals executed +system.cpu1.kern.callpal::rdusp 3 0.01% 90.93% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 90.94% # number of callpals executed +system.cpu1.kern.callpal::rti 2671 8.37% 99.31% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.58% 99.89% # number of callpals executed +system.cpu1.kern.callpal::imb 34 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 66492 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches -system.cpu1.kern.mode_switch::user 641 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 1003 -system.cpu1.kern.mode_good::user 641 -system.cpu1.kern.mode_good::idle 362 -system.cpu1.kern.mode_switch_good::kernel 0.473336 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 31908 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1099 # number of protection mode switches +system.cpu1.kern.mode_switch::user 634 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 660 +system.cpu1.kern.mode_good::user 634 +system.cpu1.kern.mode_good::idle 26 +system.cpu1.kern.mode_switch_good::kernel 0.600546 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 7877089500 0.41% 0.41% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 911545000 0.05% 0.46% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1891740750000 99.54% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1825 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.348837 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2247097500 0.12% 0.12% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 912883500 0.05% 0.17% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1900342145000 99.83% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 479 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 0374f29ea..76702c28f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,146 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.864424 # Number of seconds simulated -sim_ticks 1864423957500 # Number of ticks simulated -final_tick 1864423957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.864443 # Number of seconds simulated +sim_ticks 1864443445500 # Number of ticks simulated +final_tick 1864443445500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128916 # Simulator instruction rate (inst/s) -host_op_rate 128916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4527170908 # Simulator tick rate (ticks/s) -host_mem_usage 303408 # Number of bytes of host memory used -host_seconds 411.83 # Real time elapsed on the host -sim_insts 53091408 # Number of instructions simulated -sim_ops 53091408 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 967616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24878144 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652032 # Number of bytes read from this memory -system.physmem.bytes_read::total 28497792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 967616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517760 # Number of bytes written to this memory -system.physmem.bytes_written::total 7517760 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15119 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388721 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445278 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117465 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117465 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13343609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1422440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15285039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518989 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518989 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4032216 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4032216 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4032216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518989 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.248295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.135802 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.588235 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.588235 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.382993 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382993 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014752 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.277192 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.166457 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014752 # 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number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,80 +149,80 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75953 # number of writebacks -system.l2c.writebacks::total 75953 # number of writebacks +system.l2c.writebacks::writebacks 75976 # number of writebacks +system.l2c.writebacks::total 75976 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # 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number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 389235 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 404355 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 15120 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 389235 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 404355 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 621011997 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 10975832000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11596843997 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2105000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 2105000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4797954496 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4797954496 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 621011997 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15773786496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16394798493 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 621011997 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15773786496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16394798493 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809342530 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 809342530 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103231500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1103231500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1912574030 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1912574030 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.135802 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.588235 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.588235 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.382993 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.382993 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.277192 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.166456 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.277192 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.166456 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41072.222024 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40078.405311 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.403929 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42100 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42100 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 115356 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 115356 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 15141 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 389248 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 404389 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 15141 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 389248 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 404389 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 621548498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10984970000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11606518498 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2110000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2110000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4799591496 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4799591496 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 621548498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15784561496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16406109994 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 621548498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15784561496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16406109994 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1332350000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1332350000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1882980500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1882980500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 3215330500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3215330500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248614 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.136120 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.617284 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.617284 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383479 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383479 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166814 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166814 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41050.690047 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.939962 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40156.378331 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42200 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42200 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.377340 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.377340 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41072.222024 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40525.097938 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40545.556486 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41072.222024 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40525.097938 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40545.556486 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41606.778113 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41606.778113 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41050.690047 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40551.426073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40570.119350 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41050.690047 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40551.426073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40570.119350 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -231,14 +231,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.287077 # Cycle average of tags in use +system.iocache.tagsinuse 1.286638 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1711278506000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.287077 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.080442 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.080442 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1711308746000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.286638 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.080415 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.080415 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -249,12 +249,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7639838806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7639838806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7660511804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7660511804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7660511804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7660511804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7639193806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7639193806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7659866804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7659866804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7659866804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7659866804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -273,17 +273,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183862.119898 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183862.119898 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183595.249946 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183595.249946 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183595.249946 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183595.249946 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7420000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183846.597179 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183846.597179 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183579.791588 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183579.791588 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183579.791588 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183579.791588 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7379000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7102 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7110 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1044.776119 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1037.834037 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -299,12 +299,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5478984000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5478984000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5490660000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5490660000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5490660000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5490660000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5478339000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5478339000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5490015000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5490015000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5490015000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5490015000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -315,12 +315,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131858.490566 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131858.490566 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131591.611744 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131591.611744 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131591.611744 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131591.611744 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131842.967848 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131842.967848 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131576.153385 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131576.153385 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131576.153385 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131576.153385 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -338,22 +338,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9968108 # DTB read hits -system.cpu.dtb.read_misses 43556 # DTB read misses -system.cpu.dtb.read_acv 496 # DTB read access violations -system.cpu.dtb.read_accesses 957960 # DTB read accesses -system.cpu.dtb.write_hits 6640476 # DTB write hits -system.cpu.dtb.write_misses 10042 # DTB write misses -system.cpu.dtb.write_acv 402 # DTB write access violations -system.cpu.dtb.write_accesses 340316 # DTB write accesses -system.cpu.dtb.data_hits 16608584 # DTB hits -system.cpu.dtb.data_misses 53598 # DTB misses -system.cpu.dtb.data_acv 898 # DTB access violations -system.cpu.dtb.data_accesses 1298276 # DTB accesses -system.cpu.itb.fetch_hits 1341124 # ITB hits -system.cpu.itb.fetch_misses 40235 # ITB misses -system.cpu.itb.fetch_acv 1160 # ITB acv -system.cpu.itb.fetch_accesses 1381359 # ITB accesses +system.cpu.dtb.read_hits 9936242 # DTB read hits +system.cpu.dtb.read_misses 43490 # DTB read misses +system.cpu.dtb.read_acv 516 # DTB read access violations +system.cpu.dtb.read_accesses 957786 # DTB read accesses +system.cpu.dtb.write_hits 6625146 # DTB write hits +system.cpu.dtb.write_misses 10048 # DTB write misses +system.cpu.dtb.write_acv 376 # DTB write access violations +system.cpu.dtb.write_accesses 340602 # DTB write accesses +system.cpu.dtb.data_hits 16561388 # DTB hits +system.cpu.dtb.data_misses 53538 # DTB misses +system.cpu.dtb.data_acv 892 # DTB access violations +system.cpu.dtb.data_accesses 1298388 # DTB accesses +system.cpu.itb.fetch_hits 1339050 # ITB hits +system.cpu.itb.fetch_misses 40176 # ITB misses +system.cpu.itb.fetch_acv 1137 # ITB acv +system.cpu.itb.fetch_accesses 1379226 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -366,142 +366,142 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122531860 # number of cpu cycles simulated +system.cpu.numCycles 124718167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14045558 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11719354 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 447776 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10129156 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5920510 # Number of BTB hits +system.cpu.BPredUnit.lookups 14016362 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11699457 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 447467 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10098689 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5905629 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 939631 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44501 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31544288 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71453130 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14045558 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6860141 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13465921 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2135846 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 41803348 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 34171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 276891 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 309124 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8845261 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 302298 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 88840406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.804286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.136255 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 935083 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44772 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31431497 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71249565 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14016362 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6840712 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13427140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2133623 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43145521 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33490 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 277896 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 300852 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 229 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8810652 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 301668 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 90022350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.791465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.121682 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75374485 84.84% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 882693 0.99% 85.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1758870 1.98% 87.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 855110 0.96% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2773745 3.12% 91.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 603499 0.68% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 673337 0.76% 93.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1014466 1.14% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4904201 5.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76595210 85.08% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 880275 0.98% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1754034 1.95% 88.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 853758 0.95% 88.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2767447 3.07% 92.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 598798 0.67% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 668363 0.74% 93.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009728 1.12% 94.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4894737 5.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 88840406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.114628 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.583139 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32595578 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 41593167 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12233698 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1054489 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1363473 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 614789 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43441 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70185288 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 133206 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1363473 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33740803 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16340010 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21029757 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11532133 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4834228 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66486071 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 750706 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1800875 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44431145 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80611615 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80123142 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 488473 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38259358 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6171779 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1702958 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251555 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12743501 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10564267 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6974375 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1310956 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 921637 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58920823 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2093860 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57272597 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 128544 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7527772 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3875760 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1425872 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 88840406 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.644668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.291770 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 90022350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.112384 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.571285 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32462663 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 42944944 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12200929 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1050932 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1362881 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 612569 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43257 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69997551 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 131864 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1362881 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33604793 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17288612 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21444377 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11497846 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4823839 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66302391 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7264 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 752324 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1793006 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44298032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80385832 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79896368 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 489464 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38124388 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6173636 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1698063 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251025 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12720780 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10525150 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6958577 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1307223 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 920725 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58755274 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2090184 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57106230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 126003 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7528195 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3871424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1424917 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 90022350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.634356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.284426 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 62934632 70.84% 70.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 12040664 13.55% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5383860 6.06% 90.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3443587 3.88% 94.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2613267 2.94% 97.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1328836 1.50% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 686879 0.77% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 354518 0.40% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 54163 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64211383 71.33% 71.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11984837 13.31% 84.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5359973 5.95% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3439210 3.82% 94.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2607784 2.90% 97.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1324300 1.47% 98.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 687470 0.76% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 352783 0.39% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 54610 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 88840406 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 90022350 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73519 9.73% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 364094 48.19% 57.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 318003 42.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 75162 9.94% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 361865 47.84% 57.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 319378 42.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39090989 68.25% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61973 0.11% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38979239 68.26% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61855 0.11% 68.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued @@ -529,116 +529,116 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10411715 18.18% 86.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6718707 11.73% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952679 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10375615 18.17% 86.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6703515 11.74% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949472 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57272597 # Type of FU issued -system.cpu.iq.rate 0.467410 # Inst issue rate -system.cpu.iq.fu_busy_cnt 755616 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013193 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 203573547 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68217667 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55990659 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 696212 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 338599 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327577 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57656594 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 364328 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 594908 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57106230 # Type of FU issued +system.cpu.iq.rate 0.457882 # Inst issue rate +system.cpu.iq.fu_busy_cnt 756405 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013246 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 204420366 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68047675 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55829438 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 696851 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 339603 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327742 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57490896 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 364448 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598206 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1450991 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2769 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14176 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 581838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1442254 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2799 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13958 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 583775 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18337 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 105015 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17984 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 104066 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1363473 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11404151 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 871964 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64586243 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684405 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10564267 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6974375 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1841535 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 624319 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12765 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14176 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 237440 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 422569 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 660009 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56745623 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10040371 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 526973 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1362881 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12351222 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 868923 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64407898 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684720 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10525150 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6958577 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1840963 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 621108 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12330 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13958 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 238471 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 421447 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 659918 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56579740 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10008035 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 526489 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3571560 # number of nop insts executed -system.cpu.iew.exec_refs 16706164 # number of memory reference insts executed -system.cpu.iew.exec_branches 8999941 # Number of branches executed -system.cpu.iew.exec_stores 6665793 # Number of stores executed -system.cpu.iew.exec_rate 0.463109 # Inst execution rate -system.cpu.iew.wb_sent 56430087 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56318236 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27772479 # num instructions producing a value -system.cpu.iew.wb_consumers 37631426 # num instructions consuming a value +system.cpu.iew.exec_nop 3562440 # number of nop insts executed +system.cpu.iew.exec_refs 16658473 # number of memory reference insts executed +system.cpu.iew.exec_branches 8978804 # Number of branches executed +system.cpu.iew.exec_stores 6650438 # Number of stores executed +system.cpu.iew.exec_rate 0.453661 # Inst execution rate +system.cpu.iew.wb_sent 56268334 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56157180 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27683314 # num instructions producing a value +system.cpu.iew.wb_consumers 37519561 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.459621 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738013 # average fanout of values written-back +system.cpu.iew.wb_rate 0.450273 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737837 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56285915 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56285915 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8189376 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 616441 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 87476933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.643437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.558745 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56104643 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56104643 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 8193317 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 665267 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 615735 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 88659469 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.632811 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.547834 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 66214375 75.69% 75.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8956758 10.24% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4831410 5.52% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2600718 2.97% 94.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1447358 1.65% 96.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 605400 0.69% 96.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 515608 0.59% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 488345 0.56% 97.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1816961 2.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67465140 76.09% 76.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8924230 10.07% 86.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4814714 5.43% 91.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2600553 2.93% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1445109 1.63% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 596766 0.67% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 516883 0.58% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 484830 0.55% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1811244 2.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 87476933 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56285915 # Number of instructions committed -system.cpu.commit.committedOps 56285915 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 88659469 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56104643 # Number of instructions committed +system.cpu.commit.committedOps 56104643 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15505813 # Number of memory references committed -system.cpu.commit.loads 9113276 # Number of loads committed -system.cpu.commit.membars 227944 # Number of memory barriers committed -system.cpu.commit.branches 8463135 # Number of branches committed +system.cpu.commit.refs 15457698 # Number of memory references committed +system.cpu.commit.loads 9082896 # Number of loads committed +system.cpu.commit.membars 226441 # Number of memory barriers committed +system.cpu.commit.branches 8439531 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52124087 # Number of committed integer instructions. -system.cpu.commit.function_calls 744545 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1816961 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 51953528 # Number of committed integer instructions. +system.cpu.commit.function_calls 739583 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1811244 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149884134 # The number of ROB reads -system.cpu.rob.rob_writes 130314855 # The number of ROB writes -system.cpu.timesIdled 1389359 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33691454 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3606309626 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53091408 # Number of Instructions Simulated -system.cpu.committedOps 53091408 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53091408 # Number of Instructions Simulated -system.cpu.cpi 2.307941 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.307941 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433287 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433287 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74386687 # number of integer regfile reads -system.cpu.int_regfile_writes 40627933 # number of integer regfile writes -system.cpu.fp_regfile_reads 166209 # number of floating regfile reads -system.cpu.fp_regfile_writes 166935 # number of floating regfile writes -system.cpu.misc_regfile_reads 1998011 # number of misc regfile reads -system.cpu.misc_regfile_writes 950291 # number of misc regfile writes +system.cpu.rob.rob_reads 150896568 # The number of ROB reads +system.cpu.rob.rob_writes 129959625 # The number of ROB writes +system.cpu.timesIdled 1384663 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34695817 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3604162300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52917560 # Number of Instructions Simulated +system.cpu.committedOps 52917560 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52917560 # Number of Instructions Simulated +system.cpu.cpi 2.356839 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.356839 # CPI: Total CPI of All Threads +system.cpu.ipc 0.424297 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424297 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74164887 # number of integer regfile reads +system.cpu.int_regfile_writes 40500361 # number of integer regfile writes +system.cpu.fp_regfile_reads 166351 # number of floating regfile reads +system.cpu.fp_regfile_writes 166958 # number of floating regfile writes +system.cpu.misc_regfile_reads 1995249 # number of misc regfile reads +system.cpu.misc_regfile_writes 947406 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -670,245 +670,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1024388 # number of replacements -system.cpu.icache.tagsinuse 509.959478 # Cycle average of tags in use -system.cpu.icache.total_refs 7759501 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1024896 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.571013 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23722278000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.959478 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996015 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996015 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7759502 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7759502 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7759502 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7759502 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7759502 # number of overall hits -system.cpu.icache.overall_hits::total 7759502 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1085755 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1085755 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1085755 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1085755 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1085755 # number of overall misses -system.cpu.icache.overall_misses::total 1085755 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17501015990 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17501015990 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17501015990 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17501015990 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17501015990 # 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number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23276 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23276 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3794169 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3794169 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3794169 # number of overall misses +system.cpu.dcache.overall_misses::total 3794169 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48828356500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48828356500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 75021141961 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 75021141961 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 428009500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 428009500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 154000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 154000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 123849498461 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 123849498461 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 123849498461 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 123849498461 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9074666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9074666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6140457 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6140457 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213415 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 213415 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 219627 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219627 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15215123 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15215123 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15215123 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15215123 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.201299 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.201299 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320408 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.320408 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109064 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109064 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000023 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.249368 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.249368 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.249368 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.249368 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26730.086291 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26730.086291 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38131.155537 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38131.155537 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18388.447328 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18388.447328 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30800 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30800 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.061664 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32642.061664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.061664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32642.061664 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 733938028 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72544 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72096 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10087.092303 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10180.010375 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842689 # number of writebacks -system.cpu.dcache.writebacks::total 842689 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 745053 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 745053 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1667452 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2412505 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2412505 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2412505 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2412505 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085528 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1085528 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300544 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300544 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18217 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18217 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386072 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386072 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386072 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386072 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28234901500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28234901500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9648960448 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9648960448 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 269943500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 269943500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 85500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 85500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37883861948 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37883861948 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37883861948 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37883861948 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904971500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904971500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1224983998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1224983998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2129955498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2129955498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085086 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085086 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090798 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090798 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090798 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090798 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26010.293148 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26010.293148 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32104.984455 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32104.984455 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14818.219246 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14818.219246 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 21375 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 21375 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27331.813894 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27331.813894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27331.813894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27331.813894 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840935 # number of writebacks +system.cpu.dcache.writebacks::total 840935 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 742319 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 742319 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667295 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1667295 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5261 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5261 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2409614 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2409614 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2409614 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2409614 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084400 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084400 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300155 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300155 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18015 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18015 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384555 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384555 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384555 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384555 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28231864000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28231864000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9653593940 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9653593940 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 269637000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 269637000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 138000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 138000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37885457940 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37885457940 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37885457940 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37885457940 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423534500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423534500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2001030998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2001030998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3424565498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3424565498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119498 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119498 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048882 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048882 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084413 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084413 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090999 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090999 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090999 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090999 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26034.548137 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26034.548137 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32162.029418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32162.029418 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14967.360533 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14967.360533 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27600 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27600 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27362.912950 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27362.912950 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27362.912950 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27362.912950 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -917,28 +917,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211669 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74897 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1886 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105867 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182893 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73530 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1886 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73533 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149192 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1824783514500 97.87% 97.87% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 98568000 0.01% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384878500 0.02% 97.90% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 39156084500 2.10% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1864423045500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6425 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211112 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74681 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 133 0.07% 41.03% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1886 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105636 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182336 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73314 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1886 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73315 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148648 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1823792488500 97.82% 97.82% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 71545000 0.00% 97.82% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 571672500 0.03% 97.85% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 40006830500 2.15% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1864442536500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981695 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694579 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815734 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694034 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815242 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -974,32 +974,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175546 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6791 3.53% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed +system.cpu.kern.callpal::swpipl 175205 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6791 3.54% 96.97% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed +system.cpu.kern.callpal::rti 5112 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192513 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches -system.cpu.kern.mode_switch::user 1736 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1736 +system.cpu.kern.callpal::total 192064 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches +system.cpu.kern.mode_switch::user 1735 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2104 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1905 +system.cpu.kern.mode_good::user 1735 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320013 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325641 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.389059 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29626491000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2782272500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832014274000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080798 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393229 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29922134000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2785239500 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1831735155000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |