diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
6 files changed, 2283 insertions, 2273 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index bf1bde417..1c28eff64 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -941,7 +941,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -1003,7 +1003,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port[0] slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -1060,7 +1060,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 94dc81bdc..11f244941 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:47:55 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 11:07:21 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 106801000 -Exiting @ tick 1896395899500 because m5_exit instruction encountered +info: Launching CPU 1 @ 112168000 +Exiting @ tick 1900530800500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 0c462a770..3f76d2026 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896396 # Number of seconds simulated -sim_ticks 1896395899500 # Number of ticks simulated -final_tick 1896395899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.900531 # Number of seconds simulated +sim_ticks 1900530800500 # Number of ticks simulated +final_tick 1900530800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196112 # Simulator instruction rate (inst/s) -host_op_rate 196112 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6628227410 # Simulator tick rate (ticks/s) -host_mem_usage 302056 # Number of bytes of host memory used -host_seconds 286.11 # Real time elapsed on the host -sim_insts 56109524 # Number of instructions simulated -sim_ops 56109524 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 881728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24808704 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 99648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 472640 # Number of bytes read from this memory -system.physmem.bytes_read::total 28913408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 881728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 99648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7865856 # Number of bytes written to this memory -system.physmem.bytes_written::total 7865856 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387636 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7385 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451772 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122904 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122904 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 464949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13082028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1397750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 249231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15246504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 464949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4147792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4147792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4147792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 464949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13082028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 249231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19394296 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 344859 # number of replacements -system.l2c.tagsinuse 65321.127934 # Cycle average of tags in use -system.l2c.total_refs 2609636 # Total number of references to valid blocks. -system.l2c.sampled_refs 410035 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.364423 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6312493000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53767.491128 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5338.607060 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6047.920982 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 140.590955 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 26.517809 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820427 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.081461 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.092284 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002145 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000405 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996721 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 978177 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 784326 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 102747 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 33274 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1898524 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 832872 # number of Writeback hits -system.l2c.Writeback_hits::total 832872 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 159 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 200 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 175658 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7994 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183652 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 978177 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 959984 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 102747 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 41268 # number of demand (read+write) hits -system.l2c.demand_hits::total 2082176 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 978177 # number of overall hits -system.l2c.overall_hits::cpu0.data 959984 # number of overall hits -system.l2c.overall_hits::cpu1.inst 102747 # number of overall hits -system.l2c.overall_hits::cpu1.data 41268 # number of overall hits -system.l2c.overall_hits::total 2082176 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13779 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273160 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1574 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 765 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289278 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2448 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 557 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3005 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 42 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 122 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114897 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6716 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121613 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13779 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 388057 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1574 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 7481 # number of demand (read+write) misses -system.l2c.demand_misses::total 410891 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13779 # number of overall misses -system.l2c.overall_misses::cpu0.data 388057 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1574 # number of overall misses -system.l2c.overall_misses::cpu1.data 7481 # number of overall misses -system.l2c.overall_misses::total 410891 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 720793500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14208419500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 82364000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 41213000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15052790000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2256000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1409000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 3665000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 419000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 157000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 576000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6027292500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 352112000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6379404500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 720793500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20235712000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 82364000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 393325000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21432194500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 720793500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20235712000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 82364000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 393325000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21432194500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 991956 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1057486 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 104321 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 34039 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2187802 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 832872 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832872 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2607 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 598 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3205 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 71 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 102 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 173 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 290555 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 14710 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305265 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 991956 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1348041 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 104321 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 48749 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2493067 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 991956 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1348041 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 104321 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 48749 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2493067 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013891 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.258311 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015088 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022474 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.132223 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939010 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.931438 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.937598 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.591549 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.784314 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.705202 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.395440 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.456560 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.398385 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013891 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.287867 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015088 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.153460 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.164813 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013891 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.287867 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015088 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.153460 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.164813 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52311.016765 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52015.007688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52327.827192 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53873.202614 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52035.723422 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 921.568627 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2529.622980 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1219.633943 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9976.190476 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1962.500000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4721.311475 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52458.223452 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52428.826683 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52456.600035 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52311.016765 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52146.236249 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52327.827192 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52576.527202 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52160.291902 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52311.016765 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52146.236249 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52327.827192 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52576.527202 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52160.291902 # average overall miss latency +host_inst_rate 119697 # Simulator instruction rate (inst/s) +host_op_rate 119697 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3968630665 # Simulator tick rate (ticks/s) +host_mem_usage 303044 # Number of bytes of host memory used +host_seconds 478.89 # Real time elapsed on the host +sim_insts 57321719 # Number of instructions simulated +sim_ops 57321719 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 875648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24657536 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 107456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 693056 # Number of bytes read from this memory +system.physmem.bytes_read::total 28984512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 875648 # 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number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses -system.iocache.demand_misses::total 41729 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses -system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20390998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20390998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5719191806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5719191806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5739582804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5739582804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5739582804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5739582804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21238998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21238998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7637775806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7637775806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7659014804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7659014804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7659014804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7659014804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115203.378531 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115203.378531 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137639.386937 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137639.386937 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137544.221141 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137544.221141 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64663068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119320.213483 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183812.471265 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183537.378481 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183537.378481 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7710000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7151 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6183.711198 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1078.170885 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11186998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11186998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3558333000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3558333000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3569519998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3569519998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3569519998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3569519998 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476916000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5476916000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5488898000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5488898000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5488898000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5488898000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63203.378531 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63203.378531 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85635.661340 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85635.661340 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9453856 # DTB read hits -system.cpu0.dtb.read_misses 36184 # DTB read misses -system.cpu0.dtb.read_acv 571 # DTB read access violations -system.cpu0.dtb.read_accesses 675976 # DTB read accesses -system.cpu0.dtb.write_hits 6300368 # DTB write hits -system.cpu0.dtb.write_misses 8347 # DTB write misses -system.cpu0.dtb.write_acv 346 # DTB write access violations -system.cpu0.dtb.write_accesses 234133 # DTB write accesses -system.cpu0.dtb.data_hits 15754224 # DTB hits -system.cpu0.dtb.data_misses 44531 # DTB misses -system.cpu0.dtb.data_acv 917 # DTB access violations -system.cpu0.dtb.data_accesses 910109 # DTB accesses -system.cpu0.itb.fetch_hits 1108660 # ITB hits -system.cpu0.itb.fetch_misses 28136 # ITB misses -system.cpu0.itb.fetch_acv 1047 # ITB acv -system.cpu0.itb.fetch_accesses 1136796 # ITB accesses +system.cpu0.dtb.read_hits 8334313 # DTB read hits +system.cpu0.dtb.read_misses 29661 # DTB read misses +system.cpu0.dtb.read_acv 416 # DTB read access violations +system.cpu0.dtb.read_accesses 650050 # DTB read accesses +system.cpu0.dtb.write_hits 5360515 # DTB write hits +system.cpu0.dtb.write_misses 6017 # DTB write misses +system.cpu0.dtb.write_acv 275 # DTB write access violations +system.cpu0.dtb.write_accesses 211537 # DTB write accesses +system.cpu0.dtb.data_hits 13694828 # DTB hits +system.cpu0.dtb.data_misses 35678 # DTB misses +system.cpu0.dtb.data_acv 691 # DTB access violations +system.cpu0.dtb.data_accesses 861587 # DTB accesses +system.cpu0.itb.fetch_hits 972456 # ITB hits +system.cpu0.itb.fetch_misses 29747 # ITB misses +system.cpu0.itb.fetch_acv 802 # ITB acv +system.cpu0.itb.fetch_accesses 1002203 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,279 +483,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 111705884 # number of cpu cycles simulated +system.cpu0.numCycles 107494535 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13423445 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11229595 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 405618 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9732141 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5644182 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11769770 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9862090 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 345528 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8388023 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5075121 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 889528 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 35792 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28347650 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 67883922 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13423445 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6533710 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12779049 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1882893 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34959873 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 30735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 200156 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 304542 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 145 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8317299 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 264993 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 77847394 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.872013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.211541 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 768289 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 29261 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 25151812 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60423976 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11769770 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5843410 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11477495 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1678868 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36441754 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 35468 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 189532 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 310248 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7504127 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 232204 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74712100 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.808758 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.135218 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 65068345 83.58% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 840291 1.08% 84.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1663244 2.14% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 773630 0.99% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2654406 3.41% 91.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 587924 0.76% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 633021 0.81% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 971381 1.25% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4655152 5.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63234605 84.64% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 741221 0.99% 85.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1559530 2.09% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686170 0.92% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2492076 3.34% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 531561 0.71% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568906 0.76% 93.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 718608 0.96% 94.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4179423 5.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77847394 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.120168 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.607702 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29292805 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34750406 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11695757 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 922620 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1185805 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 575553 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 39816 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 66717094 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 118720 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1185805 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30365496 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12492089 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18756431 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10933791 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4113780 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 63191653 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6630 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 474971 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1473898 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 42180100 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 76536527 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 76096983 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 439544 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36808161 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5371931 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1596682 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238140 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11595704 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9967009 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6589337 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1245862 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 818929 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55970736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2008418 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54697537 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 108647 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6579388 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3235320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1364468 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77847394 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.702625 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.358580 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74712100 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109492 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.562112 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26235752 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36073897 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10433111 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 896014 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1073325 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 504398 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32602 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 59387121 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 93497 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1073325 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27172169 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15317742 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17291837 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9793019 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4064006 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56407383 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7139 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 656540 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1492805 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 37953017 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 68861567 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 68508934 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 352633 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33050954 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4902063 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1333181 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 200244 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10589201 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8773580 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5638577 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132250 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 738910 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50116652 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1669804 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 48856794 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 108488 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5944129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3041029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1132337 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74712100 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.653934 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.297915 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53933184 69.28% 69.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10617760 13.64% 82.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4942911 6.35% 89.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3320001 4.26% 93.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2532609 3.25% 96.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1408678 1.81% 98.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 686959 0.88% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 303964 0.39% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 101328 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52667189 70.49% 70.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10185163 13.63% 84.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4563652 6.11% 90.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2983683 3.99% 94.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2257783 3.02% 97.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1142078 1.53% 98.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 582516 0.78% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 283628 0.38% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 46408 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77847394 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74712100 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 87681 11.80% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 349168 46.97% 58.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 306477 41.23% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 73121 11.93% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 287582 46.92% 58.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 252262 41.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3778 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37484034 68.53% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60241 0.11% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 16826 0.03% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9867065 18.04% 86.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6373328 11.65% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 890382 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33934109 69.46% 69.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 53582 0.11% 69.58% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.58% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8675974 17.76% 87.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5426955 11.11% 98.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 742930 1.52% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54697537 # Type of FU issued -system.cpu0.iq.rate 0.489657 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 743326 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013590 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 187461216 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 64264846 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53535096 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 633224 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 306465 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 298013 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55105300 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 331785 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 567631 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 48856794 # Type of FU issued +system.cpu0.iq.rate 0.454505 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 612965 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012546 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 172645923 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57499135 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 47860626 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 501218 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 243758 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 236014 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 49202996 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 262296 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 518056 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1269870 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3726 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13071 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 496722 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1116510 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2510 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12661 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 476371 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18808 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 143577 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18849 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 94368 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1185805 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8725439 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 608869 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61441844 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 619329 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9967009 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6589337 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1767664 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 482033 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 12133 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13071 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 215254 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 393579 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 608833 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54218225 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9516523 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 479311 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1073325 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10798667 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 779958 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54837290 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 559703 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8773580 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5638577 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1469305 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 544312 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 8344 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12661 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186183 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 327984 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 514167 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 48431427 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8385093 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 425367 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3462690 # number of nop insts executed -system.cpu0.iew.exec_refs 15839640 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8639850 # Number of branches executed -system.cpu0.iew.exec_stores 6323117 # Number of stores executed -system.cpu0.iew.exec_rate 0.485366 # Inst execution rate -system.cpu0.iew.wb_sent 53937806 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53833109 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26624302 # num instructions producing a value -system.cpu0.iew.wb_consumers 35973761 # num instructions consuming a value +system.cpu0.iew.exec_nop 3050834 # number of nop insts executed +system.cpu0.iew.exec_refs 13764236 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7758760 # Number of branches executed +system.cpu0.iew.exec_stores 5379143 # Number of stores executed +system.cpu0.iew.exec_rate 0.450548 # Inst execution rate +system.cpu0.iew.wb_sent 48183951 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48096640 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24100280 # num instructions producing a value +system.cpu0.iew.wb_consumers 32401803 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.481918 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.740103 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.447433 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743794 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 54183968 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 54183968 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 7167159 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 643950 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 567683 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76661589 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.706794 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.627118 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 48294177 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 48294177 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6449436 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 537467 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 480768 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73638775 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.655825 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560295 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56437400 73.62% 73.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8432395 11.00% 84.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4492859 5.86% 90.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2495159 3.25% 93.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1450592 1.89% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 646072 0.84% 96.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 460772 0.60% 97.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 487702 0.64% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1758638 2.29% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55222738 74.99% 74.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7735232 10.50% 85.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4278280 5.81% 91.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2283958 3.10% 94.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1242509 1.69% 96.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 524248 0.71% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 435052 0.59% 97.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 385141 0.52% 97.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1531617 2.08% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76661589 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 54183968 # Number of instructions committed -system.cpu0.commit.committedOps 54183968 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73638775 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48294177 # Number of instructions committed +system.cpu0.commit.committedOps 48294177 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14789754 # Number of memory references committed -system.cpu0.commit.loads 8697139 # Number of loads committed -system.cpu0.commit.membars 219715 # Number of memory barriers committed -system.cpu0.commit.branches 8176675 # Number of branches committed -system.cpu0.commit.fp_insts 295518 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 50137398 # Number of committed integer instructions. -system.cpu0.commit.function_calls 709743 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1758638 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12819276 # Number of memory references committed +system.cpu0.commit.loads 7657070 # Number of loads committed +system.cpu0.commit.membars 181890 # Number of memory barriers committed +system.cpu0.commit.branches 7325526 # Number of branches committed +system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 44748110 # Number of committed integer instructions. +system.cpu0.commit.function_calls 610965 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1531617 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 136054419 # The number of ROB reads -system.cpu0.rob.rob_writes 123888625 # The number of ROB writes -system.cpu0.timesIdled 1249831 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33858490 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3681079567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 51051860 # Number of Instructions Simulated -system.cpu0.committedOps 51051860 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 51051860 # Number of Instructions Simulated -system.cpu0.cpi 2.188086 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.188086 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.457020 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.457020 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71111535 # number of integer regfile reads -system.cpu0.int_regfile_writes 38857328 # number of integer regfile writes -system.cpu0.fp_regfile_reads 146185 # number of floating regfile reads -system.cpu0.fp_regfile_writes 148692 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1886112 # number of misc regfile reads -system.cpu0.misc_regfile_writes 899559 # number of misc regfile writes +system.cpu0.rob.rob_reads 126666255 # The number of ROB reads +system.cpu0.rob.rob_writes 110560293 # The number of ROB writes +system.cpu0.timesIdled 1221795 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32782435 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693291566 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 45532520 # Number of Instructions Simulated +system.cpu0.committedOps 45532520 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 45532520 # Number of Instructions Simulated +system.cpu0.cpi 2.360830 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.360830 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423580 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423580 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 63860317 # number of integer regfile reads +system.cpu0.int_regfile_writes 34945795 # number of integer regfile writes +system.cpu0.fp_regfile_reads 117013 # number of floating regfile reads +system.cpu0.fp_regfile_writes 117648 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1550179 # number of misc regfile reads +system.cpu0.misc_regfile_writes 750147 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -787,247 +787,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 991395 # number of replacements -system.cpu0.icache.tagsinuse 510.024196 # Cycle average of tags in use -system.cpu0.icache.total_refs 7272203 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 991905 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.331552 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23165696000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.024196 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996141 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996141 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7272203 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7272203 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7272203 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7272203 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7272203 # number of overall hits -system.cpu0.icache.overall_hits::total 7272203 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1045096 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1045096 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1045096 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1045096 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1045096 # number of overall misses -system.cpu0.icache.overall_misses::total 1045096 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15554108994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 15554108994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 15554108994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 15554108994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 15554108994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 15554108994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8317299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8317299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8317299 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8317299 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8317299 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8317299 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125653 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125653 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125653 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125653 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125653 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125653 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14882.947590 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14882.947590 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14882.947590 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14882.947590 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1419995 # number of cycles access was blocked +system.cpu0.icache.replacements 790628 # number of replacements +system.cpu0.icache.tagsinuse 510.000717 # Cycle average of tags in use +system.cpu0.icache.total_refs 6669453 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 791140 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.430180 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.000717 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6669453 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6669453 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6669453 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6669453 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6669453 # number of overall hits +system.cpu0.icache.overall_hits::total 6669453 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 834673 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 834673 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 834673 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 834673 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 834673 # number of overall misses +system.cpu0.icache.overall_misses::total 834673 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13767352493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13767352493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13767352493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13767352493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13767352493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13767352493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7504126 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7504126 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7504126 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7504126 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7504126 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7504126 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111229 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111229 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111229 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111229 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111229 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111229 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16494.306744 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16494.306744 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1480996 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11007.713178 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 9141.950617 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 253 # number of writebacks -system.cpu0.icache.writebacks::total 253 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53062 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53062 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 53062 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53062 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 53062 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53062 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 992034 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 992034 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 992034 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 992034 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 992034 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 992034 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11805368995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11805368995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11805368995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11805368995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11805368995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11805368995 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119274 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.119274 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.119274 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11900.165715 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 247 # number of writebacks +system.cpu0.icache.writebacks::total 247 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43336 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43336 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43336 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43336 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43336 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43336 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791337 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 791337 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 791337 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 791337 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 791337 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 791337 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10689365997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10689365997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10689365997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10689365997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10689365997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10689365997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105454 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105454 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1352160 # number of replacements -system.cpu0.dcache.tagsinuse 506.886378 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11309312 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1352672 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.360720 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19277000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.886378 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.990012 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.990012 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6911324 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6911324 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3997215 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3997215 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 183850 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 183850 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 210761 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 210761 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10908539 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10908539 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10908539 # number of overall hits -system.cpu0.dcache.overall_hits::total 10908539 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1709932 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1709932 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1869031 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1869031 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22271 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22271 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 641 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 641 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3578963 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3578963 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3578963 # number of overall misses -system.cpu0.dcache.overall_misses::total 3578963 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36329127500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36329127500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 56639435392 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 56639435392 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326225500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 326225500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5918000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5918000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 92968562892 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 92968562892 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 92968562892 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 92968562892 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8621256 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8621256 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5866246 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5866246 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 206121 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 206121 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211402 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 211402 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14487502 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14487502 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14487502 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14487502 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198339 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.198339 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318608 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.318608 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.108048 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.108048 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003032 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003032 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247038 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247038 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247038 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247038 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21245.948669 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21245.948669 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30304.171195 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30304.171195 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.995151 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.995151 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9232.449298 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9232.449298 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25976.396764 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25976.396764 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 790531306 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 99401 # number of cycles access was blocked +system.cpu0.dcache.replacements 1206208 # number of replacements +system.cpu0.dcache.tagsinuse 505.878050 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9822290 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1206649 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.140139 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.878050 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.988043 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.988043 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6113680 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6113680 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3377171 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3377171 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150549 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 150549 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171656 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171656 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9490851 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9490851 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9490851 # number of overall hits +system.cpu0.dcache.overall_hits::total 9490851 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1478314 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1478314 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1593619 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1593619 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18637 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18637 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4699 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4699 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3071933 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3071933 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3071933 # number of overall misses +system.cpu0.dcache.overall_misses::total 3071933 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41272950000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41272950000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65317405497 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 65317405497 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315155000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 315155000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68652000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 68652000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 106590355497 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 106590355497 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591994 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7591994 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970790 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4970790 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169186 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 169186 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176355 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 176355 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12562784 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12562784 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12562784 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12562784 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194720 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.194720 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320597 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320597 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110157 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110157 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026645 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026645 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244526 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.244526 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244526 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.244526 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 716537144 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 65430 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7952.951238 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 805259 # number of writebacks -system.cpu0.dcache.writebacks::total 805259 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 661851 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 661851 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1575507 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1575507 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5029 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5029 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2237358 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2237358 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2237358 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2237358 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1048081 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1048081 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 293524 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 293524 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17242 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17242 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1341605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1341605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1341605 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1341605 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23566810500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23566810500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8456840306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8456840306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195574000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195574000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3991500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3991500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32023650806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 32023650806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32023650806 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 32023650806 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 917307000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 917307000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253595498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253595498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2170902498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2170902498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121569 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121569 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050036 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050036 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083650 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083650 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092604 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092604 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22485.676680 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22485.676680 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28811.409990 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28811.409990 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11342.883656 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.883656 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6236.718750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6236.718750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 693284 # number of writebacks +system.cpu0.dcache.writebacks::total 693284 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515563 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 515563 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344321 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1344321 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3732 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3732 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1859884 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1859884 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1859884 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1859884 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962751 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 962751 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249298 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249298 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14905 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14905 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4699 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4699 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212049 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1212049 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212049 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1212049 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25942792600 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25942792600 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8699231964 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8699231964 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186934001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186934001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 54037501 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 54037501 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34642024564 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34642024564 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34642024564 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34642024564 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918343000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918343000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327727998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327727998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246070998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246070998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126811 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126811 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050153 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050153 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088098 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088098 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026645 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026645 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096479 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096479 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1039,22 +1039,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1211336 # DTB read hits -system.cpu1.dtb.read_misses 9865 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 283619 # DTB read accesses -system.cpu1.dtb.write_hits 674221 # DTB write hits -system.cpu1.dtb.write_misses 1908 # DTB write misses -system.cpu1.dtb.write_acv 40 # DTB write access violations -system.cpu1.dtb.write_accesses 107232 # DTB write accesses -system.cpu1.dtb.data_hits 1885557 # DTB hits -system.cpu1.dtb.data_misses 11773 # DTB misses -system.cpu1.dtb.data_acv 46 # DTB access violations -system.cpu1.dtb.data_accesses 390851 # DTB accesses -system.cpu1.itb.fetch_hits 332989 # ITB hits -system.cpu1.itb.fetch_misses 6158 # ITB misses -system.cpu1.itb.fetch_acv 143 # ITB acv -system.cpu1.itb.fetch_accesses 339147 # ITB accesses +system.cpu1.dtb.read_hits 2499316 # DTB read hits +system.cpu1.dtb.read_misses 12569 # DTB read misses +system.cpu1.dtb.read_acv 105 # DTB read access violations +system.cpu1.dtb.read_accesses 313735 # DTB read accesses +system.cpu1.dtb.write_hits 1734639 # DTB write hits +system.cpu1.dtb.write_misses 3525 # DTB write misses +system.cpu1.dtb.write_acv 140 # DTB write access violations +system.cpu1.dtb.write_accesses 132367 # DTB write accesses +system.cpu1.dtb.data_hits 4233955 # DTB hits +system.cpu1.dtb.data_misses 16094 # DTB misses +system.cpu1.dtb.data_acv 245 # DTB access violations +system.cpu1.dtb.data_accesses 446102 # DTB accesses +system.cpu1.itb.fetch_hits 489806 # ITB hits +system.cpu1.itb.fetch_misses 8851 # ITB misses +system.cpu1.itb.fetch_acv 360 # ITB acv +system.cpu1.itb.fetch_accesses 498657 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1067,520 +1067,520 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 8872891 # number of cpu cycles simulated +system.cpu1.numCycles 22717311 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1582523 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1301899 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 53959 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 749480 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 495600 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3442703 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2849702 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 108899 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2361843 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1192387 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 108561 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5012 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3100077 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 7469135 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1582523 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 604161 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1348473 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 293042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3524434 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 23987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 56676 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47433 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 951392 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 34043 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 8293149 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.900639 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.276932 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 236332 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 10679 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 9037199 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16321027 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3442703 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1428719 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2924126 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 526603 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 8306285 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 28121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 87140 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 64229 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1963514 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 75345 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 20778311 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.785484 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.154367 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 6944676 83.74% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 71085 0.86% 84.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 161786 1.95% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 117935 1.42% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 195029 2.35% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 79896 0.96% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 91030 1.10% 92.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 58799 0.71% 93.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 572913 6.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 17854185 85.93% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 203613 0.98% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 301133 1.45% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 225724 1.09% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 404540 1.95% 91.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151692 0.73% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 164507 0.79% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 309022 1.49% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1163895 5.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 8293149 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.178355 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.841793 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3156648 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 3626684 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1266182 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 55854 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 187780 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 69682 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4376 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 7275177 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13096 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 187780 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3279437 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 303001 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 2955129 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1188563 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 379237 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 6712088 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 36332 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 73621 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 4503320 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 8147567 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 8100022 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 47545 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3660294 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 843026 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 283944 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 19782 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1166048 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1294582 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 736122 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 125256 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 86989 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 5902743 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 293921 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 5640439 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22605 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1087589 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 606184 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 224688 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 8293149 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.680132 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.353961 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 20778311 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.151545 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.718440 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8812255 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8762880 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2709089 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 172906 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 321180 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 151088 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 10133 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 16020033 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 29351 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 321180 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 9094333 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 882455 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6951469 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2594850 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 934022 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14843152 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 114 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 83650 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 279958 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9660007 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 17630674 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17422680 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 207994 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 8331005 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1328994 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 594043 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 64597 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2775458 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2641121 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1825529 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 246953 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 159017 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12975245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 664400 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12700763 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 35708 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1746535 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 829425 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 468662 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 20778311 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.611251 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.284414 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 5841725 70.44% 70.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1091278 13.16% 83.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 496152 5.98% 89.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 349787 4.22% 93.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 258149 3.11% 96.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 126242 1.52% 98.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 71640 0.86% 99.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 51558 0.62% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 6618 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15115816 72.75% 72.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2653114 12.77% 85.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1112593 5.35% 90.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 724594 3.49% 94.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 603153 2.90% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 287847 1.39% 98.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 182303 0.88% 99.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 88112 0.42% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10779 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 8293149 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 20778311 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3067 2.40% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 73236 57.36% 59.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 51382 40.24% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3869 1.53% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 134765 53.16% 54.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 114892 45.32% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3484656 61.78% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10025 0.18% 62.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8917 0.16% 62.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1261676 22.37% 84.58% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 692210 12.27% 96.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 177678 3.15% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7927502 62.42% 62.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 20764 0.16% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10543 0.08% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2623377 20.66% 83.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1764952 13.90% 97.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 349391 2.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 5640439 # Type of FU issued -system.cpu1.iq.rate 0.635693 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 127685 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.022637 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 19654183 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 7250568 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 5466934 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 70134 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 35039 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 33778 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 5728452 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 36154 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 64737 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12700763 # Type of FU issued +system.cpu1.iq.rate 0.559079 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 253526 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 46169663 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15243166 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 12341001 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 299407 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 145151 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 140846 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12794667 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 156799 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 115193 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 237812 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 428 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1426 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 105246 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 347930 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 808 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2222 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 153073 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 373 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 23964 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 370 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 11635 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 187780 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 210633 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 9248 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 6437285 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 88203 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1294582 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 736122 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 274301 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 3887 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1426 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 25150 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 66283 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 91433 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 5579037 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1224301 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 61402 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 321180 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 537224 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 73444 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 14366092 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 206312 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2641121 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1825529 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 596088 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 55197 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6016 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2222 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 53937 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 130013 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 183950 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12579473 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2523314 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 121289 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 240621 # number of nop insts executed -system.cpu1.iew.exec_refs 1903575 # number of memory reference insts executed -system.cpu1.iew.exec_branches 816845 # Number of branches executed -system.cpu1.iew.exec_stores 679274 # Number of stores executed -system.cpu1.iew.exec_rate 0.628773 # Inst execution rate -system.cpu1.iew.wb_sent 5526738 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 5500712 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2655801 # num instructions producing a value -system.cpu1.iew.wb_consumers 3693565 # num instructions consuming a value +system.cpu1.iew.exec_nop 726447 # number of nop insts executed +system.cpu1.iew.exec_refs 4269906 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1887172 # Number of branches executed +system.cpu1.iew.exec_stores 1746592 # Number of stores executed +system.cpu1.iew.exec_rate 0.553740 # Inst execution rate +system.cpu1.iew.wb_sent 12515990 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 12481847 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5700900 # num instructions producing a value +system.cpu1.iew.wb_consumers 8040202 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.619946 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.719035 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.549442 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709049 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5260797 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 5260797 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1110508 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 69233 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 85933 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 8105369 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.649051 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577854 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 12433159 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 12433159 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1857667 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 195738 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 173364 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 20457131 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.607767 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.554530 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6083727 75.06% 75.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 977563 12.06% 87.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 351716 4.34% 91.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 209459 2.58% 94.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 128681 1.59% 95.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 67803 0.84% 96.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 72265 0.89% 97.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 49144 0.61% 97.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 165011 2.04% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 15844350 77.45% 77.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2122437 10.38% 87.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 810532 3.96% 91.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 497134 2.43% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 362445 1.77% 95.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133722 0.65% 96.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 129038 0.63% 97.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 154146 0.75% 98.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 403327 1.97% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 8105369 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5260797 # Number of instructions committed -system.cpu1.commit.committedOps 5260797 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 20457131 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 12433159 # Number of instructions committed +system.cpu1.commit.committedOps 12433159 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1687646 # Number of memory references committed -system.cpu1.commit.loads 1056770 # Number of loads committed -system.cpu1.commit.membars 18284 # Number of memory barriers committed -system.cpu1.commit.branches 746127 # Number of branches committed -system.cpu1.commit.fp_insts 32538 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 4917553 # Number of committed integer instructions. -system.cpu1.commit.function_calls 83297 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 165011 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3965647 # Number of memory references committed +system.cpu1.commit.loads 2293191 # Number of loads committed +system.cpu1.commit.membars 64658 # Number of memory barriers committed +system.cpu1.commit.branches 1777478 # Number of branches committed +system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 11488003 # Number of committed integer instructions. +system.cpu1.commit.function_calls 194670 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 403327 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 14229924 # The number of ROB reads -system.cpu1.rob.rob_writes 12929135 # The number of ROB writes -system.cpu1.timesIdled 74630 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 579742 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3783284242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5057664 # Number of Instructions Simulated -system.cpu1.committedOps 5057664 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5057664 # Number of Instructions Simulated -system.cpu1.cpi 1.754346 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.754346 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.570013 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.570013 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 7235777 # number of integer regfile reads -system.cpu1.int_regfile_writes 3986410 # number of integer regfile writes -system.cpu1.fp_regfile_reads 21879 # number of floating regfile reads -system.cpu1.fp_regfile_writes 20613 # number of floating regfile writes -system.cpu1.misc_regfile_reads 262487 # number of misc regfile reads -system.cpu1.misc_regfile_writes 123180 # number of misc regfile writes -system.cpu1.icache.replacements 103776 # number of replacements -system.cpu1.icache.tagsinuse 452.422972 # Cycle average of tags in use -system.cpu1.icache.total_refs 841895 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 104287 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.072866 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1873827117000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 452.422972 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.883639 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.883639 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 841895 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 841895 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 841895 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 841895 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 841895 # number of overall hits -system.cpu1.icache.overall_hits::total 841895 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 109497 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 109497 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 109497 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 109497 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 109497 # number of overall misses -system.cpu1.icache.overall_misses::total 109497 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1632285999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1632285999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1632285999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1632285999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1632285999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1632285999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 951392 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 951392 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 951392 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 951392 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 951392 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 951392 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115091 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.115091 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115091 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.115091 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115091 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.115091 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14907.129867 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14907.129867 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14907.129867 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14907.129867 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 108999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 34238592 # The number of ROB reads +system.cpu1.rob.rob_writes 28901418 # The number of ROB writes +system.cpu1.timesIdled 230949 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1939000 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3778341690 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11789199 # Number of Instructions Simulated +system.cpu1.committedOps 11789199 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 11789199 # Number of Instructions Simulated +system.cpu1.cpi 1.926960 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.926960 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.518952 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.518952 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 16196586 # number of integer regfile reads +system.cpu1.int_regfile_writes 8796247 # number of integer regfile writes +system.cpu1.fp_regfile_reads 73611 # number of floating regfile reads +system.cpu1.fp_regfile_writes 74214 # number of floating regfile writes +system.cpu1.misc_regfile_reads 699711 # number of misc regfile reads +system.cpu1.misc_regfile_writes 299448 # number of misc regfile writes +system.cpu1.icache.replacements 315447 # number of replacements +system.cpu1.icache.tagsinuse 471.003081 # Cycle average of tags in use +system.cpu1.icache.total_refs 1635327 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 315959 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.175757 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 471.003081 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919928 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919928 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1635327 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1635327 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1635327 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1635327 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1635327 # number of overall hits +system.cpu1.icache.overall_hits::total 1635327 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 328187 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 328187 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 328187 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 328187 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 328187 # number of overall misses +system.cpu1.icache.overall_misses::total 328187 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323842998 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5323842998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5323842998 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5323842998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5323842998 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5323842998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1963514 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1963514 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1963514 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1963514 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1963514 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1963514 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167143 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.167143 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167143 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.167143 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167143 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.167143 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 16221.980145 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 16221.980145 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 228998 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7266.600000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6189.135135 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 39 # number of writebacks -system.cpu1.icache.writebacks::total 39 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5150 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 5150 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 5150 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 5150 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 5150 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 5150 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 104347 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 104347 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 104347 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 104347 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 104347 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 104347 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1240890499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1240890499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1240890499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1240890499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1240890499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1240890499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.109678 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.109678 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.109678 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11891.961427 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 38 # number of writebacks +system.cpu1.icache.writebacks::total 38 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12173 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12173 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12173 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12173 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12173 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12173 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316014 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316014 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316014 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316014 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316014 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316014 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183208998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183208998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183208998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4183208998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183208998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4183208998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.160943 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.160943 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.160943 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 49122 # number of replacements -system.cpu1.dcache.tagsinuse 427.490507 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1549420 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 49435 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 31.342571 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1873347092000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 427.490507 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.834942 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.834942 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1023689 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1023689 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 507974 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 507974 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 14665 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 14665 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 12767 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 12767 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1531663 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1531663 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1531663 # number of overall hits -system.cpu1.dcache.overall_hits::total 1531663 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 89035 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 89035 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 104470 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 104470 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1314 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1314 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 680 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 680 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 193505 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 193505 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 193505 # number of overall misses -system.cpu1.dcache.overall_misses::total 193505 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1323211000 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1112724 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1112724 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 612444 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 612444 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 15979 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 15979 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 13447 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 13447 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1725168 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1725168 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1725168 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1725168 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.080015 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.080015 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.170579 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.170579 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082233 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082233 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050569 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050569 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.112166 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.112166 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.112166 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.112166 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14861.694839 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14861.694839 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32101.084713 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32101.084713 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12240.106545 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12240.106545 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11758.088235 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11758.088235 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.954794 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.954794 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2022458 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2022458 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1251052 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1251052 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49972 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 49972 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3273510 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3273510 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3273510 # number of overall hits +system.cpu1.dcache.overall_hits::total 3273510 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 307183 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 307183 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 360837 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 360837 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8700 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8700 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5048 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5048 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 668020 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 668020 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 668020 # number of overall misses +system.cpu1.dcache.overall_misses::total 668020 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6372115000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6372115000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11323925707 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11323925707 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121529000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 121529000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68413000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 68413000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 17696040707 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 17696040707 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 17696040707 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 17696040707 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2329641 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2329641 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611889 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1611889 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58672 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 58672 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53649 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 53649 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3941530 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3941530 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3941530 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3941530 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131859 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.131859 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223860 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.223860 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148282 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148282 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094093 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094093 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169482 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.169482 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169482 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.169482 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 57515988 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 4983 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6825 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10447.420831 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8427.250989 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 27321 # number of writebacks -system.cpu1.dcache.writebacks::total 27321 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 51379 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 51379 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 87869 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 87869 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 246 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 246 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 139248 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 139248 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 139248 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 139248 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37656 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37656 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 16601 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 16601 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 674 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 674 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 54257 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 54257 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 54257 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 54257 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 431650500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 431650500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 497061484 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 497061484 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9472500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9472500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5965000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5965000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 928711984 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 928711984 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 928711984 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 928711984 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18616500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18616500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 318558500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 318558500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 337175000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 337175000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033841 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033841 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027106 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027106 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066838 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066838 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050123 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050123 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031450 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031450 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11462.993945 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11462.993945 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29941.659177 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29941.659177 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8869.382022 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8869.382022 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8850.148368 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8850.148368 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 112743 # number of writebacks +system.cpu1.dcache.writebacks::total 112743 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 196860 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 196860 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298722 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 298722 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1021 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1021 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 495582 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 495582 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 495582 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 495582 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110323 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 110323 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62115 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62115 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7679 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7679 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5048 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5048 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 172438 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 172438 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 172438 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 172438 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1760210564 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1760210564 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471458330 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471458330 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78242000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78242000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52885501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52885501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3231668894 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3231668894 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3231668894 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3231668894 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18623000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18623000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400648500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400648500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419271500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419271500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047356 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047356 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038536 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038536 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130880 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130880 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094093 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094093 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043749 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043749 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1589,161 +1589,171 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6349 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 201504 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72229 40.68% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.13% 40.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1919 1.08% 41.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 103147 58.10% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 177538 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70862 49.25% 49.25% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.16% 49.42% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1919 1.33% 50.75% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.75% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70856 49.25% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 143880 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1857798011000 97.96% 97.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91384000 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 387547000 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 3124500 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38114922000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896394988500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981074 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 167510 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 84509 58.04% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 145601 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862592276000 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96187500 0.01% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 394889000 0.02% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 155178500 0.01% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37157854000 1.96% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900396385000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.686942 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810418 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed -system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 228 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.681016 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810063 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed +system.cpu0.kern.syscall::6 28 13.33% 25.71% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 26.19% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.48% 26.67% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.29% 30.95% # number of syscalls executed +system.cpu0.kern.syscall::19 5 2.38% 33.33% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.90% 35.24% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.95% 36.19% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.90% 38.10% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.33% 41.43% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.95% 42.38% # number of syscalls executed +system.cpu0.kern.syscall::45 35 16.67% 59.05% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.90% 60.95% # number of syscalls executed +system.cpu0.kern.syscall::48 6 2.86% 63.81% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.29% 68.10% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 68.57% # number of syscalls executed +system.cpu0.kern.syscall::59 4 1.90% 70.48% # number of syscalls executed +system.cpu0.kern.syscall::71 32 15.24% 85.71% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.43% 87.14% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.29% 91.43% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 91.90% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.48% 92.38% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.33% 95.71% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.95% 96.67% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.95% 97.62% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.95% 98.57% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.48% 99.05% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 210 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3893 2.09% 2.15% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed -system.cpu0.kern.callpal::swpipl 170509 91.52% 93.70% # number of callpals executed -system.cpu0.kern.callpal::rdps 6338 3.40% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.11% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed -system.cpu0.kern.callpal::rti 4866 2.61% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 386 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 186310 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7415 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1346 # number of protection mode switches +system.cpu0.kern.callpal::wripir 439 0.29% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed +system.cpu0.kern.callpal::swpipl 138810 90.43% 92.75% # number of callpals executed +system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::rdusp 6 0.00% 96.90% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.90% # number of callpals executed +system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed +system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 153507 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1345 -system.cpu0.kern.mode_good::user 1346 +system.cpu0.kern.mode_good::kernel 1098 +system.cpu0.kern.mode_good::user 1098 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181389 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.164126 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.307157 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894436238500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1958742000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.281972 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1897963397000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1861803000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3894 # number of times the context was actually changed +system.cpu0.kern.swap_context 3077 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2266 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 36241 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9521 32.62% 32.62% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1918 6.57% 39.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.36% 39.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17647 60.46% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 29190 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9511 45.42% 45.42% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1918 9.16% 54.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.50% 55.08% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9407 44.92% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20940 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870201149000 98.64% 98.64% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 342845500 0.02% 98.65% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 41642500 0.00% 98.66% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25494039500 1.34% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896079676500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998950 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 74467 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 24565 38.36% 38.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 3.00% 41.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 37108 57.95% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 64035 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 23886 48.07% 48.07% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 23447 47.18% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 49695 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870827437000 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343518500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 182737500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29176221000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900529914000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.972359 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.533065 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.717369 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed -system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed -system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 98 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.631858 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.776060 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed +system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed +system.cpu1.kern.syscall::6 14 12.07% 25.86% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.17% 31.03% # number of syscalls executed +system.cpu1.kern.syscall::19 5 4.31% 35.34% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.72% 37.07% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.72% 38.79% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.72% 40.52% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.45% 43.97% # number of syscalls executed +system.cpu1.kern.syscall::45 19 16.38% 60.34% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.72% 62.07% # number of syscalls executed +system.cpu1.kern.syscall::48 4 3.45% 65.52% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.86% 66.38% # number of syscalls executed +system.cpu1.kern.syscall::59 3 2.59% 68.97% # number of syscalls executed +system.cpu1.kern.syscall::71 22 18.97% 87.93% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.03% 93.97% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.72% 95.69% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.72% 97.41% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.72% 99.14% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.86% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 116 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 334 1.11% 1.14% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.15% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.17% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24745 82.19% 83.36% # number of callpals executed -system.cpu1.kern.callpal::rdps 2407 7.99% 91.36% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.36% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.37% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed -system.cpu1.kern.callpal::rti 2422 8.04% 99.43% # number of callpals executed -system.cpu1.kern.callpal::callsys 129 0.43% 99.86% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.14% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 340 0.51% 0.51% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.51% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed +system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed +system.cpu1.kern.callpal::swpipl 57992 87.22% 90.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.11% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed +system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed +system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # number of callpals executed +system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 30107 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 710 # number of protection mode switches -system.cpu1.kern.mode_switch::user 392 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 420 -system.cpu1.kern.mode_good::user 392 -system.cpu1.kern.mode_good::idle 28 -system.cpu1.kern.mode_switch_good::kernel 0.591549 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 66490 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches +system.cpu1.kern.mode_switch::user 641 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 1003 +system.cpu1.kern.mode_good::user 641 +system.cpu1.kern.mode_good::idle 362 +system.cpu1.kern.mode_switch_good::kernel 0.473336 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.013672 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.266667 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1688462500 0.09% 0.09% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 719657500 0.04% 0.13% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893332404000 99.87% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 335 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 7877043500 0.41% 0.41% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 912149500 0.05% 0.46% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1891740713000 99.54% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1825 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 3ccfd349b..b1df0f096 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -517,7 +517,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -579,7 +579,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port[0] slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -636,7 +636,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 3b2f5c4a1..a30a37ba8 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:47:37 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 11:00:25 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858879782500 because m5_exit instruction encountered +Exiting @ tick 1865402113500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 90f62bf97..a9a5c3cb0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858880 # Number of seconds simulated -sim_ticks 1858879782500 # Number of ticks simulated -final_tick 1858879782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.865402 # Number of seconds simulated +sim_ticks 1865402113500 # Number of ticks simulated +final_tick 1865402113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196297 # Simulator instruction rate (inst/s) -host_op_rate 196297 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6876664069 # Simulator tick rate (ticks/s) -host_mem_usage 298988 # Number of bytes of host memory used -host_seconds 270.32 # Real time elapsed on the host -sim_insts 53062487 # Number of instructions simulated -sim_ops 53062487 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24884032 # Number of bytes read from this memory +host_inst_rate 131129 # Simulator instruction rate (inst/s) +host_op_rate 131129 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4607058697 # Simulator tick rate (ticks/s) +host_mem_usage 298956 # Number of bytes of host memory used +host_seconds 404.90 # Real time elapsed on the host +sim_insts 53094243 # Number of instructions simulated +sim_ops 53094243 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 967424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24877312 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28505408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory -system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388813 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28497024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516928 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516928 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15116 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388708 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445397 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 521329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13386574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1426821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15334724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 521329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 521329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 521329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13386574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1426821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19382788 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 338457 # number of replacements -system.l2c.tagsinuse 65351.732427 # Cycle average of tags in use -system.l2c.total_refs 2557615 # Total number of references to valid blocks. -system.l2c.sampled_refs 403631 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.336518 # Average number of references to valid blocks. -system.l2c.warmup_cycle 4816079000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53832.150010 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5352.172668 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6167.409749 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.821413 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.081668 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094107 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997188 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 1006386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 826813 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1833199 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 841169 # number of Writeback hits -system.l2c.Writeback_hits::total 841169 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185491 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185491 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 1006386 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1012304 # number of demand (read+write) hits -system.l2c.demand_hits::total 2018690 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 1006386 # number of overall hits -system.l2c.overall_hits::cpu.data 1012304 # number of overall hits -system.l2c.overall_hits::total 2018690 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 273879 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289023 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 27 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 115423 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115423 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 15144 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 389302 # number of demand (read+write) misses -system.l2c.demand_misses::total 404446 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 15144 # number of overall misses -system.l2c.overall_misses::cpu.data 389302 # number of overall misses -system.l2c.overall_misses::total 404446 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 792218000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14246173000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15038391000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 322000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 322000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6056487000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6056487000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 792218000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20302660000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21094878000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 792218000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20302660000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21094878000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 1021530 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1100692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2122222 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 841169 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 841169 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 42 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 42 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 300914 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300914 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1021530 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1401606 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2423136 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1021530 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1401606 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2423136 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014825 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.248824 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.136189 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.642857 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.642857 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383575 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383575 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014825 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.277754 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.166910 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014825 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.277754 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.166910 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52312.334918 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52016.302820 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52031.814077 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11925.925926 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 11925.925926 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52472.098282 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52472.098282 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52157.464779 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52157.464779 # average overall miss latency +system.physmem.num_reads::total 445266 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117452 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117452 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13336166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1421832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15276612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4029656 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4029656 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4029656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13336166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1421832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19306267 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 338323 # number of replacements +system.l2c.tagsinuse 65346.781313 # Cycle average of tags in use +system.l2c.total_refs 2566599 # Total number of references to valid blocks. +system.l2c.sampled_refs 403491 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.360982 # Average number of references to valid blocks. +system.l2c.warmup_cycle 4861120000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53937.288272 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5357.413768 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6052.079273 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.823018 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.081748 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092347 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997113 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1010692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 829338 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1840030 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 843192 # number of Writeback hits +system.l2c.Writeback_hits::total 843192 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 35 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 185767 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185767 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1010692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1015105 # number of demand (read+write) hits +system.l2c.demand_hits::total 2025797 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 1010692 # number of overall hits +system.l2c.overall_hits::cpu.data 1015105 # number of overall hits +system.l2c.overall_hits::total 2025797 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 15118 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 273845 # number of ReadReq misses +system.l2c.ReadReq_misses::total 288963 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 49 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 49 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 115352 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115352 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 15118 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 389197 # number of demand (read+write) misses +system.l2c.demand_misses::total 404315 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 15118 # number of overall misses +system.l2c.overall_misses::cpu.data 389197 # number of overall misses +system.l2c.overall_misses::total 404315 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 805739998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14260725000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15066464998 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 501500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 501500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6190534997 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6190534997 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 805739998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20451259997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21256999995 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 805739998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20451259997 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21256999995 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1025810 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1103183 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2128993 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 843192 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 843192 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 84 # 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average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.468800 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -219,14 +219,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.268378 # Cycle average of tags in use +system.iocache.tagsinuse 1.294799 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338896000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.268378 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079274 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079274 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1711277767000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.294799 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.080925 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.080925 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -235,14 +235,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 19937998 # 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number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7662570804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7662570804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7662570804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -259,19 +259,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.582355 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137704.582355 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137611.475231 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137611.475231 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64649068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183911.672266 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183911.672266 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183644.596860 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183644.596860 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7656000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7143 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6171.159603 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1071.818564 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -285,14 +285,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561047996 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3561047996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571989994 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571989994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571989994 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571989994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5481043992 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5481043992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5492719992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5492719992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5492719992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5492719992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -301,14 +301,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85701.001059 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85701.001059 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131908.066808 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131908.066808 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -326,22 +326,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9957395 # DTB read hits -system.cpu.dtb.read_misses 44300 # DTB read misses -system.cpu.dtb.read_acv 564 # DTB read access violations -system.cpu.dtb.read_accesses 948872 # DTB read accesses -system.cpu.dtb.write_hits 6634412 # DTB write hits -system.cpu.dtb.write_misses 10394 # DTB write misses -system.cpu.dtb.write_acv 384 # DTB write access violations -system.cpu.dtb.write_accesses 338929 # DTB write accesses -system.cpu.dtb.data_hits 16591807 # DTB hits -system.cpu.dtb.data_misses 54694 # DTB misses -system.cpu.dtb.data_acv 948 # DTB access violations -system.cpu.dtb.data_accesses 1287801 # DTB accesses -system.cpu.itb.fetch_hits 1332166 # ITB hits -system.cpu.itb.fetch_misses 40283 # ITB misses -system.cpu.itb.fetch_acv 1114 # ITB acv -system.cpu.itb.fetch_accesses 1372449 # ITB accesses +system.cpu.dtb.read_hits 9972402 # DTB read hits +system.cpu.dtb.read_misses 43929 # DTB read misses +system.cpu.dtb.read_acv 494 # DTB read access violations +system.cpu.dtb.read_accesses 957886 # DTB read accesses +system.cpu.dtb.write_hits 6649938 # DTB write hits +system.cpu.dtb.write_misses 10071 # DTB write misses +system.cpu.dtb.write_acv 391 # DTB write access violations +system.cpu.dtb.write_accesses 340693 # DTB write accesses +system.cpu.dtb.data_hits 16622340 # DTB hits +system.cpu.dtb.data_misses 54000 # DTB misses +system.cpu.dtb.data_acv 885 # DTB access violations +system.cpu.dtb.data_accesses 1298579 # DTB accesses +system.cpu.itb.fetch_hits 1343669 # ITB hits +system.cpu.itb.fetch_misses 37345 # ITB misses +system.cpu.itb.fetch_acv 1146 # ITB acv +system.cpu.itb.fetch_accesses 1381014 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -354,279 +354,279 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 114963877 # number of cpu cycles simulated +system.cpu.numCycles 122571263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 13985774 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11671873 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 444413 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10112209 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5892039 # Number of BTB hits +system.cpu.BPredUnit.lookups 14075987 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11741614 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 452517 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10126525 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5926302 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 933191 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 42453 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29251616 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71181997 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13985774 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6825230 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13396576 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2069716 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36268090 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 34293 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 258776 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 311439 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 136 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8761444 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288106 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80878220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.880113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220739 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 942334 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45003 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31564050 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71567580 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14075987 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6868636 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13486844 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2151091 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 41804632 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33708 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 276041 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 314295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 187 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8859322 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 305645 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 88896899 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.805063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.137281 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67481644 83.44% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 875531 1.08% 84.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1743396 2.16% 86.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 848384 1.05% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2751006 3.40% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 598052 0.74% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 674963 0.83% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011492 1.25% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4893752 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75410055 84.83% 84.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 885656 1.00% 85.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1762066 1.98% 87.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 856601 0.96% 88.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772547 3.12% 91.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 605003 0.68% 92.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 676052 0.76% 93.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1014878 1.14% 94.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4914041 5.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80878220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121654 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.619168 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30302953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36036206 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12267887 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 956730 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1314443 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 612620 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43298 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69919175 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129721 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1314443 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31429322 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12715444 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19630106 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11479703 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4309200 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66239771 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6813 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505927 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1528052 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44253229 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80320067 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79838854 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 481213 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38235996 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6017225 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1699905 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 247549 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12108783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10535735 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6944708 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1299665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 826518 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58678192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2085341 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57178934 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114167 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7323387 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3670404 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1417353 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80878220 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.706976 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.364710 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 88896899 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114839 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.583885 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32604567 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 41610698 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12250426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1057078 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1374129 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 617310 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43428 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70293890 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 133239 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1374129 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33752767 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16324711 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21058224 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11548980 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4838086 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66572257 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7187 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 753146 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1801877 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44498273 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80714962 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80226097 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 488865 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38261328 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6236937 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1703640 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251709 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12757763 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10570492 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6981683 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1316603 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 922104 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58981346 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2097651 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57326676 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120953 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7579711 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3887654 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1429592 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 88896899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.644867 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.291957 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55943146 69.17% 69.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11029219 13.64% 82.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5183069 6.41% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3467547 4.29% 93.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2613614 3.23% 96.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1475312 1.82% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 724581 0.90% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331422 0.41% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 110310 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 62967728 70.83% 70.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 12048856 13.55% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5390899 6.06% 90.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3449544 3.88% 94.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2613461 2.94% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1329807 1.50% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 686975 0.77% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 354371 0.40% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 55258 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80878220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 88896899 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90406 11.39% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 375907 47.36% 58.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 327352 41.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 75491 10.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 363771 48.19% 58.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315594 41.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39009688 68.22% 68.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61923 0.11% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10404436 18.20% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6713568 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952795 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39127581 68.25% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61956 0.11% 68.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10418296 18.17% 86.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6729507 11.74% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952802 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57178934 # Type of FU issued -system.cpu.iq.rate 0.497364 # Inst issue rate -system.cpu.iq.fu_busy_cnt 793665 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013880 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195448703 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67761433 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55894957 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 695216 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 339032 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327938 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57602239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363079 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 589978 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57326676 # Type of FU issued +system.cpu.iq.rate 0.467701 # Inst issue rate +system.cpu.iq.fu_busy_cnt 754856 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013168 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 203729346 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68333375 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56036726 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 696713 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 339202 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327718 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57709702 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 364539 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 594776 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1427299 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3440 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13878 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 554882 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1456655 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2870 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14252 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 588832 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 151980 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18348 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 104302 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1314443 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8887747 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 615033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64324837 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 661005 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10535735 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6944708 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1835122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 481853 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16088 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13878 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 240769 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 420658 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 661427 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56655096 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10030988 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 523837 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1374129 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11393417 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 869281 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64652535 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684492 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10570492 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6981683 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1845589 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 621506 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12714 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14252 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 241539 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 423865 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 665404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56791406 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10044983 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 535269 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3561304 # number of nop insts executed -system.cpu.iew.exec_refs 16691010 # number of memory reference insts executed -system.cpu.iew.exec_branches 8986521 # Number of branches executed -system.cpu.iew.exec_stores 6660022 # Number of stores executed -system.cpu.iew.exec_rate 0.492808 # Inst execution rate -system.cpu.iew.wb_sent 56341255 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56222895 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27828941 # num instructions producing a value -system.cpu.iew.wb_consumers 37695611 # num instructions consuming a value +system.cpu.iew.exec_nop 3573538 # number of nop insts executed +system.cpu.iew.exec_refs 16720258 # number of memory reference insts executed +system.cpu.iew.exec_branches 9005988 # Number of branches executed +system.cpu.iew.exec_stores 6675275 # Number of stores executed +system.cpu.iew.exec_rate 0.463334 # Inst execution rate +system.cpu.iew.wb_sent 56476627 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56364444 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27797872 # num instructions producing a value +system.cpu.iew.wb_consumers 37663953 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.489048 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738254 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459850 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738050 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56255888 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56255888 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 7955379 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 613263 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79563777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.707054 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.631051 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56288834 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56288834 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 8251602 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 668059 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 621198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 87522770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.643134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.558246 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58612311 73.67% 73.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8734565 10.98% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4655391 5.85% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2574186 3.24% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1496332 1.88% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 659939 0.83% 96.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 486345 0.61% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 472774 0.59% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1871934 2.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66254825 75.70% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8962066 10.24% 85.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4828588 5.52% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2603942 2.98% 94.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1449491 1.66% 96.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 603705 0.69% 96.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 515511 0.59% 97.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 488925 0.56% 97.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1815717 2.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79563777 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56255888 # Number of instructions committed -system.cpu.commit.committedOps 56255888 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 87522770 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56288834 # Number of instructions committed +system.cpu.commit.committedOps 56288834 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15498262 # Number of memory references committed -system.cpu.commit.loads 9108436 # Number of loads committed -system.cpu.commit.membars 227920 # Number of memory barriers committed -system.cpu.commit.branches 8459857 # Number of branches committed +system.cpu.commit.refs 15506688 # Number of memory references committed +system.cpu.commit.loads 9113837 # Number of loads committed +system.cpu.commit.membars 227975 # Number of memory barriers committed +system.cpu.commit.branches 8463674 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52095164 # Number of committed integer instructions. -system.cpu.commit.function_calls 744157 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1871934 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52126817 # Number of committed integer instructions. +system.cpu.commit.function_calls 744625 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1815717 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141652037 # The number of ROB reads -system.cpu.rob.rob_writes 129738562 # The number of ROB writes -system.cpu.timesIdled 1269768 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34085657 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3602789251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53062487 # Number of Instructions Simulated -system.cpu.committedOps 53062487 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53062487 # Number of Instructions Simulated -system.cpu.cpi 2.166575 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.166575 # CPI: Total CPI of All Threads -system.cpu.ipc 0.461558 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.461558 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74266984 # number of integer regfile reads -system.cpu.int_regfile_writes 40553865 # number of integer regfile writes -system.cpu.fp_regfile_reads 166054 # number of floating regfile reads -system.cpu.fp_regfile_writes 167450 # number of floating regfile writes -system.cpu.misc_regfile_reads 1999349 # number of misc regfile reads -system.cpu.misc_regfile_writes 950331 # number of misc regfile writes +system.cpu.rob.rob_reads 149996318 # The number of ROB reads +system.cpu.rob.rob_writes 130455868 # The number of ROB writes +system.cpu.timesIdled 1387986 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33674364 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3608226532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53094243 # Number of Instructions Simulated +system.cpu.committedOps 53094243 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53094243 # Number of Instructions Simulated +system.cpu.cpi 2.308560 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.308560 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433170 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433170 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74446052 # number of integer regfile reads +system.cpu.int_regfile_writes 40661007 # number of integer regfile writes +system.cpu.fp_regfile_reads 166346 # number of floating regfile reads +system.cpu.fp_regfile_writes 166939 # number of floating regfile writes +system.cpu.misc_regfile_reads 1998850 # number of misc regfile reads +system.cpu.misc_regfile_writes 950370 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -658,247 +658,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1020915 # number of replacements -system.cpu.icache.tagsinuse 509.977219 # Cycle average of tags in use -system.cpu.icache.total_refs 7681837 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1021424 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.520713 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23212946000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.977219 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996049 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996049 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7681838 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7681838 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7681838 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7681838 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7681838 # number of overall hits -system.cpu.icache.overall_hits::total 7681838 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079605 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079605 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079605 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079605 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079605 # number of overall misses -system.cpu.icache.overall_misses::total 1079605 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16072965497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16072965497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16072965497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16072965497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16072965497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16072965497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8761443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8761443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8761443 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8761443 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8761443 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8761443 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123222 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123222 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123222 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123222 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123222 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123222 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14887.820543 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14887.820543 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14887.820543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14887.820543 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1368497 # number of cycles access was blocked +system.cpu.icache.replacements 1025209 # number of replacements +system.cpu.icache.tagsinuse 509.960172 # Cycle average of tags in use +system.cpu.icache.total_refs 7772148 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1025718 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.577276 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23722278000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.960172 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996016 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7772149 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7772149 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7772149 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7772149 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7772149 # number of overall hits +system.cpu.icache.overall_hits::total 7772149 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1087170 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1087170 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1087170 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1087170 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1087170 # number of overall misses +system.cpu.icache.overall_misses::total 1087170 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528418489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17528418489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17528418489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17528418489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17528418489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17528418489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8859319 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8859319 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8859319 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8859319 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8859319 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8859319 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122715 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122715 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122715 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122715 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122715 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122715 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16122.978457 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16122.978457 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16122.978457 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16122.978457 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1581994 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9845.302158 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8071.397959 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1021632 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1021632 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12173342997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12173342997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12173342997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12173342997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12173342997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12173342997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116605 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116605 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116605 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11915.585061 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11915.585061 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 238 # number of writebacks +system.cpu.icache.writebacks::total 238 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61204 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61204 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 61204 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 61204 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 61204 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 61204 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025966 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1025966 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1025966 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1025966 # 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mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115806 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115806 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13168.573807 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13168.573807 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13168.573807 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19693000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995922 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7290659 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7290659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4213930 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4213930 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 190794 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 190794 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 220142 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220142 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319631 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319631 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000018 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000018 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.248694 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.248694 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.248694 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.248694 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26700.025689 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26700.025689 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38101.573374 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38101.573374 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18449.502498 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18449.502498 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14125 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14125 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32608.776087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32608.776087 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 732928021 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72145 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8104.740824 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10159.096556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840933 # number of writebacks -system.cpu.dcache.writebacks::total 840933 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 715397 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 715397 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640618 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1640618 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5145 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5145 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2356015 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2356015 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2356015 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048740 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048740 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083836 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083836 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090783 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090783 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22203.183350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22203.183350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28252.273818 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28252.273818 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11516.146124 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11516.146124 # average LoadLockedReq mshr miss latency +system.cpu.dcache.writebacks::writebacks 842954 # number of writebacks +system.cpu.dcache.writebacks::total 842954 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 743747 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 743747 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667534 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1667534 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5230 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5230 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2411281 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2411281 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2411281 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2411281 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085838 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1085838 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300600 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300600 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386438 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386438 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386438 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386438 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28239740000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28239740000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9650792448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9650792448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 273508500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 273508500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37890532448 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37890532448 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37890532448 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37890532448 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 905949500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 905949500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1225663998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1225663998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2131613498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2131613498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084945 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084945 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000018 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000018 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090791 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26007.323376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26007.323376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32105.097964 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32105.097964 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15038.681476 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15038.681476 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -907,28 +907,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211701 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74930 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105874 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182929 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73563 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73566 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149254 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820291216500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94615000 0.01% 97.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 380636500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38112442500 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858878910500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211694 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74899 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 247 0.14% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1887 1.03% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105884 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182917 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73532 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 247 0.17% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149203 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1825754390000 97.87% 97.87% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 99081000 0.01% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 381309500 0.02% 97.90% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39166410000 2.10% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865401190500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694845 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815912 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694505 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815687 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -967,29 +967,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175590 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6787 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175564 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192549 # number of callpals executed +system.cpu.kern.callpal::total 192535 # number of callpals executed system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_switch::user 1736 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2110 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320403 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.389547 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29004913500 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2663331000 0.14% 1.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827210658000 98.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080569 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.388940 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29632954500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2782152500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832986075500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |