diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 5632 insertions, 5649 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index f1835fc87..e646f5b40 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.909061 # Number of seconds simulated -sim_ticks 1909061460000 # Number of ticks simulated -final_tick 1909061460000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.889223 # Number of seconds simulated +sim_ticks 1889223246000 # Number of ticks simulated +final_tick 1889223246000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24403 # Simulator instruction rate (inst/s) -host_op_rate 24403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 829686396 # Simulator tick rate (ticks/s) -host_mem_usage 385840 # Number of bytes of host memory used -host_seconds 2300.94 # Real time elapsed on the host -sim_insts 56149847 # Number of instructions simulated -sim_ops 56149847 # Number of ops (including micro ops) simulated +host_inst_rate 22780 # Simulator instruction rate (inst/s) +host_op_rate 22780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 766551699 # Simulator tick rate (ticks/s) +host_mem_usage 396616 # Number of bytes of host memory used +host_seconds 2464.57 # Real time elapsed on the host +sim_insts 56141873 # Number of instructions simulated +sim_ops 56141873 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1046656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24857664 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859008 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25905280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7563328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7563328 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16354 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388401 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25907520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory +system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388422 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404770 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118177 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118177 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 548257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13020882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13569642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3961804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3961804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3961804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13020882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17531446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404770 # Number of read requests accepted -system.physmem.writeReqs 118177 # Number of write requests accepted -system.physmem.readBursts 404770 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118177 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25897600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25905280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7563328 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 404805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 554488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13158322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13713318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 554488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 554488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4005100 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4005100 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4005100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 554488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13158322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17718418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404805 # Number of read requests accepted +system.physmem.writeReqs 118227 # Number of write requests accepted +system.physmem.readBursts 404805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 7565120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25907520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25467 # Per bank write bursts -system.physmem.perBankRdBursts::1 25712 # Per bank write bursts -system.physmem.perBankRdBursts::2 25810 # Per bank write bursts -system.physmem.perBankRdBursts::3 25757 # Per bank write bursts -system.physmem.perBankRdBursts::4 25010 # Per bank write bursts -system.physmem.perBankRdBursts::5 25117 # Per bank write bursts -system.physmem.perBankRdBursts::6 24705 # Per bank write bursts -system.physmem.perBankRdBursts::7 24573 # Per bank write bursts -system.physmem.perBankRdBursts::8 25203 # Per bank write bursts -system.physmem.perBankRdBursts::9 25292 # Per bank write bursts -system.physmem.perBankRdBursts::10 25386 # Per bank write bursts -system.physmem.perBankRdBursts::11 25018 # Per bank write bursts -system.physmem.perBankRdBursts::12 24535 # Per bank write bursts -system.physmem.perBankRdBursts::13 25541 # Per bank write bursts -system.physmem.perBankRdBursts::14 25794 # Per bank write bursts -system.physmem.perBankRdBursts::15 25730 # Per bank write bursts -system.physmem.perBankWrBursts::0 7820 # Per bank write bursts +system.physmem.perBankRdBursts::0 25470 # Per bank write bursts +system.physmem.perBankRdBursts::1 25713 # Per bank write bursts +system.physmem.perBankRdBursts::2 25812 # Per bank write bursts +system.physmem.perBankRdBursts::3 25774 # Per bank write bursts +system.physmem.perBankRdBursts::4 25230 # Per bank write bursts +system.physmem.perBankRdBursts::5 24950 # Per bank write bursts +system.physmem.perBankRdBursts::6 24793 # Per bank write bursts +system.physmem.perBankRdBursts::7 24569 # Per bank write bursts +system.physmem.perBankRdBursts::8 25113 # Per bank write bursts +system.physmem.perBankRdBursts::9 25266 # Per bank write bursts +system.physmem.perBankRdBursts::10 25525 # Per bank write bursts +system.physmem.perBankRdBursts::11 24857 # Per bank write bursts +system.physmem.perBankRdBursts::12 24533 # Per bank write bursts +system.physmem.perBankRdBursts::13 25560 # Per bank write bursts +system.physmem.perBankRdBursts::14 25804 # Per bank write bursts +system.physmem.perBankRdBursts::15 25731 # Per bank write bursts +system.physmem.perBankWrBursts::0 7815 # Per bank write bursts system.physmem.perBankWrBursts::1 7678 # Per bank write bursts -system.physmem.perBankWrBursts::2 8070 # Per bank write bursts -system.physmem.perBankWrBursts::3 7721 # Per bank write bursts -system.physmem.perBankWrBursts::4 7116 # Per bank write bursts -system.physmem.perBankWrBursts::5 7111 # Per bank write bursts -system.physmem.perBankWrBursts::6 6703 # Per bank write bursts +system.physmem.perBankWrBursts::2 8068 # Per bank write bursts +system.physmem.perBankWrBursts::3 7736 # Per bank write bursts +system.physmem.perBankWrBursts::4 7326 # Per bank write bursts +system.physmem.perBankWrBursts::5 6953 # Per bank write bursts +system.physmem.perBankWrBursts::6 6780 # Per bank write bursts system.physmem.perBankWrBursts::7 6420 # Per bank write bursts -system.physmem.perBankWrBursts::8 7317 # Per bank write bursts -system.physmem.perBankWrBursts::9 6903 # Per bank write bursts -system.physmem.perBankWrBursts::10 7274 # Per bank write bursts -system.physmem.perBankWrBursts::11 7007 # Per bank write bursts -system.physmem.perBankWrBursts::12 7092 # Per bank write bursts -system.physmem.perBankWrBursts::13 7990 # Per bank write bursts -system.physmem.perBankWrBursts::14 7984 # Per bank write bursts -system.physmem.perBankWrBursts::15 7946 # Per bank write bursts +system.physmem.perBankWrBursts::8 7238 # Per bank write bursts +system.physmem.perBankWrBursts::9 6883 # Per bank write bursts +system.physmem.perBankWrBursts::10 7397 # Per bank write bursts +system.physmem.perBankWrBursts::11 6875 # Per bank write bursts +system.physmem.perBankWrBursts::12 7088 # Per bank write bursts +system.physmem.perBankWrBursts::13 8006 # Per bank write bursts +system.physmem.perBankWrBursts::14 7993 # Per bank write bursts +system.physmem.perBankWrBursts::15 7949 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 1909052547000 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 1889214280000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404770 # Read request sizes (log2) +system.physmem.readPktSize::6 404805 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118177 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118227 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,191 +149,193 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 518.162823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 316.799935 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 407.231768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14977 23.19% 23.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11234 17.40% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4851 7.51% 48.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3268 5.06% 53.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2473 3.83% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2033 3.15% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4174 6.46% 66.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1362 2.11% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20201 31.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64573 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.433321 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2890.025475 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5291 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 524.988548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.641335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 414.335221 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14725 23.10% 23.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10901 17.10% 40.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5357 8.40% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3110 4.88% 53.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2601 4.08% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1701 2.67% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1560 2.45% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1439 2.26% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22352 35.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63746 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.386372 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2900.765356 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5295 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.318096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.102648 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.930772 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4682 88.44% 88.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.62% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 23 0.43% 89.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 33 0.62% 90.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 222 4.19% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 11 0.21% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.21% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 35 0.66% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 195 3.68% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 6 0.11% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.08% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.09% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 9 0.17% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads -system.physmem.totQLat 2639973000 # Total ticks spent queuing -system.physmem.totMemAccLat 10227160500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6524.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5298 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.311250 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.880356 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.145944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4698 88.67% 88.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.62% 89.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 235 4.44% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 22 0.42% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 12 0.23% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 14 0.26% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 4 0.08% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 30 0.57% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 15 0.28% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 179 3.38% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.02% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.08% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 12 0.23% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 2 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 8 0.15% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5298 # Writes before turning the bus around for reads +system.physmem.totQLat 2164522000 # Total ticks spent queuing +system.physmem.totMemAccLat 9752647000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5348.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25274.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.96 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.57 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24098.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.71 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing -system.physmem.readRowHits 362738 # Number of row buffer hits during reads -system.physmem.writeRowHits 95491 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3650566.02 # Average gap between requests -system.physmem.pageHitRate 87.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 238623840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130201500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1576777800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 379980720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124690266480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68013230490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1085773099500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1280802180330 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.908515 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1806022540250 # Time in different power states -system.physmem_0.memoryStateTime::REF 63747580000 # Time in different power states +system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing +system.physmem.readRowHits 363251 # Number of row buffer hits during reads +system.physmem.writeRowHits 95908 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.12 # Row buffer hit rate for writes +system.physmem.avgGap 3612043.39 # Average gap between requests +system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 234556560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127982250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578025800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 380868480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60772181625 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1080221277750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1266709348065 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.494357 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1796832063750 # Time in different power states +system.physmem_0.memoryStateTime::REF 63085100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39286273500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29299865000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249548040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136162125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579492200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385644240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124690266480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68685352830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1085183526750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1280909992665 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.964984 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1805042162250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63747580000 # Time in different power states +system.physmem_1.actEnergy 247363200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134970000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1578634200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385099920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61856765370 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1079269896750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1266867185040 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.577899 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1795248089750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63085100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 40266665250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30883852750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15258422 # Number of BP lookups -system.cpu.branchPred.condPredicted 13121569 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 520615 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12105776 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4568162 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15253451 # Number of BP lookups +system.cpu.branchPred.condPredicted 13119801 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 515637 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12113296 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4570787 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.735392 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 863536 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33630 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6539212 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 544524 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5994688 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 219095 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.733636 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 859438 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30658 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6570706 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 545483 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 6025223 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 218035 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9320175 # DTB read hits -system.cpu.dtb.read_misses 17427 # DTB read misses +system.cpu.dtb.read_hits 9316925 # DTB read hits +system.cpu.dtb.read_misses 17695 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764388 # DTB read accesses -system.cpu.dtb.write_hits 6394455 # DTB write hits -system.cpu.dtb.write_misses 2545 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298887 # DTB write accesses -system.cpu.dtb.data_hits 15714630 # DTB hits -system.cpu.dtb.data_misses 19972 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1063275 # DTB accesses -system.cpu.itb.fetch_hits 4019631 # ITB hits -system.cpu.itb.fetch_misses 6355 # ITB misses -system.cpu.itb.fetch_acv 661 # ITB acv -system.cpu.itb.fetch_accesses 4025986 # ITB accesses +system.cpu.dtb.read_accesses 764827 # DTB read accesses +system.cpu.dtb.write_hits 6393212 # DTB write hits +system.cpu.dtb.write_misses 2442 # DTB write misses +system.cpu.dtb.write_acv 158 # DTB write access violations +system.cpu.dtb.write_accesses 298820 # DTB write accesses +system.cpu.dtb.data_hits 15710137 # DTB hits +system.cpu.dtb.data_misses 20137 # DTB misses +system.cpu.dtb.data_acv 369 # DTB access violations +system.cpu.dtb.data_accesses 1063647 # DTB accesses +system.cpu.itb.fetch_hits 4018824 # ITB hits +system.cpu.itb.fetch_misses 6310 # ITB misses +system.cpu.itb.fetch_acv 701 # ITB acv +system.cpu.itb.fetch_accesses 4025134 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -346,85 +348,84 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12756 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6378 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281603673.878959 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439873554.784215 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6377 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12752 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281746974.905897 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439847984.325030 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 19000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6378 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 112993228000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796068232000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 226008061 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 92804534000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796418712000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 185630526 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56149847 # Number of instructions committed -system.cpu.committedOps 56149847 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2969857 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6378 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3592114868 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 4.025088 # CPI: cycles per instruction -system.cpu.ipc 0.248442 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199355 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36201883 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60840 0.11% 70.28% # Class of committed instruction +system.cpu.committedInsts 56141873 # Number of instructions committed +system.cpu.committedOps 56141873 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2958149 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3592815966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.306454 # CPI: cycles per instruction +system.cpu.ipc 0.302439 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199005 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36197195 64.47% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60822 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::MemRead 9320961 16.60% 86.95% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6373595 11.35% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951498 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::MemRead 9319321 16.60% 86.95% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6372729 11.35% 98.31% # Class of committed instruction +system.cpu.op_class_0::IprAccess 951086 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56149847 # Class of committed instruction +system.cpu.op_class_0::total 56141873 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74821 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1907 1.04% 42.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105943 57.96% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182802 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73454 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211498 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74792 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1903 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105883 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182709 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73425 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1907 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73454 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148946 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1839859866500 96.38% 96.38% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 85941500 0.00% 96.38% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 711439500 0.04% 96.42% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 68403193000 3.58% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1909060440500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981730 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1903 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73425 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148884 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1835945903000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 85568000 0.00% 97.18% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 710063500 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 52480708000 2.78% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1889222242500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693335 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814794 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693454 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814870 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -463,513 +464,514 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175631 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6810 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175546 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5132 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5128 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192526 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5877 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 192434 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2091 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1905 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324315 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324200 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392625 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 38921683000 2.04% 2.04% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4598347000 0.24% 2.28% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1865540400500 97.72% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080344 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36856948000 1.95% 1.95% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4192339500 0.22% 2.17% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1848172945000 97.83% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85327235 # Number of cycles that the object actually ticked -system.cpu.idleCycles 140680826 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394976 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.976740 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13944378 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395488 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.992474 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 124106500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.976740 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy +system.cpu.tickCycles 85233988 # Number of cycles that the object actually ticked +system.cpu.idleCycles 100396538 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394263 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980931 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13942036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394775 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.995903 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 94238500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980931 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63924438 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63924438 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7983946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7983946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5577839 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5577839 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183518 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183518 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199043 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199043 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13561785 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13561785 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13561785 # number of overall hits -system.cpu.dcache.overall_hits::total 13561785 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096703 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 574639 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 574639 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16549 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16549 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1671342 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1671342 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1671342 # number of overall misses -system.cpu.dcache.overall_misses::total 1671342 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45383174000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45383174000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964439500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33964439500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 226601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 226601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 79347613500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 79347613500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 79347613500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 79347613500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9080649 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9080649 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152478 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152478 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200067 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200067 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199043 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199043 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15233127 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15233127 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15233127 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15233127 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120774 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120774 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093400 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093400 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082717 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082717 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109718 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109718 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109718 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109718 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41381.462438 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41381.462438 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59105.698534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59105.698534 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13692.760892 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13692.760892 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47475.390136 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47475.390136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47475.390136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47475.390136 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63909041 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63909041 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7981560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7981560 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5577988 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5577988 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183448 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183448 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199007 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199007 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13559548 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13559548 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13559548 # number of overall hits +system.cpu.dcache.overall_hits::total 13559548 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096304 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096304 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573678 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16581 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16581 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1669982 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1669982 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1669982 # number of overall misses +system.cpu.dcache.overall_misses::total 1669982 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31558344500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31558344500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22538815500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22538815500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222577500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222577500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54097160000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54097160000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54097160000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54097160000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9077864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9077864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151666 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151666 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199007 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199007 # 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miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109654 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109654 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109654 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28786.125472 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28786.125472 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39288.268855 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39288.268855 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.647548 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13423.647548 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32393.858137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32393.858137 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 838068 # number of writebacks -system.cpu.dcache.writebacks::total 838068 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21939 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21939 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270415 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270415 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837697 # number of writebacks +system.cpu.dcache.writebacks::total 837697 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269759 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269759 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 292354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 292354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 292354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 292354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304224 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304224 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16546 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16546 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378988 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378988 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378988 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378988 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291740 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291740 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291740 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291740 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074323 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074323 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303919 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 303919 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16578 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16578 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378242 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378242 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378242 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9625 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9625 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43721360500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43721360500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17277660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17277660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209790000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209790000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60999021000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 60999021000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60999021000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 60999021000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1527294000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1527294000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1527294000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1527294000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118358 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118358 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049447 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049447 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082702 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082702 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090526 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40679.963694 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40679.963694 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56792.562388 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56792.562388 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12679.197389 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12679.197389 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44234.627858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44234.627858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44234.627858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44234.627858 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220388.744589 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220388.744589 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92255.753549 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92255.753549 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1477492 # number of replacements -system.cpu.icache.tags.tagsinuse 508.111413 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19219698 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1478003 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.003829 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 50147606500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.111413 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992405 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992405 # Average percentage of cache occupancy +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30011433500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30011433500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11481403000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11481403000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205832000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205832000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41492836500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41492836500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41492836500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41492836500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534160500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534160500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534160500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534160500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118345 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118345 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049404 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049404 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082878 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082878 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090498 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090498 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27935.205241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27935.205241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37777.838832 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37777.838832 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12415.972976 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12415.972976 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.581530 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.581530 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92692.918857 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92692.918857 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1476241 # number of replacements +system.cpu.icache.tags.tagsinuse 509.437018 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19208652 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1476752 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.007365 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 33938325500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.437018 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994994 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994994 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1170547500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17243377000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17243377000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170547500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25130391500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26300939000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170547500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25130391500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26300939000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383740 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383740 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011084 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249543 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249543 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141109 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141109 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39900 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39900 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67624.234759 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67624.234759 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71510.018938 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71510.018938 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63343.767334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63343.767334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87457.857531 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87457.857531 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5742250 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2870700 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1972 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2576516 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 956247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1477492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 820003 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2574859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 914412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1476241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819473 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1478177 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8653101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189159296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143002060 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332161356 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 423210 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3313265 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001022 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031947 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 303930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 303930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1476926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4430038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217161 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8647199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188999168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142932652 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 331931820 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340234 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923264 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3228320 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000974 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031197 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3309880 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3385 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3225175 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3145 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3313265 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5201739500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3228320 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5198149000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2217424681 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2215530716 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105003991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2103938977 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -983,12 +985,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51177 # Transaction distribution -system.iobus.trans_dist::WriteResp 51177 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5106 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51173 # Transaction distribution +system.iobus.trans_dist::WriteResp 51173 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5098 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -997,11 +999,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20424 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116552 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1010,50 +1012,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44364 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44332 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705972 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5417500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705940 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5405000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 799000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 800000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 182000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15625500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14495500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6004000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5973000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215719668 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216181312 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23485000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23481000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.297488 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.301361 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1750571994000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.297488 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081093 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081093 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1731952426000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.301361 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081335 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081335 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1062,14 +1064,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244162285 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5244162285 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5266079668 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5266079668 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5266079668 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5266079668 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21934383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21934383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4859195929 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4859195929 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4881130312 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4881130312 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4881130312 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4881130312 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1086,19 +1088,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126207.217101 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126207.217101 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126209.219125 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126209.219125 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126209.219125 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126209.219125 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126788.341040 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126788.341040 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116942.528133 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116942.528133 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116983.350797 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116983.350797 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1110,14 +1112,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3164763984 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3164763984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3178031367 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3178031367 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3178031367 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3178031367 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13284383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13284383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2779181979 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2779181979 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2792466362 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2792466362 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2792466362 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2792466362 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1126,69 +1128,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76163.938776 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76163.938776 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76166.120240 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76166.120240 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76166.120240 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76166.120240 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76788.341040 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76788.341040 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66884.433457 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66884.433457 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827436 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381422 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295632 # Transaction distribution -system.membus.trans_dist::WriteReq 9625 # Transaction distribution -system.membus.trans_dist::WriteResp 9625 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118177 # Transaction distribution -system.membus.trans_dist::CleanEvict 262256 # Transaction distribution -system.membus.trans_dist::UpgradeReq 167 # Transaction distribution +system.membus.trans_dist::ReadResp 295668 # Transaction distribution +system.membus.trans_dist::WriteReq 9621 # Transaction distribution +system.membus.trans_dist::WriteResp 9621 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution +system.membus.trans_dist::CleanEvict 262241 # Transaction distribution +system.membus.trans_dist::UpgradeReq 137 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116499 # Transaction distribution -system.membus.trans_dist::ReadExResp 116499 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288726 # Transaction distribution -system.membus.trans_dist::BadAddressError 24 # Transaction distribution +system.membus.trans_dist::ReadExReq 116498 # Transaction distribution +system.membus.trans_dist::ReadExResp 116498 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288761 # Transaction distribution +system.membus.trans_dist::BadAddressError 23 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148698 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181921 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265281 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1265346 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44332 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860652 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33512972 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33518380 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 843934 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 463499 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001458 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038162 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843934 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462823 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 676 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843934 # Request fanout histogram -system.membus.reqLayer0.occupancy 30445500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463499 # Request fanout histogram +system.membus.reqLayer0.occupancy 29272500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319244966 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319341290 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 31000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2159924750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160301000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1220,28 +1228,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 1d7e55213..dfe837c06 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.907672 # Number of seconds simulated -sim_ticks 1907672102500 # Number of ticks simulated -final_tick 1907672102500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906534 # Number of seconds simulated +sim_ticks 1906533530000 # Number of ticks simulated +final_tick 1906533530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159928 # Simulator instruction rate (inst/s) -host_op_rate 159928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5430263290 # Simulator tick rate (ticks/s) -host_mem_usage 337712 # Number of bytes of host memory used -host_seconds 351.30 # Real time elapsed on the host -sim_insts 56183395 # Number of instructions simulated -sim_ops 56183395 # Number of ops (including micro ops) simulated +host_inst_rate 134861 # Simulator instruction rate (inst/s) +host_op_rate 134861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4533949866 # Simulator tick rate (ticks/s) +host_mem_usage 343876 # Number of bytes of host memory used +host_seconds 420.50 # Real time elapsed on the host +sim_insts 56709432 # Number of instructions simulated +sim_ops 56709432 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 861632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24651584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 117952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 582656 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 896192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24492096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 81664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 812544 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26214784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 861632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 117952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 979584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7845056 # Number of bytes written to this memory -system.physmem.bytes_written::total 7845056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9104 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26283456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 896192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 81664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7904832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7904832 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14003 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 382689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12696 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 409606 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122579 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122579 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 451667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12922338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 61830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 305428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13741766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 451667 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 61830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4112371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4112371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4112371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 451667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12922338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 61830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 305428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17854137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 409606 # Number of read requests accepted -system.physmem.writeReqs 122579 # Number of write requests accepted -system.physmem.readBursts 409606 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122579 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26206336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7843200 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26214784 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7845056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410679 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123513 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123513 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 470064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12846402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 42834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 426189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13785992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 470064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 42834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512897 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4146180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4146180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4146180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 470064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12846402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 42834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 426189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17932172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410679 # Number of read requests accepted +system.physmem.writeReqs 123513 # Number of write requests accepted +system.physmem.readBursts 410679 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123513 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26276352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 7903488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26283456 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7904832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26087 # Per bank write bursts -system.physmem.perBankRdBursts::1 25986 # Per bank write bursts -system.physmem.perBankRdBursts::2 25681 # Per bank write bursts -system.physmem.perBankRdBursts::3 25351 # Per bank write bursts -system.physmem.perBankRdBursts::4 24681 # Per bank write bursts -system.physmem.perBankRdBursts::5 24934 # Per bank write bursts -system.physmem.perBankRdBursts::6 25045 # Per bank write bursts -system.physmem.perBankRdBursts::7 25140 # Per bank write bursts -system.physmem.perBankRdBursts::8 25540 # Per bank write bursts -system.physmem.perBankRdBursts::9 26037 # Per bank write bursts -system.physmem.perBankRdBursts::10 25956 # Per bank write bursts -system.physmem.perBankRdBursts::11 25606 # Per bank write bursts -system.physmem.perBankRdBursts::12 26142 # Per bank write bursts -system.physmem.perBankRdBursts::13 25795 # Per bank write bursts -system.physmem.perBankRdBursts::14 25668 # Per bank write bursts -system.physmem.perBankRdBursts::15 25825 # Per bank write bursts -system.physmem.perBankWrBursts::0 8182 # Per bank write bursts -system.physmem.perBankWrBursts::1 8217 # Per bank write bursts -system.physmem.perBankWrBursts::2 8055 # Per bank write bursts -system.physmem.perBankWrBursts::3 7694 # Per bank write bursts -system.physmem.perBankWrBursts::4 7332 # Per bank write bursts -system.physmem.perBankWrBursts::5 7389 # Per bank write bursts -system.physmem.perBankWrBursts::6 7497 # Per bank write bursts -system.physmem.perBankWrBursts::7 6907 # Per bank write bursts -system.physmem.perBankWrBursts::8 7336 # Per bank write bursts -system.physmem.perBankWrBursts::9 7821 # Per bank write bursts -system.physmem.perBankWrBursts::10 7658 # Per bank write bursts -system.physmem.perBankWrBursts::11 7295 # Per bank write bursts -system.physmem.perBankWrBursts::12 7753 # Per bank write bursts -system.physmem.perBankWrBursts::13 7589 # Per bank write bursts -system.physmem.perBankWrBursts::14 7825 # Per bank write bursts -system.physmem.perBankWrBursts::15 8000 # Per bank write bursts +system.physmem.perBankRdBursts::0 26110 # Per bank write bursts +system.physmem.perBankRdBursts::1 26073 # Per bank write bursts +system.physmem.perBankRdBursts::2 25765 # Per bank write bursts +system.physmem.perBankRdBursts::3 25777 # Per bank write bursts +system.physmem.perBankRdBursts::4 25805 # Per bank write bursts +system.physmem.perBankRdBursts::5 25558 # Per bank write bursts +system.physmem.perBankRdBursts::6 25453 # Per bank write bursts +system.physmem.perBankRdBursts::7 25268 # Per bank write bursts +system.physmem.perBankRdBursts::8 25514 # Per bank write bursts +system.physmem.perBankRdBursts::9 25670 # Per bank write bursts +system.physmem.perBankRdBursts::10 25901 # Per bank write bursts +system.physmem.perBankRdBursts::11 25385 # Per bank write bursts +system.physmem.perBankRdBursts::12 25810 # Per bank write bursts +system.physmem.perBankRdBursts::13 25833 # Per bank write bursts +system.physmem.perBankRdBursts::14 25046 # Per bank write bursts +system.physmem.perBankRdBursts::15 25600 # Per bank write bursts +system.physmem.perBankWrBursts::0 8438 # Per bank write bursts +system.physmem.perBankWrBursts::1 8395 # Per bank write bursts +system.physmem.perBankWrBursts::2 7934 # Per bank write bursts +system.physmem.perBankWrBursts::3 7573 # Per bank write bursts +system.physmem.perBankWrBursts::4 7567 # Per bank write bursts +system.physmem.perBankWrBursts::5 7501 # Per bank write bursts +system.physmem.perBankWrBursts::6 7444 # Per bank write bursts +system.physmem.perBankWrBursts::7 7061 # Per bank write bursts +system.physmem.perBankWrBursts::8 7349 # Per bank write bursts +system.physmem.perBankWrBursts::9 7703 # Per bank write bursts +system.physmem.perBankWrBursts::10 7693 # Per bank write bursts +system.physmem.perBankWrBursts::11 7415 # Per bank write bursts +system.physmem.perBankWrBursts::12 7960 # Per bank write bursts +system.physmem.perBankWrBursts::13 8226 # Per bank write bursts +system.physmem.perBankWrBursts::14 7426 # Per bank write bursts +system.physmem.perBankWrBursts::15 7807 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 1907667754500 # Total gap between requests +system.physmem.numWrRetry 24 # Number of times write queue was full causing retry +system.physmem.totGap 1906529083500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 409606 # Read request sizes (log2) +system.physmem.readPktSize::6 410679 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122579 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123513 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see @@ -159,193 +159,209 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.308617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.463735 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.737705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14846 22.95% 22.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11278 17.43% 40.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5774 8.92% 49.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2666 4.12% 53.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2483 3.84% 57.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1468 2.27% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1658 2.56% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1459 2.26% 64.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23063 35.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64695 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5527 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.082685 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2821.240872 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5524 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64501 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 529.911784 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 323.379229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.310744 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14472 22.44% 22.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11319 17.55% 39.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5673 8.80% 48.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2735 4.24% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2521 3.91% 56.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1561 2.42% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1592 2.47% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1422 2.20% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23206 35.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64501 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5582 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.544966 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2807.309852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5579 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5527 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5527 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.172969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.909622 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.446069 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4919 89.00% 89.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 36 0.65% 89.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 243 4.40% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 19 0.34% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 15 0.27% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 14 0.25% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 95.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 36 0.65% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 13 0.24% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 182 3.29% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.05% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 4 0.07% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.05% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 5 0.09% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 12 0.22% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5527 # Writes before turning the bus around for reads -system.physmem.totQLat 3957301251 # Total ticks spent queuing -system.physmem.totMemAccLat 11634938751 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2047370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9664.35 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5582 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5582 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.123253 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.862531 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.587113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4829 86.51% 86.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 142 2.54% 89.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.27% 89.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 29 0.52% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 220 3.94% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.38% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.23% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.11% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 3 0.05% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.14% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.14% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.13% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.38% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.04% 95.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 16 0.29% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 179 3.21% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.04% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.04% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.09% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 13 0.23% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5582 # Writes before turning the bus around for reads +system.physmem.totQLat 4047296750 # Total ticks spent queuing +system.physmem.totMemAccLat 11745446750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9857.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28414.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.74 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.74 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28607.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing -system.physmem.readRowHits 368811 # Number of row buffer hits during reads -system.physmem.writeRowHits 98518 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.37 # Row buffer hit rate for writes -system.physmem.avgGap 3584595.12 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244392120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133348875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1582659000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 397049040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124599742800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57755737350 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1093939329000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278652258185 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.268952 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1819699135250 # Time in different power states -system.physmem_0.memoryStateTime::REF 63701300000 # Time in different power states +system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.95 # Average write queue length when enqueuing +system.physmem.readRowHits 369870 # Number of row buffer hits during reads +system.physmem.writeRowHits 99689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.71 # Row buffer hit rate for writes +system.physmem.avgGap 3568995.95 # Average gap between requests +system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245828520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134132625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1605310200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 401196240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 58054066515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1092995561250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1277961588390 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.306343 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1818124535500 # Time in different power states +system.physmem_0.memoryStateTime::REF 63663080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24270006000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24745773250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244702080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133518000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1611238200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397074960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124599742800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57480963435 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1094180367000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278647606475 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.266509 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1820097449251 # Time in different power states -system.physmem_1.memoryStateTime::REF 63701300000 # Time in different power states +system.physmem_1.actEnergy 241799040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131934000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597120200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 399031920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57215830500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1093730864250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1277842072950 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.243651 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1819353589250 # Time in different power states +system.physmem_1.memoryStateTime::REF 63663080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23871705749 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23516733250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 18486901 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15748793 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 541835 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 11639433 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5170762 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16961800 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14485891 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 473040 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10754552 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4802971 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.424518 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1045004 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 41208 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5538250 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 525213 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 5013037 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 248456 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.659889 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 946597 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 35405 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5065158 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 501808 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4563350 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 210940 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 10388247 # DTB read hits -system.cpu0.dtb.read_misses 39745 # DTB read misses +system.cpu0.dtb.read_hits 9542415 # DTB read hits +system.cpu0.dtb.read_misses 34570 # DTB read misses system.cpu0.dtb.read_acv 614 # DTB read access violations -system.cpu0.dtb.read_accesses 666259 # DTB read accesses -system.cpu0.dtb.write_hits 6304219 # DTB write hits -system.cpu0.dtb.write_misses 9494 # DTB write misses -system.cpu0.dtb.write_acv 419 # DTB write access violations -system.cpu0.dtb.write_accesses 221498 # DTB write accesses -system.cpu0.dtb.data_hits 16692466 # DTB hits -system.cpu0.dtb.data_misses 49239 # DTB misses -system.cpu0.dtb.data_acv 1033 # DTB access violations -system.cpu0.dtb.data_accesses 887757 # DTB accesses -system.cpu0.itb.fetch_hits 1498511 # ITB hits -system.cpu0.itb.fetch_misses 7842 # ITB misses -system.cpu0.itb.fetch_acv 715 # ITB acv -system.cpu0.itb.fetch_accesses 1506353 # ITB accesses +system.cpu0.dtb.read_accesses 570502 # DTB read accesses +system.cpu0.dtb.write_hits 5776455 # DTB write hits +system.cpu0.dtb.write_misses 8473 # DTB write misses +system.cpu0.dtb.write_acv 390 # DTB write access violations +system.cpu0.dtb.write_accesses 186760 # DTB write accesses +system.cpu0.dtb.data_hits 15318870 # DTB hits +system.cpu0.dtb.data_misses 43043 # DTB misses +system.cpu0.dtb.data_acv 1004 # DTB access violations +system.cpu0.dtb.data_accesses 757262 # DTB accesses +system.cpu0.itb.fetch_hits 1323023 # ITB hits +system.cpu0.itb.fetch_misses 7096 # ITB misses +system.cpu0.itb.fetch_acv 610 # ITB acv +system.cpu0.itb.fetch_accesses 1330119 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -358,606 +374,606 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12731 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6366 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 290215354.618913 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 443182270.048279 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 4 0.06% 0.06% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6362 99.94% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 13007 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6504 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 284289977.091175 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440390387.503353 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6503 99.98% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6366 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 60161154996 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847510947504 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 120328672 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6504 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 57511518999 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849022011001 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 115029541 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 28758768 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 80605672 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 18486901 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6740979 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 84470777 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1538724 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 99 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 156668 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 425628 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 282 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 9251036 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 365043 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.icacheStallCycles 26105514 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 74391279 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16961800 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6251376 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 82220028 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1360432 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28534 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 140847 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 424678 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8564382 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 320281 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 114609928 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.703304 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.035053 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 109600123 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.678752 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.000671 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 99708886 87.00% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 974143 0.85% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1998972 1.74% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 868407 0.76% 90.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2758687 2.41% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 641235 0.56% 93.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 755467 0.66% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 978409 0.85% 94.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5925722 5.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 95795479 87.40% 87.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 897061 0.82% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1880834 1.72% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 785387 0.72% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2637004 2.41% 93.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 588358 0.54% 93.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 697546 0.64% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 846325 0.77% 95.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5472129 4.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 114609928 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.153637 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.669879 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 23115734 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 79187494 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9649471 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1920435 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 736793 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 689182 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 33223 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 69733339 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 101960 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 736793 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24053074 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 52045501 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18448869 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10567955 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8757734 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 66954427 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 200777 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2040075 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 234878 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4698433 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 45085797 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 80572701 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 80419250 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 143477 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36303569 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8782228 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1592248 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 261178 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 13101083 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10872978 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6724173 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1603556 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1060240 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 59089633 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2074933 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 57153011 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 84826 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10861661 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4738821 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1447538 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 114609928 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.498674 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.243633 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 109600123 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.147456 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.646715 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20981522 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 77286866 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8861450 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1818601 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 651683 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 621495 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29133 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 64563390 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 88112 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 651683 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21851256 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 51776932 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17156942 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9742291 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8421017 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 62086646 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 197170 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2004328 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 218757 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4545100 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41879351 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 74952395 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 74819888 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 123702 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34134806 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7744545 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1440211 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 234687 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12404512 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9945616 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6151141 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1474462 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 959878 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54892526 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1879962 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 53219239 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 73531 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9606336 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4159079 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1308684 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 109600123 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.485576 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.229164 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 91405720 79.75% 79.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9883367 8.62% 88.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4163005 3.63% 92.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2977529 2.60% 94.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 3083312 2.69% 97.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1549770 1.35% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1029487 0.90% 99.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 389877 0.34% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 127861 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 87964311 80.26% 80.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9240201 8.43% 88.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3866881 3.53% 92.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2775272 2.53% 94.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2892547 2.64% 97.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1421694 1.30% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 953270 0.87% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 366394 0.33% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 119553 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 114609928 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 109600123 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 177461 15.95% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 577417 51.89% 67.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 357940 32.17% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 170160 16.71% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 520319 51.11% 67.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 327644 32.18% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 38903396 68.07% 68.07% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60002 0.10% 68.18% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28431 0.05% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 10881663 19.04% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6404122 11.21% 98.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 870425 1.52% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36500931 68.59% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56437 0.11% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25510 0.05% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9976302 18.75% 87.49% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5867670 11.03% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 788585 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 57153011 # Type of FU issued -system.cpu0.iq.rate 0.474974 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1112818 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019471 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 229452003 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 71724793 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 55161872 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 661591 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 320309 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 299753 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 57905331 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 357182 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 649944 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 53219239 # Type of FU issued +system.cpu0.iq.rate 0.462657 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1018124 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019131 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 216556534 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 66119650 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51474452 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 573722 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 277081 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 260310 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53925009 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 309817 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 608784 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2311061 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3974 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19354 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 772397 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1996070 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4265 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18313 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 688901 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18463 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 400325 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18448 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 363376 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 736793 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 48901711 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 778245 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 65010536 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 175759 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10872978 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6724173 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1839088 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42617 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 533932 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19354 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 209386 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 582195 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 791581 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 56370431 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 10457447 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 782580 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 651683 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 48679015 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 759858 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 60350483 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 162315 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9945616 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6151141 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1664805 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40490 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 518912 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18313 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186521 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 513145 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 699666 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52530190 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9602772 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 689049 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3845970 # number of nop insts executed -system.cpu0.iew.exec_refs 16790279 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8937296 # Number of branches executed -system.cpu0.iew.exec_stores 6332832 # Number of stores executed -system.cpu0.iew.exec_rate 0.468470 # Inst execution rate -system.cpu0.iew.wb_sent 55678100 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 55461625 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 28192926 # num instructions producing a value -system.cpu0.iew.wb_consumers 39039520 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.460918 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.722164 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 11448425 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 627395 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 706831 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112623597 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.474128 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.409611 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3577995 # number of nop insts executed +system.cpu0.iew.exec_refs 15404618 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8349417 # Number of branches executed +system.cpu0.iew.exec_stores 5801846 # Number of stores executed +system.cpu0.iew.exec_rate 0.456667 # Inst execution rate +system.cpu0.iew.wb_sent 51922146 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51734762 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26504573 # num instructions producing a value +system.cpu0.iew.wb_consumers 36648490 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.449752 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723211 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10116425 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 571278 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 623596 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 107842796 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.464314 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.394503 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 93749029 83.24% 83.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7554104 6.71% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4011836 3.56% 93.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2145505 1.91% 95.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1663134 1.48% 96.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 616876 0.55% 97.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 455080 0.40% 97.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 507934 0.45% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1920099 1.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 90117032 83.56% 83.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7061240 6.55% 90.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3809100 3.53% 93.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2021336 1.87% 95.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1578999 1.46% 96.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 575276 0.53% 97.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 421394 0.39% 97.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 458654 0.43% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1799765 1.67% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112623597 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53398017 # Number of instructions committed -system.cpu0.commit.committedOps 53398017 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 107842796 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50072886 # Number of instructions committed +system.cpu0.commit.committedOps 50072886 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14513693 # Number of memory references committed -system.cpu0.commit.loads 8561917 # Number of loads committed -system.cpu0.commit.membars 214579 # Number of memory barriers committed -system.cpu0.commit.branches 8068022 # Number of branches committed -system.cpu0.commit.fp_insts 288973 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49410509 # Number of committed integer instructions. -system.cpu0.commit.function_calls 696168 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 3098426 5.80% 5.80% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 34606705 64.81% 70.61% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 58588 0.11% 70.72% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 27960 0.05% 70.77% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.77% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.77% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.77% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8776496 16.44% 87.21% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5957761 11.16% 98.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 870425 1.63% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13411786 # Number of memory references committed +system.cpu0.commit.loads 7949546 # Number of loads committed +system.cpu0.commit.membars 194670 # Number of memory barriers committed +system.cpu0.commit.branches 7579863 # Number of branches committed +system.cpu0.commit.fp_insts 251347 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46348996 # Number of committed integer instructions. +system.cpu0.commit.function_calls 640938 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2909270 5.81% 5.81% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32681197 65.27% 71.08% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55117 0.11% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 25038 0.05% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8144216 16.26% 87.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5468196 10.92% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 788585 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 53398017 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1920099 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 175358628 # The number of ROB reads -system.cpu0.rob.rob_writes 131681344 # The number of ROB writes -system.cpu0.timesIdled 541437 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5718744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3694399415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50302904 # Number of Instructions Simulated -system.cpu0.committedOps 50302904 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.392082 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.392082 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.418046 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.418046 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 73576817 # number of integer regfile reads -system.cpu0.int_regfile_writes 40321383 # number of integer regfile writes -system.cpu0.fp_regfile_reads 142542 # number of floating regfile reads -system.cpu0.fp_regfile_writes 152983 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1859375 # number of misc regfile reads -system.cpu0.misc_regfile_writes 873240 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1336574 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.845930 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11809421 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1336976 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.832934 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 50072886 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1799765 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 166055766 # The number of ROB reads +system.cpu0.rob.rob_writes 122136916 # The number of ROB writes +system.cpu0.timesIdled 488999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5429418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3697477415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47166151 # Number of Instructions Simulated +system.cpu0.committedOps 47166151 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.438816 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.438816 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.410035 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.410035 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68768616 # number of integer regfile reads +system.cpu0.int_regfile_writes 37693548 # number of integer regfile writes +system.cpu0.fp_regfile_reads 122704 # number of floating regfile reads +system.cpu0.fp_regfile_writes 131478 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1676808 # number of misc regfile reads +system.cpu0.misc_regfile_writes 792469 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1260860 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.428743 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10814422 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1261290 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.574096 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.845930 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62763513 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62763513 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 7501117 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7501117 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3904271 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3904271 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 200075 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 200075 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 202804 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 202804 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11405388 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11405388 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11405388 # number of overall hits -system.cpu0.dcache.overall_hits::total 11405388 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1695209 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1695209 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1829361 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1829361 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22067 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22067 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 927 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 927 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3524570 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3524570 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3524570 # number of overall misses -system.cpu0.dcache.overall_misses::total 3524570 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40549578500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40549578500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77276130293 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77276130293 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333041000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 333041000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6753500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 6753500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117825708793 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117825708793 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117825708793 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117825708793 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 9196326 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9196326 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5733632 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5733632 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 222142 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 222142 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 203731 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 203731 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14929958 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14929958 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14929958 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14929958 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184335 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.184335 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.319058 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.319058 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.099337 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.099337 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004550 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004550 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236074 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.236074 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236074 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.236074 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23920.105721 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23920.105721 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42242.143728 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42242.143728 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15092.264467 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15092.264467 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7285.329018 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7285.329018 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33429.810954 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33429.810954 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33429.810954 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33429.810954 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4313991 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 8795 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 119168 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 132 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.200918 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 66.628788 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 791920 # number of writebacks -system.cpu0.dcache.writebacks::total 791920 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 639925 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 639925 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1556053 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1556053 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6507 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6507 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2195978 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2195978 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2195978 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2195978 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1055284 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1055284 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273308 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 273308 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15560 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15560 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 926 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 926 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1328592 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1328592 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1328592 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1328592 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7032 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7032 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9755 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9755 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16787 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16787 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30284931500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30284931500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12180596213 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12180596213 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 192236000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 192236000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5827500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5827500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42465527713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 42465527713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42465527713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 42465527713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566422000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566422000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566422000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566422000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114751 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114751 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047668 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047668 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.070045 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.070045 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004545 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004545 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088988 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.088988 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088988 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.088988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28698.370770 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28698.370770 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44567.287503 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44567.287503 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12354.498715 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12354.498715 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6293.196544 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6293.196544 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31962.805521 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31962.805521 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31962.805521 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31962.805521 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222756.257110 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222756.257110 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93311.610175 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93311.610175 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1014611 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.545427 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 8173897 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1015123 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.052125 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28452447500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.545427 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995206 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995206 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 10266395 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 10266395 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 8173897 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 8173897 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 8173897 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 8173897 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 8173897 # number of overall hits -system.cpu0.icache.overall_hits::total 8173897 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1077136 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1077136 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1077136 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1077136 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1077136 # number of overall misses -system.cpu0.icache.overall_misses::total 1077136 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15255278493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 15255278493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 15255278493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 15255278493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 15255278493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 15255278493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 9251033 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 9251033 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 9251033 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 9251033 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 9251033 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 9251033 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116434 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116434 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116434 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116434 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116434 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116434 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14162.815553 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14162.815553 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14162.815553 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14162.815553 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14162.815553 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14162.815553 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5826 # number of cycles access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.428743 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989119 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.989119 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 57625075 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 57625075 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6881291 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6881291 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3568585 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3568585 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177059 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 177059 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 182551 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 182551 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10449876 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10449876 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10449876 # number of overall hits +system.cpu0.dcache.overall_hits::total 10449876 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1562512 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1562512 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1693924 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1693924 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20209 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20209 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2828 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2828 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3256436 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3256436 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3256436 # number of overall misses +system.cpu0.dcache.overall_misses::total 3256436 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38980676000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 38980676000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74553561151 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 74553561151 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 291267500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 291267500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 15945500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 15945500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 113534237151 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 113534237151 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 113534237151 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 113534237151 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8443803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8443803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5262509 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5262509 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 197268 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 197268 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 185379 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 185379 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13706312 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13706312 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13706312 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13706312 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.185048 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.185048 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.321885 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.321885 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102444 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102444 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015255 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015255 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.237587 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.237587 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.237587 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.237587 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24947.441044 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24947.441044 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44012.341257 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44012.341257 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14412.761641 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14412.761641 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5638.437058 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5638.437058 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34864.568857 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34864.568857 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4192146 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2471 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 109181 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.396296 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 29.771084 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 743371 # number of writebacks +system.cpu0.dcache.writebacks::total 743371 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 555767 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 555767 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1440437 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1440437 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5460 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5460 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1996204 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1996204 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1996204 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1996204 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1006745 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1006745 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253487 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 253487 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14749 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14749 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2828 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2828 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1260232 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1260232 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1260232 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1260232 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7013 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7013 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10003 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10003 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17016 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17016 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29619600000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29619600000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11703772725 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11703772725 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170858500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170858500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 13117500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 13117500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41323372725 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 41323372725 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41323372725 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 41323372725 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563340000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563340000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1563340000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1563340000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119229 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119229 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048168 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048168 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074766 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074766 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015255 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015255 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091945 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091945 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29421.154314 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29421.154314 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46171.096447 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46171.096447 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11584.412503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11584.412503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4638.437058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4638.437058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222920.290888 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222920.290888 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91874.706159 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91874.706159 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 908505 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.512047 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7601055 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 909016 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.361850 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28452405500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.512047 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995141 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995141 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9473645 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9473645 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7601055 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7601055 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7601055 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7601055 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7601055 # number of overall hits +system.cpu0.icache.overall_hits::total 7601055 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 963326 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 963326 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 963326 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 963326 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 963326 # number of overall misses +system.cpu0.icache.overall_misses::total 963326 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13819823495 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13819823495 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13819823495 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13819823495 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13819823495 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13819823495 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8564381 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8564381 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8564381 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8564381 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8564381 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8564381 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112481 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.112481 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112481 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.112481 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112481 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.112481 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14345.946746 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14345.946746 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14345.946746 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14345.946746 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6257 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 231 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.220779 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.822660 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1014611 # number of writebacks -system.cpu0.icache.writebacks::total 1014611 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 61774 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 61774 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 61774 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 61774 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 61774 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 61774 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1015362 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1015362 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1015362 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1015362 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1015362 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1015362 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13566878495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13566878495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13566878495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13566878495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13566878495 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13566878495 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109757 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.109757 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.109757 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13361.617330 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13361.617330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13361.617330 # average overall mshr miss latency -system.cpu1.branchPred.lookups 2716012 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2349135 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 64284 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1339574 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 486642 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 908505 # number of writebacks +system.cpu0.icache.writebacks::total 908505 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54062 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54062 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54062 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54062 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54062 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54062 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909264 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 909264 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 909264 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 909264 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 909264 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 909264 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12278033496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12278033496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12278033496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12278033496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12278033496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12278033496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.106168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.106168 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.106168 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13503.265824 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4250134 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3659200 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 108723 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2354380 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 849662 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.328116 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 131116 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4300 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 740387 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 107863 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 632524 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 18463 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 36.088567 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 217108 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8204 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1308734 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 157441 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1151293 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 37897 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1491854 # DTB read hits -system.cpu1.dtb.read_misses 11707 # DTB read misses -system.cpu1.dtb.read_acv 49 # DTB read access violations -system.cpu1.dtb.read_accesses 336889 # DTB read accesses -system.cpu1.dtb.write_hits 824931 # DTB write hits -system.cpu1.dtb.write_misses 2806 # DTB write misses -system.cpu1.dtb.write_acv 46 # DTB write access violations -system.cpu1.dtb.write_accesses 126281 # DTB write accesses -system.cpu1.dtb.data_hits 2316785 # DTB hits -system.cpu1.dtb.data_misses 14513 # DTB misses -system.cpu1.dtb.data_acv 95 # DTB access violations -system.cpu1.dtb.data_accesses 463170 # DTB accesses -system.cpu1.itb.fetch_hits 477856 # ITB hits -system.cpu1.itb.fetch_misses 2662 # ITB misses -system.cpu1.itb.fetch_acv 96 # ITB acv -system.cpu1.itb.fetch_accesses 480518 # ITB accesses +system.cpu1.dtb.read_hits 2331871 # DTB read hits +system.cpu1.dtb.read_misses 15400 # DTB read misses +system.cpu1.dtb.read_acv 73 # DTB read access violations +system.cpu1.dtb.read_accesses 429786 # DTB read accesses +system.cpu1.dtb.write_hits 1381774 # DTB write hits +system.cpu1.dtb.write_misses 3743 # DTB write misses +system.cpu1.dtb.write_acv 71 # DTB write access violations +system.cpu1.dtb.write_accesses 161427 # DTB write accesses +system.cpu1.dtb.data_hits 3713645 # DTB hits +system.cpu1.dtb.data_misses 19143 # DTB misses +system.cpu1.dtb.data_acv 144 # DTB access violations +system.cpu1.dtb.data_accesses 591213 # DTB accesses +system.cpu1.itb.fetch_hits 662529 # ITB hits +system.cpu1.itb.fetch_misses 3380 # ITB misses +system.cpu1.itb.fetch_acv 133 # ITB acv +system.cpu1.itb.fetch_accesses 665909 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -970,580 +986,572 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 4646 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2323 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 818936669.177787 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 339506423.560652 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2323 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 4980 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2490 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 762354971.285141 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 386526411.344669 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2490 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975573000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2323 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 5282220000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1902389882500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 10566764 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 975501000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2490 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8269651500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898263878500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 16541794 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 3825216 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 10675597 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2716012 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 725621 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 5983543 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 229964 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 23815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 51735 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 41039 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1221851 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48225 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 10040370 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.063267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.470833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6749073 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16895090 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4250134 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1224211 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 8698208 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 363130 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26231 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65753 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47571 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1900929 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 80768 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15768440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.071450 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.476995 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 8168289 81.35% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 102687 1.02% 82.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 210133 2.09% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 146343 1.46% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 249317 2.48% 88.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 97935 0.98% 89.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 113554 1.13% 90.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 71548 0.71% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 880564 8.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12797159 81.16% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 186632 1.18% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 321640 2.04% 84.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 225512 1.43% 85.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 384419 2.44% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 144313 0.92% 89.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 169042 1.07% 90.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 202635 1.29% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1337088 8.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 10040370 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.257033 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.010300 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3212898 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 5233388 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1306839 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 176592 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 110652 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 87490 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4477 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8611500 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 14236 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 110652 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3332108 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 534859 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3861101 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1363516 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 838132 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 8128723 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 840 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 81504 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 20811 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 431912 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 5442265 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9792683 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9760108 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 27875 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4220598 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1221659 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 323796 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 24055 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1462372 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1548375 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 895151 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 190303 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 111620 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 7151730 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 356002 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6823456 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 19520 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1627236 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 806919 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 274884 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 10040370 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.679602 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.404814 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15768440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.256933 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.021358 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5523877 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7693314 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2103455 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 273251 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 174542 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 146034 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7171 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 13792543 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22640 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 174542 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5705734 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 782365 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5725411 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2195690 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1184696 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13060888 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4153 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 107025 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 30497 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 586772 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 8670673 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 15585724 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 15521516 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 57730 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6788049 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1882616 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 491915 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 50500 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2201368 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2434805 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1482534 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 303562 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 164759 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11452007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 560044 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10991859 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27120 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2468765 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1174488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 414117 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15768440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.697080 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.421678 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 7219551 71.91% 71.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1226248 12.21% 84.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 523144 5.21% 89.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 383300 3.82% 93.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 329501 3.28% 96.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 173963 1.73% 98.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 102712 1.02% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 58679 0.58% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 23272 0.23% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11265469 71.44% 71.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1937394 12.29% 83.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 827410 5.25% 88.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 596936 3.79% 92.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 547934 3.47% 96.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 289502 1.84% 98.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 188780 1.20% 99.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 83209 0.53% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 31806 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 10040370 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15768440 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 25321 11.84% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 118979 55.64% 67.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 69548 32.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32091 10.27% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173932 55.66% 65.93% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 106485 34.07% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3973 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 4192346 61.44% 61.50% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10770 0.16% 61.66% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10332 0.15% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1560504 22.87% 84.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 845461 12.39% 97.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 198084 2.90% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6803980 61.90% 61.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16523 0.15% 62.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 13867 0.13% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2450394 22.29% 84.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1410696 12.83% 97.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 289273 2.63% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6823456 # Type of FU issued -system.cpu1.iq.rate 0.645747 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 213848 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.031340 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 23830038 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 9093503 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6518367 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 90611 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 45521 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 43008 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6985974 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 47357 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 77493 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10991859 # Type of FU issued +system.cpu1.iq.rate 0.664490 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 312508 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028431 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 37874505 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14381418 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10489971 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 217280 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 104295 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 101356 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11183979 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 115637 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 113432 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 335188 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 932 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4197 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 122462 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 527848 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1066 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5067 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 174171 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 439 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 72925 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 475 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99025 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 110652 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 347034 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 152695 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7850434 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 37055 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1548375 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 895151 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 329794 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4928 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 146829 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4197 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 25483 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 92224 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117707 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6707770 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1507715 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 115685 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 174542 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 497039 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 226226 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 12632900 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 57966 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2434805 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1482534 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 508876 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6584 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 218362 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5067 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 44763 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 141821 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 186584 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10809707 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2356029 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 182151 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 342702 # number of nop insts executed -system.cpu1.iew.exec_refs 2339108 # number of memory reference insts executed -system.cpu1.iew.exec_branches 982956 # Number of branches executed -system.cpu1.iew.exec_stores 831393 # Number of stores executed -system.cpu1.iew.exec_rate 0.634799 # Inst execution rate -system.cpu1.iew.wb_sent 6597173 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6561375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3197425 # num instructions producing a value -system.cpu1.iew.wb_consumers 4464974 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.620945 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.716113 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1594434 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 81118 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 100274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9755465 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.627758 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.585985 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 620849 # number of nop insts executed +system.cpu1.iew.exec_refs 3747857 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1612675 # Number of branches executed +system.cpu1.iew.exec_stores 1391828 # Number of stores executed +system.cpu1.iew.exec_rate 0.653479 # Inst execution rate +system.cpu1.iew.wb_sent 10644010 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 10591327 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5073681 # num instructions producing a value +system.cpu1.iew.wb_consumers 7144079 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.640277 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710194 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2479122 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 145927 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 162123 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 15327061 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.652859 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.628724 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 7484983 76.73% 76.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1079374 11.06% 87.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 367183 3.76% 91.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 234920 2.41% 93.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 168491 1.73% 95.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 74517 0.76% 96.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76064 0.78% 97.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 56824 0.58% 97.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 213109 2.18% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11704556 76.37% 76.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1675096 10.93% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 596024 3.89% 91.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 370132 2.41% 93.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 281840 1.84% 95.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 119415 0.78% 96.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 109784 0.72% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 115974 0.76% 97.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 354240 2.31% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9755465 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 6124073 # Number of instructions committed -system.cpu1.commit.committedOps 6124073 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 15327061 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10006417 # Number of instructions committed +system.cpu1.commit.committedOps 10006417 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1985876 # Number of memory references committed -system.cpu1.commit.loads 1213187 # Number of loads committed -system.cpu1.commit.membars 22586 # Number of memory barriers committed -system.cpu1.commit.branches 866488 # Number of branches committed -system.cpu1.commit.fp_insts 41227 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5722327 # Number of committed integer instructions. -system.cpu1.commit.function_calls 95129 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 247554 4.04% 4.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 3646853 59.55% 63.59% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 10597 0.17% 63.76% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.76% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10326 0.17% 63.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1235773 20.18% 84.14% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 772900 12.62% 96.77% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 198084 3.23% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3215320 # Number of memory references committed +system.cpu1.commit.loads 1906957 # Number of loads committed +system.cpu1.commit.membars 46297 # Number of memory barriers committed +system.cpu1.commit.branches 1432968 # Number of branches committed +system.cpu1.commit.fp_insts 99355 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9296453 # Number of committed integer instructions. +system.cpu1.commit.function_calls 155642 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 467886 4.68% 4.68% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5954632 59.51% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16225 0.16% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13860 0.14% 64.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1953254 19.52% 84.03% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1308912 13.08% 97.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 289273 2.89% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 6124073 # Class of committed instruction -system.cpu1.commit.bw_lim_events 213109 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 17170417 # The number of ROB reads -system.cpu1.rob.rob_writes 15719262 # The number of ROB writes -system.cpu1.timesIdled 71397 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 526394 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3804777442 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5880491 # Number of Instructions Simulated -system.cpu1.committedOps 5880491 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.796919 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.796919 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556508 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556508 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8685381 # number of integer regfile reads -system.cpu1.int_regfile_writes 4740732 # number of integer regfile writes -system.cpu1.fp_regfile_reads 27201 # number of floating regfile reads -system.cpu1.fp_regfile_writes 25643 # number of floating regfile writes -system.cpu1.misc_regfile_reads 310247 # number of misc regfile reads -system.cpu1.misc_regfile_writes 141917 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 65099 # number of replacements -system.cpu1.dcache.tags.tagsinuse 463.722972 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1848833 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 65611 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.178705 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1879972526500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.722972 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905709 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.905709 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10006417 # Class of committed instruction +system.cpu1.commit.bw_lim_events 354240 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 27350454 # The number of ROB reads +system.cpu1.rob.rob_writes 25410376 # The number of ROB writes +system.cpu1.timesIdled 127916 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 773354 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3796525267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9543281 # Number of Instructions Simulated +system.cpu1.committedOps 9543281 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.733345 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.733345 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.576919 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.576919 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13915898 # number of integer regfile reads +system.cpu1.int_regfile_writes 7574327 # number of integer regfile writes +system.cpu1.fp_regfile_reads 57027 # number of floating regfile reads +system.cpu1.fp_regfile_writes 56084 # number of floating regfile writes +system.cpu1.misc_regfile_reads 548336 # number of misc regfile reads +system.cpu1.misc_regfile_writes 233992 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 125899 # number of replacements +system.cpu1.dcache.tags.tagsinuse 488.643443 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2930828 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 126411 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.184913 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 47496090500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.643443 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954382 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.954382 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 8556411 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 8556411 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1222356 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1222356 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 588321 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 588321 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 17437 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 17437 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 16296 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 16296 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1810677 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1810677 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1810677 # number of overall hits -system.cpu1.dcache.overall_hits::total 1810677 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 112363 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 112363 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 161965 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 161965 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1793 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1793 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 891 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 891 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 274328 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 274328 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 274328 # number of overall misses -system.cpu1.dcache.overall_misses::total 274328 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1482127500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1482127500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7331574147 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7331574147 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19537500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 19537500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6718500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 6718500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 34500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 34500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8813701647 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8813701647 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8813701647 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8813701647 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1334719 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1334719 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 750286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 750286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 19230 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 19230 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 17187 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 17187 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2085005 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2085005 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2085005 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2085005 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.084185 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.084185 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.215871 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.215871 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093240 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093240 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.051842 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.051842 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131572 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.131572 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131572 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.131572 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13190.529801 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13190.529801 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 45266.410317 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 45266.410317 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10896.542108 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10896.542108 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7540.404040 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7540.404040 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32128.334137 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32128.334137 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32128.334137 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32128.334137 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 454264 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 482 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15527 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.256392 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 48.200000 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 38456 # number of writebacks -system.cpu1.dcache.writebacks::total 38456 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66033 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 66033 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137281 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 137281 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 379 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 379 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 203314 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 203314 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 203314 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 203314 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 46330 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 46330 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24684 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 24684 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1414 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1414 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 891 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 891 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 71014 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 71014 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 71014 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 71014 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2639 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2639 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 2801 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 2801 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 590183000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 590183000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1153615997 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1153615997 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13566500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13566500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5828500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5828500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 33500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 33500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1743798997 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1743798997 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1743798997 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1743798997 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32350500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32350500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32350500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32350500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032899 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032899 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073531 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073531 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.051842 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.051842 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034059 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034059 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034059 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034059 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12738.679042 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12738.679042 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46735.375020 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46735.375020 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9594.413013 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9594.413013 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6541.526375 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6541.526375 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24555.707283 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24555.707283 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24555.707283 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24555.707283 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199694.444444 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 199694.444444 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11549.625134 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11549.625134 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 129926 # number of replacements -system.cpu1.icache.tags.tagsinuse 466.448190 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1084325 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 130435 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.313144 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880575078500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.448190 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911032 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.911032 # Average percentage of cache occupancy +system.cpu1.dcache.tags.tag_accesses 13906652 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 13906652 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1865609 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1865609 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 981966 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 981966 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 38120 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 38120 # 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number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2912 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 514242 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 514242 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 514242 # number of overall misses +system.cpu1.dcache.overall_misses::total 514242 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3027811000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3027811000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10676531998 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10676531998 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51207500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 51207500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 16199500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 16199500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13704342998 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13704342998 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13704342998 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13704342998 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2097428 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2097428 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1264389 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1264389 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 43198 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 43198 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 37769 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 37769 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3361817 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3361817 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3361817 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3361817 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110525 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110525 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223367 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.223367 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117552 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117552 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.077100 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.077100 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152965 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152965 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152965 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152965 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13061.099392 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13061.099392 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37803.337540 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37803.337540 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10084.186688 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10084.186688 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5563.015110 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5563.015110 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26649.598823 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26649.598823 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 625764 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 300 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24254 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.800445 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 15.789474 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 81179 # number of writebacks +system.cpu1.dcache.writebacks::total 81179 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 142547 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 142547 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 235954 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 235954 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 779 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 779 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 378501 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 378501 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 378501 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 378501 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 89272 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 89272 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 46469 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 46469 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4299 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4299 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2912 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2912 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 135741 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 135741 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 135741 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 135741 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 182 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 182 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3016 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3016 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3198 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3198 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1142608000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1142608000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1700967690 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1700967690 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38610000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38610000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 13287500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 13287500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2843575690 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2843575690 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2843575690 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2843575690 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 35749500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 35749500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 35749500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 35749500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042563 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042563 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036752 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036752 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099518 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.099518 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.077100 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.077100 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040377 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040377 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12799.175553 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12799.175553 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36604.353225 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36604.353225 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8981.158409 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8981.158409 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4563.015110 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4563.015110 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196425.824176 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196425.824176 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11178.705441 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11178.705441 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 243897 # number of replacements +system.cpu1.icache.tags.tagsinuse 471.203096 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1645008 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 244406 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.730637 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1879506005500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.203096 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920319 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.920319 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 419 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1352346 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1352346 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1084325 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1084325 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1084325 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1084325 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1084325 # number of overall hits -system.cpu1.icache.overall_hits::total 1084325 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 137526 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 137526 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 137526 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 137526 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 137526 # number of overall misses -system.cpu1.icache.overall_misses::total 137526 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1969078999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1969078999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1969078999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1969078999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1969078999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1969078999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1221851 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1221851 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1221851 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1221851 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1221851 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1221851 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112555 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112555 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112555 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14317.867160 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14317.867160 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14317.867160 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14317.867160 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14317.867160 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14317.867160 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2145410 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2145410 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1645008 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1645008 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1645008 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1645008 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1645008 # number of overall hits +system.cpu1.icache.overall_hits::total 1645008 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 255921 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 255921 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 255921 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 255921 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 255921 # number of overall misses +system.cpu1.icache.overall_misses::total 255921 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3476894499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3476894499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3476894499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3476894499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3476894499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3476894499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1900929 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1900929 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1900929 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1900929 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1900929 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1900929 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.134629 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.134629 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.134629 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.134629 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.134629 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.134629 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13585.811633 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13585.811633 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13585.811633 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13585.811633 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 470 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.400000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.368421 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 129926 # number of writebacks -system.cpu1.icache.writebacks::total 129926 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7031 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7031 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7031 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7031 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7031 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7031 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 130495 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 130495 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 130495 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 130495 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 130495 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 130495 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1753458499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1753458499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1753458499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1753458499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1753458499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1753458499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106801 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.106801 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.106801 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13436.978421 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13436.978421 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13436.978421 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 243897 # number of writebacks +system.cpu1.icache.writebacks::total 243897 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11440 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 11440 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 11440 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 11440 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 11440 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 11440 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244481 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 244481 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 244481 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 244481 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 244481 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 244481 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3131245499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3131245499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3131245499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3131245499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3131245499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3131245499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.128611 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.128611 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.128611 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12807.725341 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1556,13 +1564,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7367 # Transaction distribution -system.iobus.trans_dist::ReadResp 7367 # Transaction distribution -system.iobus.trans_dist::WriteReq 53946 # Transaction distribution -system.iobus.trans_dist::WriteResp 53946 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 7374 # Transaction distribution +system.iobus.trans_dist::ReadResp 7374 # Transaction distribution +system.iobus.trans_dist::WriteReq 54571 # Transaction distribution +system.iobus.trans_dist::WriteResp 54571 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1570,12 +1578,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122626 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123890 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1583,74 +1591,74 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 68530 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2730138 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 10859000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2735194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12271500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 821000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 178000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14076000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14105000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6060001 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6057000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216164058 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216200796 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26782000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27409000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41693 # number of replacements -system.iocache.tags.tagsinuse 0.508375 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.499134 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712300354000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.508375 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031773 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031773 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712299837000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.499134 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031196 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031196 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.tags.tag_accesses 375579 # Number of tag accesses +system.iocache.tags.data_accesses 375579 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21862383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21862383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858655675 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858655675 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4880518058 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4880518058 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4880518058 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4880518058 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses +system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses +system.iocache.overall_misses::total 41731 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22562883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22562883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858746913 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858746913 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4881309796 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4881309796 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4881309796 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4881309796 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1659,38 +1667,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126372.156069 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126372.156069 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116929.526256 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116929.526256 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116968.677244 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116968.677244 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116968.677244 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116968.677244 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126049.625698 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126049.625698 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116931.722011 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116931.722011 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116970.832139 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116970.832139 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13212383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13212383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778666661 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778666661 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2791879044 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2791879044 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2791879044 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2791879044 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41731 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1699,463 +1707,452 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76372.156069 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76372.156069 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.031695 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.031695 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5305.017555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6468.149046 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 210.708528 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 37.097733 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.812327 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080948 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.098696 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003215 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995752 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65027 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 238 # 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mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260010 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019567 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250706 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.289464 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014127 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.142329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.161307 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.289464 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014127 # 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mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002247 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001093 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.427024 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.271164 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.405440 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.272862 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019084 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253523 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162131 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162131 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19166.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 36888.888889 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79104.848165 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104314.292075 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81439.691219 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74350.916230 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63857.855060 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84805.714286 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63978.016615 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210417.938115 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183925.824176 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209747.810980 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86721.967560 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10467.323327 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74657.935094 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 850516 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 398567 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 435 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7194 # Transaction distribution -system.membus.trans_dist::ReadResp 297120 # Transaction distribution -system.membus.trans_dist::WriteReq 12394 # Transaction distribution -system.membus.trans_dist::WriteResp 12394 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122579 # Transaction distribution -system.membus.trans_dist::CleanEvict 262673 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5556 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1697 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 7195 # Transaction distribution +system.membus.trans_dist::ReadResp 297176 # Transaction distribution +system.membus.trans_dist::WriteReq 13019 # Transaction distribution +system.membus.trans_dist::WriteResp 13019 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123513 # Transaction distribution +system.membus.trans_dist::CleanEvict 262911 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6111 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4826 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 120271 # Transaction distribution -system.membus.trans_dist::ReadExResp 120125 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289973 # Transaction distribution -system.membus.trans_dist::BadAddressError 47 # Transaction distribution +system.membus.trans_dist::ReadExReq 121549 # Transaction distribution +system.membus.trans_dist::ReadExResp 121146 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 290030 # Transaction distribution +system.membus.trans_dist::BadAddressError 49 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1170427 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1209697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1293130 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68530 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31401600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31470130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1177677 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 98 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1218203 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1301648 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73538 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31530048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31603586 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34128370 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 4361 # Total snoops (count) -system.membus.snoopTraffic 28480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 478637 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001444 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037968 # Request fanout histogram +system.membus.pkt_size::total 34261826 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11676 # Total snoops (count) +system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 484282 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001355 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036780 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 477946 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 691 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 483626 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 656 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 478637 # Request fanout histogram -system.membus.reqLayer0.occupancy 34935499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 484282 # Request fanout histogram +system.membus.reqLayer0.occupancy 36370000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1350989532 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1352579532 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 59500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 62000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2172548749 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2178718000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 925113 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 960113 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5110475 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2554732 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 342217 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1055 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 987 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5113699 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2556514 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 337557 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1071 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7194 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2261145 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12394 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12394 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 911435 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1144537 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 834683 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5633 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1816 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 7449 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302973 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302973 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1145857 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1108145 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3045120 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4050284 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 390880 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 209583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7695867 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 129904512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 135990364 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16664640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6622614 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 289182130 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 363206 # Total snoops (count) -system.toL2Bus.snoopTraffic 6121792 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2928698 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.120181 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.325532 # Request fanout histogram +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2265500 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13019 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13019 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 906543 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1152402 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 825837 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10249 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5740 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15989 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 300358 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 300358 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1153745 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1104612 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 49 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 203 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2726862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3834313 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 401077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7695072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116326272 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128153608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31253696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13151546 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288885122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 379909 # Total snoops (count) +system.toL2Bus.snoopTraffic 6725760 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2940742 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.121053 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.326514 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2577056 87.99% 87.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 351320 12.00% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 312 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 10 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2585068 87.91% 87.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 355364 12.08% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 309 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2928698 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4546181919 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2940742 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4550461413 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 291385 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1524803969 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1365446887 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2026499354 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1921756875 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 197300876 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 368286347 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 108970290 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 208891088 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2187,185 +2184,194 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197565 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 70781 40.59% 40.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.66% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.10% 41.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 20 0.01% 41.78% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101534 58.22% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174393 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69444 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 20 0.01% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69424 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 140946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863377945500 97.69% 97.69% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 65817500 0.00% 97.70% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 580544500 0.03% 97.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 11361000 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 43328343000 2.27% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907364011500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981111 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6504 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 179089 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 63660 40.34% 40.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.42% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.22% 41.64% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 175 0.11% 41.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 91921 58.25% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 157813 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 62631 49.19% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.51% 50.81% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 175 0.14% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 62456 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 127319 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863112245000 97.74% 97.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 65536000 0.00% 97.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577434000 0.03% 97.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 84972500 0.00% 97.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42413276000 2.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1906253463500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983836 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683751 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808209 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.76% 3.76% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.45% 12.21% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.88% 14.08% # number of syscalls executed -system.cpu0.kern.syscall::6 32 15.02% 29.11% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 29.58% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.76% 33.33% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.69% 38.03% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.82% 40.85% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 41.31% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.41% 42.72% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.82% 45.54% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.94% 46.48% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.49% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.41% 63.38% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.69% 68.08% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.69% 72.77% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 73.24% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.82% 76.06% # number of syscalls executed -system.cpu0.kern.syscall::71 21 9.86% 85.92% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.41% 87.32% # number of syscalls executed -system.cpu0.kern.syscall::74 5 2.35% 89.67% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 90.14% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.41% 91.55% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.23% 95.77% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.94% 96.71% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.94% 97.65% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.12% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.94% 99.06% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.94% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 213 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.679453 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.806771 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed +system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed +system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed +system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed +system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed +system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed +system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed +system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 178 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 120 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3815 2.08% 2.15% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed -system.cpu0.kern.callpal::swpipl 167656 91.61% 93.80% # number of callpals executed -system.cpu0.kern.callpal::rdps 6177 3.38% 97.17% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::rti 4658 2.55% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183007 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7158 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1253 # number of protection mode switches +system.cpu0.kern.callpal::wripir 278 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3399 2.05% 2.22% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.25% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151231 91.28% 93.54% # number of callpals executed +system.cpu0.kern.callpal::rdps 5900 3.56% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed +system.cpu0.kern.callpal::rti 4349 2.63% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 165676 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6738 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1253 -system.cpu0.kern.mode_good::user 1253 +system.cpu0.kern.mode_good::kernel 1097 +system.cpu0.kern.mode_good::user 1097 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175049 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162808 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.297943 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905453819000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1901068000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280026 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1904214078500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1672761500 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3816 # number of times the context was actually changed +system.cpu0.kern.swap_context 3400 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2323 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 40320 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10930 33.84% 33.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 5.96% 39.80% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 120 0.37% 40.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 19320 59.82% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 32295 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10890 45.94% 45.94% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 8.12% 54.06% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 120 0.51% 54.57% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10770 45.43% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 23705 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876314481500 98.36% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 564739500 0.03% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 58247500 0.00% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30733817000 1.61% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907671285500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.996340 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2490 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 60423 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18641 37.27% 37.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.85% 41.12% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 278 0.56% 41.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 29176 58.33% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 50020 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 18293 47.50% 47.50% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.00% 52.50% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 278 0.72% 53.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18016 46.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 38512 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1873859043000 98.29% 98.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 564907000 0.03% 98.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 133677500 0.01% 98.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31975089500 1.68% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1906532717000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981331 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.557453 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.734015 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 12 10.62% 10.62% # number of syscalls executed -system.cpu1.kern.syscall::6 10 8.85% 19.47% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.88% 20.35% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.19% 26.55% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.65% 29.20% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.65% 31.86% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.42% 36.28% # number of syscalls executed -system.cpu1.kern.syscall::45 21 18.58% 54.87% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.65% 57.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.88% 58.41% # number of syscalls executed -system.cpu1.kern.syscall::71 33 29.20% 87.61% # number of syscalls executed -system.cpu1.kern.syscall::74 11 9.73% 97.35% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.65% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 113 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.617494 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769932 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed +system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed +system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed +system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed +system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed +system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed +system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed +system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed +system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 148 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 20 0.06% 0.06% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu1.kern.callpal::swpctx 449 1.34% 1.41% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.42% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.44% # number of callpals executed -system.cpu1.kern.callpal::swpipl 27672 82.56% 84.00% # number of callpals executed -system.cpu1.kern.callpal::rdps 2585 7.71% 91.71% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.71% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 91.73% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.74% # number of callpals executed -system.cpu1.kern.callpal::rti 2577 7.69% 99.42% # number of callpals executed -system.cpu1.kern.callpal::callsys 148 0.44% 99.87% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.13% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 175 0.33% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1166 2.23% 2.57% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 2.58% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.59% # number of callpals executed +system.cpu1.kern.callpal::swpipl 44628 85.35% 87.94% # number of callpals executed +system.cpu1.kern.callpal::rdps 2858 5.47% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.42% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed +system.cpu1.kern.callpal::rti 3189 6.10% 99.52% # number of callpals executed +system.cpu1.kern.callpal::callsys 200 0.38% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 33518 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 911 # number of protection mode switches -system.cpu1.kern.mode_switch::user 493 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2088 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 538 -system.cpu1.kern.mode_good::user 493 -system.cpu1.kern.mode_good::idle 45 -system.cpu1.kern.mode_switch_good::kernel 0.590560 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 52290 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1624 # number of protection mode switches +system.cpu1.kern.mode_switch::user 640 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2399 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 844 +system.cpu1.kern.mode_good::user 640 +system.cpu1.kern.mode_good::idle 204 +system.cpu1.kern.mode_switch_good::kernel 0.519704 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.021552 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.308133 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2257888000 0.12% 0.12% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 790670500 0.04% 0.16% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1904622719000 99.84% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 450 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.085035 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.361999 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4862135000 0.26% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1013458000 0.05% 0.31% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1900657116000 99.69% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1167 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 39a06dc53..f5019500b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.876794 # Number of seconds simulated -sim_ticks 1876794488000 # Number of ticks simulated -final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.862042 # Number of seconds simulated +sim_ticks 1862042063000 # Number of ticks simulated +final_tick 1862042063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152079 # Simulator instruction rate (inst/s) -host_op_rate 152079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5387044029 # Simulator tick rate (ticks/s) -host_mem_usage 330796 # Number of bytes of host memory used -host_seconds 348.39 # Real time elapsed on the host -sim_insts 52982943 # Number of instructions simulated -sim_ops 52982943 # Number of ops (including micro ops) simulated +host_inst_rate 137297 # Simulator instruction rate (inst/s) +host_op_rate 137297 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4825772422 # Simulator tick rate (ticks/s) +host_mem_usage 338492 # Number of bytes of host memory used +host_seconds 385.85 # Real time elapsed on the host +sim_insts 52976505 # Number of instructions simulated +sim_ops 52976505 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 963392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881792 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory -system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25846144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7528832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7528832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15053 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388778 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403799 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117620 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117620 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 512431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13256885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13769827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4010924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4010924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4010924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13256885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17780751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403799 # Number of read requests accepted -system.physmem.writeReqs 117620 # Number of write requests accepted -system.physmem.readBursts 403799 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117620 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25835776 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7525824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7527680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 403846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117638 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117638 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13362637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13880537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043320 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043320 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13362637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17923857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403846 # Number of read requests accepted +system.physmem.writeReqs 117638 # Number of write requests accepted +system.physmem.readBursts 403846 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117638 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25839232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue +system.physmem.bytesWritten 7527104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25846144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7528832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25625 # Per bank write bursts -system.physmem.perBankRdBursts::1 25421 # Per bank write bursts -system.physmem.perBankRdBursts::2 25559 # Per bank write bursts -system.physmem.perBankRdBursts::3 25464 # Per bank write bursts -system.physmem.perBankRdBursts::4 25431 # Per bank write bursts -system.physmem.perBankRdBursts::5 24732 # Per bank write bursts -system.physmem.perBankRdBursts::6 24935 # Per bank write bursts -system.physmem.perBankRdBursts::7 25090 # Per bank write bursts -system.physmem.perBankRdBursts::8 24946 # Per bank write bursts -system.physmem.perBankRdBursts::9 25020 # Per bank write bursts -system.physmem.perBankRdBursts::10 25560 # Per bank write bursts -system.physmem.perBankRdBursts::11 24886 # Per bank write bursts -system.physmem.perBankRdBursts::12 24460 # Per bank write bursts -system.physmem.perBankRdBursts::13 25266 # Per bank write bursts -system.physmem.perBankRdBursts::14 25703 # Per bank write bursts -system.physmem.perBankRdBursts::15 25586 # Per bank write bursts -system.physmem.perBankWrBursts::0 7949 # Per bank write bursts -system.physmem.perBankWrBursts::1 7513 # Per bank write bursts -system.physmem.perBankWrBursts::2 7969 # Per bank write bursts -system.physmem.perBankWrBursts::3 7485 # Per bank write bursts -system.physmem.perBankWrBursts::4 7367 # Per bank write bursts -system.physmem.perBankWrBursts::5 6667 # Per bank write bursts -system.physmem.perBankWrBursts::6 6767 # Per bank write bursts -system.physmem.perBankWrBursts::7 6715 # Per bank write bursts -system.physmem.perBankWrBursts::8 7150 # Per bank write bursts -system.physmem.perBankWrBursts::9 6697 # Per bank write bursts -system.physmem.perBankWrBursts::10 7421 # Per bank write bursts -system.physmem.perBankWrBursts::11 6978 # Per bank write bursts -system.physmem.perBankWrBursts::12 7150 # Per bank write bursts -system.physmem.perBankWrBursts::13 7899 # Per bank write bursts -system.physmem.perBankWrBursts::14 8060 # Per bank write bursts -system.physmem.perBankWrBursts::15 7804 # Per bank write bursts +system.physmem.perBankRdBursts::0 25618 # Per bank write bursts +system.physmem.perBankRdBursts::1 25426 # Per bank write bursts +system.physmem.perBankRdBursts::2 25537 # Per bank write bursts +system.physmem.perBankRdBursts::3 25512 # Per bank write bursts +system.physmem.perBankRdBursts::4 25419 # Per bank write bursts +system.physmem.perBankRdBursts::5 24740 # Per bank write bursts +system.physmem.perBankRdBursts::6 24937 # Per bank write bursts +system.physmem.perBankRdBursts::7 25096 # Per bank write bursts +system.physmem.perBankRdBursts::8 24930 # Per bank write bursts +system.physmem.perBankRdBursts::9 25035 # Per bank write bursts +system.physmem.perBankRdBursts::10 25569 # Per bank write bursts +system.physmem.perBankRdBursts::11 24892 # Per bank write bursts +system.physmem.perBankRdBursts::12 24450 # Per bank write bursts +system.physmem.perBankRdBursts::13 25273 # Per bank write bursts +system.physmem.perBankRdBursts::14 25713 # Per bank write bursts +system.physmem.perBankRdBursts::15 25591 # Per bank write bursts +system.physmem.perBankWrBursts::0 7930 # Per bank write bursts +system.physmem.perBankWrBursts::1 7514 # Per bank write bursts +system.physmem.perBankWrBursts::2 7945 # Per bank write bursts +system.physmem.perBankWrBursts::3 7523 # Per bank write bursts +system.physmem.perBankWrBursts::4 7351 # Per bank write bursts +system.physmem.perBankWrBursts::5 6673 # Per bank write bursts +system.physmem.perBankWrBursts::6 6769 # Per bank write bursts +system.physmem.perBankWrBursts::7 6726 # Per bank write bursts +system.physmem.perBankWrBursts::8 7138 # Per bank write bursts +system.physmem.perBankWrBursts::9 6708 # Per bank write bursts +system.physmem.perBankWrBursts::10 7428 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 7147 # Per bank write bursts +system.physmem.perBankWrBursts::13 7895 # Per bank write bursts +system.physmem.perBankWrBursts::14 8063 # Per bank write bursts +system.physmem.perBankWrBursts::15 7810 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 1876789160500 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1862036687500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403799 # Read request sizes (log2) +system.physmem.readPktSize::6 403846 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117620 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 35764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -149,192 +149,195 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.886657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.247155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 411.697741 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13677 22.01% 22.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10478 16.86% 38.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4968 7.99% 46.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2775 4.47% 51.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2441 3.93% 55.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1588 2.56% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3776 6.08% 63.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1174 1.89% 65.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21262 34.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62139 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5217 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.374545 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2903.927058 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5214 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 541.558358 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 333.246769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.180517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13396 21.74% 21.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10505 17.05% 38.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5359 8.70% 47.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2621 4.25% 51.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2461 3.99% 55.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1425 2.31% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1507 2.45% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1351 2.19% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22986 37.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61611 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5236 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.104660 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2917.579007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5233 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5217 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5217 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.539965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.244136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.635763 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4619 88.54% 88.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 29 0.56% 89.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 25 0.48% 89.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 38 0.73% 90.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 214 4.10% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 9 0.17% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.21% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 34 0.65% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 184 3.53% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.10% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.10% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.08% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.12% 99.35% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5236 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.461994 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.033018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.013556 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4631 88.45% 88.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 42 0.80% 89.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 243 4.64% 93.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 21 0.40% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 6 0.11% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 10 0.19% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 6 0.11% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 20 0.38% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 23 0.44% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 185 3.53% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 2 0.04% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 3 0.06% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.13% 99.35% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-151 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.15% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.12% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5217 # Writes before turning the bus around for reads -system.physmem.totQLat 4201005000 # Total ticks spent queuing -system.physmem.totMemAccLat 11770080000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10406.67 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 11 0.21% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5236 # Writes before turning the bus around for reads +system.physmem.totQLat 3726058000 # Total ticks spent queuing +system.physmem.totMemAccLat 11296145500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9228.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29156.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27978.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing -system.physmem.readRowHits 363845 # Number of row buffer hits during reads -system.physmem.writeRowHits 95291 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.13 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes -system.physmem.avgGap 3599387.75 # Average gap between requests -system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233399880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127351125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577604600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378639360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61740410985 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1071915840750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1258556040540 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.589641 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1783024934000 # Time in different power states -system.physmem_0.memoryStateTime::REF 62670140000 # Time in different power states +system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing +system.physmem.readRowHits 364089 # Number of row buffer hits during reads +system.physmem.writeRowHits 95648 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.31 # Row buffer hit rate for writes +system.physmem.avgGap 3570649.70 # Average gap between requests +system.physmem.pageHitRate 88.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230882400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125977500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577823000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378632880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56327619735 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067810937000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1248070945155 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.272471 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1776230272500 # Time in different power states +system.physmem_0.memoryStateTime::REF 62177440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31095099750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23627517500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 236370960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128972250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571130600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383350320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61477234290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.573928 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states -system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states +system.physmem_1.actEnergy 234896760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128167875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571286600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383486400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 56258103960 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067871924000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1248066938235 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.270314 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1776335363750 # Time in different power states +system.physmem_1.memoryStateTime::REF 62177440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23523591750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19569408 # Number of BP lookups -system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 19539848 # Number of BP lookups +system.cpu.branchPred.condPredicted 16614646 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 591620 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12579114 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5416634 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42865 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6372302 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563108 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5809194 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 264983 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 43.060537 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1121926 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41569 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6087322 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 563395 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5523927 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 264320 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11131372 # DTB read hits -system.cpu.dtb.read_misses 49301 # DTB read misses -system.cpu.dtb.read_acv 623 # DTB read access violations -system.cpu.dtb.read_accesses 996761 # DTB read accesses -system.cpu.dtb.write_hits 6776847 # DTB write hits -system.cpu.dtb.write_misses 12217 # DTB write misses -system.cpu.dtb.write_acv 418 # DTB write access violations -system.cpu.dtb.write_accesses 345142 # DTB write accesses -system.cpu.dtb.data_hits 17908219 # DTB hits -system.cpu.dtb.data_misses 61518 # DTB misses -system.cpu.dtb.data_acv 1041 # DTB access violations -system.cpu.dtb.data_accesses 1341903 # DTB accesses -system.cpu.itb.fetch_hits 1817383 # ITB hits -system.cpu.itb.fetch_misses 10321 # ITB misses -system.cpu.itb.fetch_acv 767 # ITB acv -system.cpu.itb.fetch_accesses 1827704 # ITB accesses +system.cpu.dtb.read_hits 11126873 # DTB read hits +system.cpu.dtb.read_misses 49288 # DTB read misses +system.cpu.dtb.read_acv 612 # DTB read access violations +system.cpu.dtb.read_accesses 995471 # DTB read accesses +system.cpu.dtb.write_hits 6773971 # DTB write hits +system.cpu.dtb.write_misses 12183 # DTB write misses +system.cpu.dtb.write_acv 423 # DTB write access violations +system.cpu.dtb.write_accesses 345274 # DTB write accesses +system.cpu.dtb.data_hits 17900844 # DTB hits +system.cpu.dtb.data_misses 61471 # DTB misses +system.cpu.dtb.data_acv 1035 # DTB access violations +system.cpu.dtb.data_accesses 1340745 # DTB accesses +system.cpu.itb.fetch_hits 1815480 # ITB hits +system.cpu.itb.fetch_misses 10441 # ITB misses +system.cpu.itb.fetch_acv 750 # ITB acv +system.cpu.itb.fetch_accesses 1825921 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -347,148 +350,148 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12876 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12878 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279534848.967231 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439378966.267034 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 96000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 155167561 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 62117170500 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1799924892500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 124240781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1681668 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 87 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 207083 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 421165 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 751 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9930605 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 406777 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 30188704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85612379 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19539848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7101955 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 86725868 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1678156 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207275 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 432547 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9909625 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 405389 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 148422395 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.577690 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.864310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 118425370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.722923 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.060283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132578342 89.33% 89.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1033201 0.70% 90.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2106811 1.42% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971505 0.65% 92.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2908700 1.96% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 663530 0.45% 94.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 808471 0.54% 95.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1037122 0.70% 95.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6314713 4.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102607090 86.64% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1029926 0.87% 87.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2106958 1.78% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 967243 0.82% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2899427 2.45% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 665654 0.56% 93.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 809857 0.68% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1032032 0.87% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6307183 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148422395 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126118 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.552578 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24118440 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 111208587 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10245196 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2044112 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806059 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 738327 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35573 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 74062953 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 114064 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806059 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25129468 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 79314805 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20217508 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11209636 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11744917 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 71031430 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 202187 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2134257 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 304114 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7385918 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47856784 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85577316 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85396639 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168224 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38182032 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9674744 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1729903 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 277398 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13945265 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11667584 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7222268 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1740236 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1128330 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62719117 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2208284 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60532785 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94680 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11944453 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5319004 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1547012 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148422395 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.407841 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.141989 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 118425370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.157274 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.689084 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24239485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 81100635 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10246732 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2034421 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 804096 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 734883 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 35786 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 73972445 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 113808 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 804096 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25248689 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52456334 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19565246 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11202200 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9148803 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 70966243 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 196842 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2117370 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 228092 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4881037 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47806174 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85505184 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85324382 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168350 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38176913 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9629253 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1728484 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 276268 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13926032 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11656323 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7221031 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1724354 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1093863 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62666856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2206869 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60507866 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 96262 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11897215 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5284366 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1545682 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 118425370 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.510937 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.257755 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 123871811 83.46% 83.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10428219 7.03% 90.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4419616 2.98% 93.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3188761 2.15% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3243069 2.19% 97.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1605515 1.08% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1096686 0.74% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 430660 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 138058 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93896241 79.29% 79.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10410761 8.79% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4424184 3.74% 91.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3178503 2.68% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3240709 2.74% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1606797 1.36% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1097474 0.93% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 434045 0.37% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136656 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148422395 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 118425370 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206261 16.62% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 637065 51.34% 67.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 397617 32.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206587 16.63% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 638209 51.38% 68.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 397270 31.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7280 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40910867 67.58% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62087 0.10% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7277 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40893641 67.58% 67.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62155 0.10% 67.70% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38559 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38558 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued @@ -514,95 +517,95 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11677582 19.29% 87.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6883616 11.37% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949158 1.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11671611 19.29% 87.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6881999 11.37% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948989 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60532785 # Type of FU issued -system.cpu.iq.rate 0.390112 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1240943 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020500 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 270086631 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76534291 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58304379 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 736956 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359180 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336827 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61370896 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 395552 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 686477 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60507866 # Type of FU issued +system.cpu.iq.rate 0.487021 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1242066 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020527 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 240042364 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76433076 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58286910 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 737065 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359346 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336745 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61347086 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 395569 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 690461 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2574541 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4210 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22293 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 843973 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2564224 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 22069 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 843181 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18024 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 466103 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17987 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 463704 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806059 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 75493298 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1202730 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68906340 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 204916 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11667584 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7222268 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1958885 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 46577 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 953145 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22293 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 228745 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 630471 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 859216 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59676170 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11213777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 856614 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 804096 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 49123510 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 920451 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68850753 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 204809 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11656323 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7221031 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1958834 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45972 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 671584 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 22069 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 229357 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 628132 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 857489 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59656852 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11208773 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 851013 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3978939 # number of nop insts executed -system.cpu.iew.exec_refs 18023142 # number of memory reference insts executed -system.cpu.iew.exec_branches 9384066 # Number of branches executed -system.cpu.iew.exec_stores 6809365 # Number of stores executed -system.cpu.iew.exec_rate 0.384592 # Inst execution rate -system.cpu.iew.wb_sent 58885265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58641206 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29760600 # num instructions producing a value -system.cpu.iew.wb_consumers 41260135 # num instructions consuming a value -system.cpu.iew.wb_rate 0.377922 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721292 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12542077 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661272 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 769434 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146251910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.384089 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.283290 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3977028 # number of nop insts executed +system.cpu.iew.exec_refs 18015122 # number of memory reference insts executed +system.cpu.iew.exec_branches 9379233 # Number of branches executed +system.cpu.iew.exec_stores 6806349 # Number of stores executed +system.cpu.iew.exec_rate 0.480171 # Inst execution rate +system.cpu.iew.wb_sent 58867691 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58623655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29756177 # num instructions producing a value +system.cpu.iew.wb_consumers 41250197 # num instructions consuming a value +system.cpu.iew.wb_rate 0.471855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721358 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12492004 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661187 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 767634 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 116265516 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.483093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.421972 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 126403677 86.43% 86.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7969213 5.45% 91.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4187918 2.86% 94.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2256490 1.54% 96.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1756984 1.20% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 633259 0.43% 97.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 482491 0.33% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 524954 0.36% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2036924 1.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 96403146 82.92% 82.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7978599 6.86% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4192375 3.61% 93.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2264506 1.95% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1757271 1.51% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 632678 0.54% 97.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 482043 0.41% 97.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 513720 0.44% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2041178 1.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146251910 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56173766 # Number of instructions committed -system.cpu.commit.committedOps 56173766 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 116265516 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56167063 # Number of instructions committed +system.cpu.commit.committedOps 56167063 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471338 # Number of memory references committed -system.cpu.commit.loads 9093043 # Number of loads committed -system.cpu.commit.membars 226379 # Number of memory barriers committed -system.cpu.commit.branches 8441154 # Number of branches committed +system.cpu.commit.refs 15469949 # Number of memory references committed +system.cpu.commit.loads 9092099 # Number of loads committed +system.cpu.commit.membars 226348 # Number of memory barriers committed +system.cpu.commit.branches 8440307 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52023017 # Number of committed integer instructions. -system.cpu.commit.function_calls 740601 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198096 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36220454 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52016709 # Number of committed integer instructions. +system.cpu.commit.function_calls 740521 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197831 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36215597 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60674 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -630,554 +633,544 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319422 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384252 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949158 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318447 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383804 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948989 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56173766 # Class of committed instruction -system.cpu.commit.bw_lim_events 2036924 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 212681294 # The number of ROB reads -system.cpu.rob.rob_writes 139606986 # The number of ROB writes -system.cpu.timesIdled 557347 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6745166 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598421416 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52982943 # Number of Instructions Simulated -system.cpu.committedOps 52982943 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.928632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.928632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77864960 # number of integer regfile reads -system.cpu.int_regfile_writes 42584488 # number of integer regfile writes -system.cpu.fp_regfile_reads 166613 # number of floating regfile reads -system.cpu.fp_regfile_writes 175794 # number of floating regfile writes -system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads -system.cpu.misc_regfile_writes 939529 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405900 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 56167063 # Class of committed instruction +system.cpu.commit.bw_lim_events 2041178 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 182633884 # The number of ROB reads +system.cpu.rob.rob_writes 139481914 # The number of ROB writes +system.cpu.timesIdled 555871 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5815411 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599843346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52976505 # Number of Instructions Simulated +system.cpu.committedOps 52976505 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.345205 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.345205 # CPI: Total CPI of All Threads +system.cpu.ipc 0.426402 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.426402 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77842014 # number of integer regfile reads +system.cpu.int_regfile_writes 42572961 # number of integer regfile writes +system.cpu.fp_regfile_reads 166584 # number of floating regfile reads +system.cpu.fp_regfile_writes 175742 # number of floating regfile writes +system.cpu.misc_regfile_reads 2001057 # number of misc regfile reads +system.cpu.misc_regfile_writes 939419 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1405448 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994324 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12624146 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1405960 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.979022 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26885500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994324 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12199345 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12199345 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12199345 # number of overall hits -system.cpu.dcache.overall_hits::total 12199345 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1817411 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1817411 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1966241 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1966241 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23192 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23192 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 96 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 96 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3783652 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3783652 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3783652 # number of overall misses -system.cpu.dcache.overall_misses::total 3783652 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57696836500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57696836500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116764719993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116764719993 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 411714000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 411714000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1875000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1875000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 174461556493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 174461556493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 174461556493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 174461556493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9835178 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9835178 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147819 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147819 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235666 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235666 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215771 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215771 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15982997 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15982997 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15982997 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15982997 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184787 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184787 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319827 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319827 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098410 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098410 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000445 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000445 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236730 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236730 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46109.302994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46109.302994 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7149027 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133846 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks -system.cpu.dcache.writebacks::total 843569 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717041 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676919 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1676919 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6351 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6351 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2393960 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2393960 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2393960 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2393960 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100370 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1100370 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289322 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289322 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16841 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16841 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 96 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 96 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389692 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389692 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389692 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389692 # number of overall MSHR misses +system.cpu.dcache.tags.tag_accesses 67117469 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67117469 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 8015814 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8015814 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4179783 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4179783 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 212605 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 212605 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215671 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215671 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 12195597 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 12195597 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 12195597 # number of overall hits +system.cpu.dcache.overall_hits::total 12195597 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1813103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1813103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1967603 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1967603 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23208 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23208 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 90 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 90 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3780706 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3780706 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3780706 # number of overall misses +system.cpu.dcache.overall_misses::total 3780706 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 42125006500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 42125006500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80961387023 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80961387023 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 351774000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 351774000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1258000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 1258000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 123086393523 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 123086393523 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 123086393523 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 123086393523 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9828917 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9828917 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235813 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 235813 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215761 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215761 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15976303 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15976303 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15976303 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15976303 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184466 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184466 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320071 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.320071 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098417 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098417 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000417 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000417 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.236645 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.236645 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.236645 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.236645 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23233.653300 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23233.653300 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41147.216701 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41147.216701 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15157.445708 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15157.445708 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13977.777778 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13977.777778 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32556.457319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32556.457319 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4549830 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3359 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133574 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.062243 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 93.305556 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 843871 # number of writebacks +system.cpu.dcache.writebacks::total 843871 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 713283 # 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mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086948 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1074186 # number of replacements -system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30901101000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30901101000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12647974805 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12647974805 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 208768500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 208768500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43549075805 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43549075805 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43549075805 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43549075805 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535163500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535163500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535163500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535163500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111896 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111896 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047104 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047104 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.070819 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.070819 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000417 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000417 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.086965 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.086965 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28096.507610 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28096.507610 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43679.225062 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43679.225062 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12501.107784 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12501.107784 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12977.777778 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12977.777778 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31344.138453 # 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number of replacements +system.cpu.icache.tags.tagsinuse 509.176961 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8765751 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1075522 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.150229 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28399256500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.176961 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits -system.cpu.icache.overall_hits::total 8786985 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9930600 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9930600 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9930600 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9930600 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9930600 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9930600 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115161 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115161 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115161 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115161 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115161 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115161 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14866.496136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14866.496136 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 12933 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10985459 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10985459 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 8765751 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8765751 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8765751 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8765751 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8765751 # number of overall hits +system.cpu.icache.overall_hits::total 8765751 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1143868 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1143868 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1143868 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1143868 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1143868 # number of overall misses +system.cpu.icache.overall_misses::total 1143868 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15979138992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15979138992 # 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number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 307500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 307500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9179285500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9179285500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1123478500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1123478500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17540240000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17540240000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1123478500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26719525500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27843004000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1123478500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26719525500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27843004000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448524000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448524000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448524000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448524000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097561 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097561 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382246 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382246 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013998 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248230 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248230 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.162919 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.162919 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 38437.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 38437.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80029.342017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80029.342017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74629.899030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74629.899030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63892.586157 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63892.586157 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209022.222222 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209022.222222 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87640.609874 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87640.609874 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4962480 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480820 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 950 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 96 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 299827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 299827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3223811 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252378 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7476189 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137523904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144052988 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 281576892 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422541 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7562240 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2920171 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001264 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.035530 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 2188821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 919997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1075014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 824089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 90 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 172 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 300066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 254 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3226322 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4251016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7477338 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137630848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144043380 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 281674228 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 339580 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4905856 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2837598 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001208 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.034736 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2916480 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3691 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2834170 99.88% 99.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3428 0.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2920171 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4411678000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2837598 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4413188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613546403 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1614811393 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121618679 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121037981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1191,12 +1184,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51151 # Transaction distribution -system.iobus.trans_dist::WriteResp 51151 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51150 # Transaction distribution +system.iobus.trans_dist::WriteResp 51150 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1205,11 +1198,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1218,50 +1211,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5364000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5361000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14181000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14040000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2177500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6052000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6050500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216173801 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.258860 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712294555000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.258860 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078679 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078679 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1270,14 +1263,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21845883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21845883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858784918 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858784918 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4880630801 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4880630801 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4880630801 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4880630801 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1294,19 +1287,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126276.780347 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126276.780347 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116932.636648 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116932.636648 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116971.379293 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116971.379293 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1318,14 +1311,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13195883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13195883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778792164 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2778792164 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2791988047 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2791988047 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2791988047 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2791988047 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1334,70 +1327,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76276.780347 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76276.780347 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66875.052079 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66875.052079 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 825555 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 380464 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296606 # Transaction distribution -system.membus.trans_dist::WriteReq 9599 # Transaction distribution -system.membus.trans_dist::WriteResp 9599 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution -system.membus.trans_dist::CleanEvict 261864 # Transaction distribution -system.membus.trans_dist::UpgradeReq 278 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.membus.trans_dist::ReadResp 296639 # Transaction distribution +system.membus.trans_dist::WriteReq 9598 # Transaction distribution +system.membus.trans_dist::WriteResp 9598 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117638 # Transaction distribution +system.membus.trans_dist::CleanEvict 261892 # Transaction distribution +system.membus.trans_dist::UpgradeReq 135 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114558 # Transaction distribution -system.membus.trans_dist::ReadExResp 114558 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289719 # Transaction distribution -system.membus.trans_dist::BadAddressError 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 114572 # Transaction distribution +system.membus.trans_dist::ReadExResp 114572 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289754 # Transaction distribution +system.membus.trans_dist::BadAddressError 45 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 86 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179065 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262499 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30713088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1262490 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30717248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30761396 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33414972 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33419124 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 438 # Total snoops (count) system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 842137 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 462541 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001500 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038706 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842137 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 461847 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 694 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842137 # Request fanout histogram -system.membus.reqLayer0.occupancy 28883000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 462541 # Request fanout histogram +system.membus.reqLayer0.occupancy 28740000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314155780 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 57000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139053000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1429,52 +1427,52 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210996 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74658 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105584 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182266 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105558 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182227 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73291 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818987792000 96.92% 96.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67503500 0.00% 96.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 563118000 0.03% 96.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57175249500 3.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1876793663000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73291 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148593 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818067214500 97.64% 97.64% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67498000 0.00% 97.64% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 564111500 0.03% 97.67% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 43342412500 2.33% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1862041236500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981690 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694262 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815391 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694320 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815428 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1513,29 +1511,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175147 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175110 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191994 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5854 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.callpal::total 191955 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326273 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 30164955000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2918722500 0.16% 1.76% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843709977500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29461996000 1.58% 1.58% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2701361000 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829877871500 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index d7da6ec5c..848d1d5ab 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841599 # Number of seconds simulated -sim_ticks 1841599161000 # Number of ticks simulated -final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842573 # Number of seconds simulated +sim_ticks 1842573194000 # Number of ticks simulated +final_tick 1842573194000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220916 # Simulator instruction rate (inst/s) -host_op_rate 220916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6097623299 # Simulator tick rate (ticks/s) -host_mem_usage 332848 # Number of bytes of host memory used -host_seconds 302.02 # Real time elapsed on the host -sim_insts 66720805 # Number of instructions simulated -sim_ops 66720805 # Number of ops (including micro ops) simulated +host_inst_rate 206946 # Simulator instruction rate (inst/s) +host_op_rate 206946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5715573944 # Simulator tick rate (ticks/s) +host_mem_usage 339016 # Number of bytes of host memory used +host_seconds 322.38 # Real time elapsed on the host +sim_insts 66714903 # Number of instructions simulated +sim_ops 66714903 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 472448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20115392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2145088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 298752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2611904 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 469248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20132864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 150208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2123008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 298368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2617024 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25791552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 472448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 298752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7488832 # Number of bytes written to this memory -system.physmem.bytes_written::total 7488832 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7382 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 40811 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25791680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 469248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 298368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 917824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7488960 # Number of bytes written to this memory +system.physmem.bytes_written::total 7488960 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7332 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 40891 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402993 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117013 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117013 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 256542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10922785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1164796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 162224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1418280 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402995 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117015 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117015 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 254670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10926493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1152197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 161930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1420309 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14004976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 256542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 162224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4066483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4066483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4066483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 256542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10922785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1164796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 162224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1418280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13997642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 254670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 161930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4064403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4064403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4064403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 254670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10926493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 81521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1152197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 161930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1420309 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18071459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81308 # Number of read requests accepted -system.physmem.writeReqs 46917 # Number of write requests accepted -system.physmem.readBursts 81308 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 46917 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5202560 # Total number of bytes read from DRAM +system.physmem.bw_total::total 18062045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81087 # Number of read requests accepted +system.physmem.writeReqs 46731 # Number of write requests accepted +system.physmem.readBursts 81087 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 46731 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5188416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue -system.physmem.bytesWritten 3000896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5203712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3002688 # Total written bytes from the system interface side +system.physmem.bytesWritten 2989056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5189568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2990784 # Total written bytes from the system interface side system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4879 # Per bank write bursts -system.physmem.perBankRdBursts::1 4860 # Per bank write bursts -system.physmem.perBankRdBursts::2 4840 # Per bank write bursts -system.physmem.perBankRdBursts::3 5116 # Per bank write bursts -system.physmem.perBankRdBursts::4 5145 # Per bank write bursts -system.physmem.perBankRdBursts::5 5201 # Per bank write bursts -system.physmem.perBankRdBursts::6 5134 # Per bank write bursts -system.physmem.perBankRdBursts::7 5033 # Per bank write bursts -system.physmem.perBankRdBursts::8 5242 # Per bank write bursts -system.physmem.perBankRdBursts::9 4887 # Per bank write bursts -system.physmem.perBankRdBursts::10 5474 # Per bank write bursts -system.physmem.perBankRdBursts::11 5136 # Per bank write bursts -system.physmem.perBankRdBursts::12 4904 # Per bank write bursts -system.physmem.perBankRdBursts::13 4973 # Per bank write bursts +system.physmem.perBankRdBursts::0 4742 # Per bank write bursts +system.physmem.perBankRdBursts::1 4753 # Per bank write bursts +system.physmem.perBankRdBursts::2 4837 # Per bank write bursts +system.physmem.perBankRdBursts::3 5252 # Per bank write bursts +system.physmem.perBankRdBursts::4 5163 # Per bank write bursts +system.physmem.perBankRdBursts::5 5213 # Per bank write bursts +system.physmem.perBankRdBursts::6 5141 # Per bank write bursts +system.physmem.perBankRdBursts::7 5015 # Per bank write bursts +system.physmem.perBankRdBursts::8 5238 # Per bank write bursts +system.physmem.perBankRdBursts::9 4880 # Per bank write bursts +system.physmem.perBankRdBursts::10 5475 # Per bank write bursts +system.physmem.perBankRdBursts::11 5008 # Per bank write bursts +system.physmem.perBankRdBursts::12 4911 # Per bank write bursts +system.physmem.perBankRdBursts::13 4972 # Per bank write bursts system.physmem.perBankRdBursts::14 5564 # Per bank write bursts -system.physmem.perBankRdBursts::15 4902 # Per bank write bursts -system.physmem.perBankWrBursts::0 2770 # Per bank write bursts -system.physmem.perBankWrBursts::1 2825 # Per bank write bursts -system.physmem.perBankWrBursts::2 2866 # Per bank write bursts -system.physmem.perBankWrBursts::3 3058 # Per bank write bursts -system.physmem.perBankWrBursts::4 2994 # Per bank write bursts -system.physmem.perBankWrBursts::5 2828 # Per bank write bursts -system.physmem.perBankWrBursts::6 3105 # Per bank write bursts -system.physmem.perBankWrBursts::7 2723 # Per bank write bursts -system.physmem.perBankWrBursts::8 3290 # Per bank write bursts -system.physmem.perBankWrBursts::9 2741 # Per bank write bursts +system.physmem.perBankRdBursts::15 4905 # Per bank write bursts +system.physmem.perBankWrBursts::0 2655 # Per bank write bursts +system.physmem.perBankWrBursts::1 2725 # Per bank write bursts +system.physmem.perBankWrBursts::2 2864 # Per bank write bursts +system.physmem.perBankWrBursts::3 3189 # Per bank write bursts +system.physmem.perBankWrBursts::4 3009 # Per bank write bursts +system.physmem.perBankWrBursts::5 2838 # Per bank write bursts +system.physmem.perBankWrBursts::6 3113 # Per bank write bursts +system.physmem.perBankWrBursts::7 2705 # Per bank write bursts +system.physmem.perBankWrBursts::8 3288 # Per bank write bursts +system.physmem.perBankWrBursts::9 2746 # Per bank write bursts system.physmem.perBankWrBursts::10 3262 # Per bank write bursts -system.physmem.perBankWrBursts::11 2912 # Per bank write bursts -system.physmem.perBankWrBursts::12 2689 # Per bank write bursts -system.physmem.perBankWrBursts::13 2734 # Per bank write bursts -system.physmem.perBankWrBursts::14 3349 # Per bank write bursts -system.physmem.perBankWrBursts::15 2743 # Per bank write bursts +system.physmem.perBankWrBursts::11 2782 # Per bank write bursts +system.physmem.perBankWrBursts::12 2699 # Per bank write bursts +system.physmem.perBankWrBursts::13 2735 # Per bank write bursts +system.physmem.perBankWrBursts::14 3348 # Per bank write bursts +system.physmem.perBankWrBursts::15 2746 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 1840587284000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 1841561317000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81308 # Read request sizes (log2) +system.physmem.readPktSize::6 81087 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 46917 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 63682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.writePktSize::6 46731 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -154,14 +154,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see @@ -169,191 +169,189 @@ system.physmem.wrQLenPdf::11 36 # Wh system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1705 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.368110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.960357 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 378.240859 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7179 33.20% 33.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4878 22.56% 55.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1948 9.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1045 4.83% 69.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 873 4.04% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 450 2.08% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 417 1.93% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 373 1.72% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4461 20.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21624 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 39.666179 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 981.071588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2047 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.808047 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.054900 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 378.494212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7105 33.09% 33.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4792 22.32% 55.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1974 9.19% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1058 4.93% 69.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 851 3.96% 73.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 468 2.18% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 396 1.84% 77.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 380 1.77% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4450 20.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21474 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2032 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 39.890256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 985.167686 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2030 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.883846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.590123 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.999579 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 33 1.61% 1.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.39% 2.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 2.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 3 0.15% 2.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1695 82.72% 84.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 48 2.34% 87.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.49% 87.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 15 0.73% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 91 4.44% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 8 0.39% 93.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.05% 93.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 4 0.20% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.10% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.15% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.10% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.10% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 2 0.10% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.05% 94.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.10% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.63% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.20% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 77 3.76% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.05% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.10% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.10% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.05% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.10% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.05% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.05% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.20% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2049 # Writes before turning the bus around for reads -system.physmem.totQLat 885699750 # Total ticks spent queuing -system.physmem.totMemAccLat 2409887250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 406450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10895.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2032 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2032 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.984252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.590209 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.991562 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.67% 1.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.34% 2.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.15% 2.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.10% 2.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1678 82.58% 84.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 43 2.12% 86.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 12 0.59% 87.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 18 0.89% 88.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 100 4.92% 93.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.10% 93.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.25% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.15% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.05% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.10% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.05% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.10% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 2 0.10% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.05% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.05% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.34% 94.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.10% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.10% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 82 4.04% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.05% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.10% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.05% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.10% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.10% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.05% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.05% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 7 0.34% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2032 # Writes before turning the bus around for reads +system.physmem.totQLat 878117500 # Total ticks spent queuing +system.physmem.totMemAccLat 2398161250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 405345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10831.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29645.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.83 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29581.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.82 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing -system.physmem.readRowHits 69553 # Number of row buffer hits during reads -system.physmem.writeRowHits 37002 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.87 # Row buffer hit rate for writes -system.physmem.avgGap 14354355.89 # Average gap between requests -system.physmem.pageHitRate 83.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 80733240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 43918875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 313622400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 150135120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35737868835 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 798596823000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 923983654350 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.983586 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1308907007000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45531980000 # Time in different power states +system.physmem.avgWrQLen 7.72 # Average write queue length when enqueuing +system.physmem.readRowHits 69338 # Number of row buffer hits during reads +system.physmem.writeRowHits 36961 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.09 # Row buffer hit rate for writes +system.physmem.avgGap 14407683.71 # Average gap between requests +system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 80173800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 43646625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 312904800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 149675040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89124122880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35767572390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 797968033500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 923446129035 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.080170 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309854007000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45564480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9262769000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9260985250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 82744200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 44962500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 320439600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 153705600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35470252125 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 802756182000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 927888838905 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.649647 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1309307344000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45531980000 # Time in different power states +system.physmem_1.actEnergy 82169640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 44677875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 319433400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 152966880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89124122880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35452017540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 802163554500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 927338942715 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.741345 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1310300112750 # Time in different power states +system.physmem_1.memoryStateTime::REF 45564480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8896844750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8843530000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4808616 # DTB read hits -system.cpu0.dtb.read_misses 6111 # DTB read misses +system.cpu0.dtb.read_hits 4806164 # DTB read hits +system.cpu0.dtb.read_misses 6050 # DTB read misses system.cpu0.dtb.read_acv 122 # DTB read access violations -system.cpu0.dtb.read_accesses 428608 # DTB read accesses -system.cpu0.dtb.write_hits 3411554 # DTB write hits -system.cpu0.dtb.write_misses 685 # DTB write misses +system.cpu0.dtb.read_accesses 427464 # DTB read accesses +system.cpu0.dtb.write_hits 3411517 # DTB write hits +system.cpu0.dtb.write_misses 679 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 164458 # DTB write accesses -system.cpu0.dtb.data_hits 8220170 # DTB hits -system.cpu0.dtb.data_misses 6796 # DTB misses +system.cpu0.dtb.write_accesses 163616 # DTB write accesses +system.cpu0.dtb.data_hits 8217681 # DTB hits +system.cpu0.dtb.data_misses 6729 # DTB misses system.cpu0.dtb.data_acv 206 # DTB access violations -system.cpu0.dtb.data_accesses 593066 # DTB accesses -system.cpu0.itb.fetch_hits 2729287 # ITB hits -system.cpu0.itb.fetch_misses 3056 # ITB misses +system.cpu0.dtb.data_accesses 591080 # DTB accesses +system.cpu0.itb.fetch_hits 2722802 # ITB hits +system.cpu0.itb.fetch_misses 3018 # ITB misses system.cpu0.itb.fetch_acv 101 # ITB acv -system.cpu0.itb.fetch_accesses 2732343 # ITB accesses +system.cpu0.itb.fetch_accesses 2725820 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -366,42 +364,42 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 6508 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 3254 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 553026714.363860 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 1352809149.832599 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 3254 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 213500 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 6514 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 3257 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 552798033.019036 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 1352688826.519808 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 3257 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 142000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 3905515000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 3254 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 42050232460 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1799548928540 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 928788202 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 3257 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 42110000457 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1800463193543 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 928783152 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211368 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6426 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74798 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105692 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73431 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818752965500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39793500 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 370197000 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22435471000 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841598427000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73431 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148944 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819731049500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39465000 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 370305500 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22431640000 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842572460000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694808 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815838 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694764 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815810 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -440,500 +438,498 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192212 # number of callpals executed +system.cpu0.kern.callpal::total 192227 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1906 -system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390854 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29766458500 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2570000000 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809261966500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29732108000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2585852000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810254498000 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4176 # number of times the context was actually changed -system.cpu0.committedInsts 30028359 # Number of instructions committed -system.cpu0.committedOps 30028359 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 27949209 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 163605 # Number of float alu accesses -system.cpu0.num_func_calls 796078 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3573160 # number of instructions that are conditional controls -system.cpu0.num_int_insts 27949209 # number of integer instructions -system.cpu0.num_fp_insts 163605 # number of float instructions -system.cpu0.num_int_register_reads 38472094 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20603467 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84586 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86140 # number of times the floating registers were written -system.cpu0.num_mem_refs 8249833 # number of memory refs -system.cpu0.num_load_insts 4829697 # Number of load instructions -system.cpu0.num_store_insts 3420136 # Number of store instructions -system.cpu0.num_idle_cycles 907169648.432742 # Number of idle cycles -system.cpu0.num_busy_cycles 21618553.567258 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023276 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976724 # Percentage of idle cycles -system.cpu0.Branches 4625246 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1572413 5.24% 5.24% # Class of executed instruction -system.cpu0.op_class::IntAlu 19517057 64.98% 70.22% # Class of executed instruction -system.cpu0.op_class::IntMult 31821 0.11% 70.32% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.32% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12868 0.04% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1602 0.01% 70.37% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::MemRead 4960051 16.51% 86.88% # Class of executed instruction -system.cpu0.op_class::MemWrite 3423231 11.40% 98.28% # Class of executed instruction -system.cpu0.op_class::IprAccess 516318 1.72% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30003730 # Number of instructions committed +system.cpu0.committedOps 30003730 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 27925731 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163756 # Number of float alu accesses +system.cpu0.num_func_calls 796110 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3567009 # number of instructions that are conditional controls +system.cpu0.num_int_insts 27925731 # number of integer instructions +system.cpu0.num_fp_insts 163756 # number of float instructions +system.cpu0.num_int_register_reads 38434691 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20585928 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84641 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86208 # number of times the floating registers were written +system.cpu0.num_mem_refs 8247251 # number of memory refs +system.cpu0.num_load_insts 4827160 # Number of load instructions +system.cpu0.num_store_insts 3420091 # Number of store instructions +system.cpu0.num_idle_cycles 907147772.055444 # Number of idle cycles +system.cpu0.num_busy_cycles 21635379.944556 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023294 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976706 # Percentage of idle cycles +system.cpu0.Branches 4619076 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1571431 5.24% 5.24% # Class of executed instruction +system.cpu0.op_class::IntAlu 19496987 64.97% 70.20% # Class of executed instruction +system.cpu0.op_class::IntMult 31839 0.11% 70.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12846 0.04% 70.35% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1596 0.01% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::MemRead 4957504 16.52% 86.88% # Class of executed instruction +system.cpu0.op_class::MemWrite 3423190 11.41% 98.28% # Class of executed instruction +system.cpu0.op_class::IprAccess 515272 1.72% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30035361 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1394566 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13521910 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1395078 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.692583 # Average number of references to valid blocks. +system.cpu0.op_class::total 30010665 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1394329 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13513290 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1394841 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.688050 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.707457 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 77.564418 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.725941 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503335 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.151493 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345168 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.899506 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 77.334042 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.764270 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503710 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.151043 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345243 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 64423039 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 64423039 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 3984765 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1069804 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2772856 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7827425 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3123452 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 820342 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1358314 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5302108 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113859 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19272 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 59831 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 192962 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122665 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21310 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55350 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199325 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7108217 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1890146 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 4131170 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13129533 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7108217 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1890146 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 4131170 # number of overall hits -system.cpu0.dcache.overall_hits::total 13129533 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 711198 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 95313 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 558903 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1365414 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 164044 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43456 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 643142 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 850642 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9353 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2169 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7565 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19087 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 26 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 875242 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 138769 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1202045 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2216056 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 875242 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 138769 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1202045 # number of overall misses -system.cpu0.dcache.overall_misses::total 2216056 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2254809000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8236813000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10491622000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1752799000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19370305557 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21123104557 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28695000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 118437000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 147132000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 416000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 416000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4007608000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27607118557 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31614726557 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4007608000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27607118557 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31614726557 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4695963 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1165117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3331759 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9192839 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3287496 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 863798 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2001456 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6152750 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123212 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21441 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 67396 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 212049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21310 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55376 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199352 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 7983459 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2028915 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5333215 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15345589 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 7983459 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2028915 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5333215 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15345589 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151449 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081806 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.167750 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.148530 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049899 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050308 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.321337 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.138254 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075910 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101161 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.112247 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090012 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000470 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000135 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109632 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068396 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.225388 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.144410 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109632 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068396 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.225388 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.144410 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23656.888357 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14737.464283 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.839480 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40335.028535 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30118.240695 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24831.955813 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13229.598893 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15655.915400 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7708.492691 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15407.407407 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28879.706563 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22966.792888 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14266.212838 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28879.706563 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22966.792888 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14266.212838 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 997927 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2476 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 58775 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.978766 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 130.315789 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 836681 # number of writebacks -system.cpu0.dcache.writebacks::total 836681 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 289767 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 289767 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548232 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 548232 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69860500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96386500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 390000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 390000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3868839000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7487550240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11356389240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3868839000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7487550240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11356389240 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248693500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 375591500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 624285000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 248693500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 375591500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 624285000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081806 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.080779 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039645 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050308 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047420 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022488 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101161 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.082305 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036388 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000470 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068396 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.068260 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032766 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068396 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.068260 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032766 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22656.888357 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16506.047129 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18114.653902 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39335.028535 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32084.909282 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34361.922293 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12229.598893 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12594.285199 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12491.770347 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27879.706563 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20567.593766 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22585.621431 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27879.706563 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20567.593766 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22585.621431 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219888.152078 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 217860.498840 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218663.747811 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97107.965638 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 99971.120575 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98810.541311 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 969876 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.205246 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39683030 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 970387 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 40.894025 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10200405500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.920563 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.077972 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 184.206711 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.511564 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127105 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.359779 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998448 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1713 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2844 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1429 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2015 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3444 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2560 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3728 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6288 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2154855500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4439209000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6594064500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1679571000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3050724099 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4730295099 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26658500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69598500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96257000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 194000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3834426500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7489933099 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11324359599 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3834426500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7489933099 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11324359599 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248626500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 373633000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 622259500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 248626500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 373633000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 622259500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081506 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.080873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039638 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.049939 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047430 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022440 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100656 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.082460 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036450 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000271 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000075 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068069 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.068314 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032740 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068069 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.068314 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032740 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22668.134145 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16495.951455 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18107.105198 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38909.581615 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32145.030283 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34259.874260 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12228.669725 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12544.790916 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12455.615942 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 12933.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12933.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27740.068872 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20575.947900 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22547.660583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27740.068872 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20575.947900 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22547.660583 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219828.912467 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 218116.170461 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218797.292546 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97119.726562 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 100223.444206 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98959.844148 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 970146 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.204815 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39666884 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 970657 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 40.866015 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10200765500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.084411 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 64.947265 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 183.173139 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.513837 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.126850 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.357760 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998447 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 41646260 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 41646260 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 29526010 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7417850 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2739170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39683030 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29526010 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7417850 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2739170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39683030 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29526010 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7417850 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2739170 # number of overall hits -system.cpu0.icache.overall_hits::total 39683030 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 509351 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 126603 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 356690 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 992644 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 509351 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 126603 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 356690 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 992644 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 509351 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 126603 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 356690 # number of overall misses -system.cpu0.icache.overall_misses::total 992644 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1812461000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4955400483 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6767861483 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1812461000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4955400483 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6767861483 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1812461000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4955400483 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6767861483 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30035361 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7544453 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3095860 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40675674 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30035361 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7544453 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3095860 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40675674 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30035361 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7544453 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3095860 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40675674 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016958 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016781 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115215 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.024404 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016958 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016781 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115215 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.024404 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016958 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016781 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115215 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.024404 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14316.098355 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13892.737343 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6818.014800 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14316.098355 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13892.737343 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6818.014800 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14316.098355 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13892.737343 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6818.014800 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4716 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 41630359 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 41630359 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 29500548 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7433858 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2732478 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 39666884 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29500548 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7433858 # 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number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7561080 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3087765 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 40659510 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016998 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016826 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115063 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.024413 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016998 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016826 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115063 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.024413 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016998 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016826 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115063 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.024413 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14340.059109 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13898.822597 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6812.678677 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14340.059109 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13898.822597 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6812.678677 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14340.059109 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13898.822597 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6812.678677 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4393 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 235 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 224 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.068085 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.611607 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 969876 # 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number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 461235 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 126603 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 334632 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 461235 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1685858000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4399066985 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6084924985 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1685858000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4399066985 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6084924985 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1685858000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4399066985 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6084924985 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011339 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011339 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011339 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13192.678320 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 970146 # number of writebacks +system.cpu0.icache.writebacks::total 970146 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 21777 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 21777 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 21777 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 21777 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 21777 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 21777 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 127222 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 333510 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 460732 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 127222 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 333510 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 460732 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 127222 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 333510 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 460732 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1697149000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4385581487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6082730487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1697149000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4385581487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6082730487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1697149000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4385581487 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6082730487 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13202.318239 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13202.318239 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13202.318239 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1184324 # DTB read hits -system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_hits 1185765 # DTB read hits +system.cpu1.dtb.read_misses 1350 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 141546 # DTB read accesses -system.cpu1.dtb.write_hits 885341 # DTB write hits -system.cpu1.dtb.write_misses 169 # DTB write misses -system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57820 # DTB write accesses -system.cpu1.dtb.data_hits 2069665 # DTB hits -system.cpu1.dtb.data_misses 1485 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 199366 # DTB accesses -system.cpu1.itb.fetch_hits 852668 # ITB hits -system.cpu1.itb.fetch_misses 656 # ITB misses -system.cpu1.itb.fetch_acv 33 # ITB acv -system.cpu1.itb.fetch_accesses 853324 # ITB accesses +system.cpu1.dtb.read_accesses 142577 # DTB read accesses +system.cpu1.dtb.write_hits 886140 # DTB write hits +system.cpu1.dtb.write_misses 164 # DTB write misses +system.cpu1.dtb.write_acv 19 # DTB write access violations +system.cpu1.dtb.write_accesses 58302 # DTB write accesses +system.cpu1.dtb.data_hits 2071905 # DTB hits +system.cpu1.dtb.data_misses 1514 # DTB misses +system.cpu1.dtb.data_acv 53 # DTB access violations +system.cpu1.dtb.data_accesses 200879 # DTB accesses +system.cpu1.itb.fetch_hits 858318 # ITB hits +system.cpu1.itb.fetch_misses 678 # ITB misses +system.cpu1.itb.fetch_acv 29 # ITB acv +system.cpu1.itb.fetch_accesses 858996 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -946,17 +942,17 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 2293 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1147 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1553407081.081081 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 1902806399.455202 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1147 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 6635637500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1147 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 59841239000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1781757922000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 953375365 # number of cpu cycles simulated +system.cpu1.numPwrStateTransitions 2295 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 1148 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1552918826.219512 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 1902969233.500840 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1148 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 123500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 6633070500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 1148 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 59822381500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1782750812500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 953371043 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -976,94 +972,94 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7542911 # Number of instructions committed -system.cpu1.committedOps 7542911 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7009980 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44709 # Number of float alu accesses -system.cpu1.num_func_calls 205791 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 911955 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7009980 # number of integer instructions -system.cpu1.num_fp_insts 44709 # number of float instructions -system.cpu1.num_int_register_reads 9753806 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5113025 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24116 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24503 # number of times the floating registers were written -system.cpu1.num_mem_refs 2076660 # number of memory refs -system.cpu1.num_load_insts 1189039 # Number of load instructions -system.cpu1.num_store_insts 887621 # Number of store instructions -system.cpu1.num_idle_cycles 923368497.825425 # Number of idle cycles -system.cpu1.num_busy_cycles 30006867.174575 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031474 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968526 # Percentage of idle cycles -system.cpu1.Branches 1183564 # Number of branches fetched -system.cpu1.op_class::No_OpClass 404590 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 4887103 64.78% 70.14% # Class of executed instruction -system.cpu1.op_class::IntMult 8470 0.11% 70.25% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.25% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5131 0.07% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.33% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::MemRead 1217523 16.14% 86.47% # Class of executed instruction -system.cpu1.op_class::MemWrite 888839 11.78% 98.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 131986 1.75% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7559512 # Number of instructions committed +system.cpu1.committedOps 7559512 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7024268 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44783 # Number of float alu accesses +system.cpu1.num_func_calls 206891 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 914000 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7024268 # number of integer instructions +system.cpu1.num_fp_insts 44783 # number of float instructions +system.cpu1.num_int_register_reads 9773567 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5124259 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24150 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24568 # number of times the floating registers were written +system.cpu1.num_mem_refs 2078876 # number of memory refs +system.cpu1.num_load_insts 1190479 # Number of load instructions +system.cpu1.num_store_insts 888397 # Number of store instructions +system.cpu1.num_idle_cycles 923345266.952757 # Number of idle cycles +system.cpu1.num_busy_cycles 30025776.047243 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031494 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968506 # Percentage of idle cycles +system.cpu1.Branches 1187005 # Number of branches fetched +system.cpu1.op_class::No_OpClass 406253 5.37% 5.37% # Class of executed instruction +system.cpu1.op_class::IntAlu 4898849 64.79% 70.16% # Class of executed instruction +system.cpu1.op_class::IntMult 8443 0.11% 70.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5163 0.07% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatDiv 816 0.01% 70.35% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::MemRead 1219110 16.12% 86.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 889613 11.77% 98.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 132832 1.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7544452 # Class of executed instruction -system.cpu2.branchPred.lookups 10195062 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9245801 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 194837 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7645666 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5489178 # Number of BTB hits +system.cpu1.op_class::total 7561079 # Class of executed instruction +system.cpu2.branchPred.lookups 10182069 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9237326 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 193435 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7648921 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5487936 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.794635 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 367323 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 14555 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1840410 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 186758 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 1653652 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 86236 # Number of mispredicted indirect branches. +system.cpu2.branchPred.BTBHitPct 71.747845 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 365631 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 14350 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1844704 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 187088 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 1657616 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 85690 # Number of mispredicted indirect branches. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3794321 # DTB read hits -system.cpu2.dtb.read_misses 14980 # DTB read misses -system.cpu2.dtb.read_acv 154 # DTB read access violations -system.cpu2.dtb.read_accesses 231448 # DTB read accesses -system.cpu2.dtb.write_hits 2188085 # DTB write hits -system.cpu2.dtb.write_misses 3764 # DTB write misses +system.cpu2.dtb.read_hits 3799673 # DTB read hits +system.cpu2.dtb.read_misses 14845 # DTB read misses +system.cpu2.dtb.read_acv 160 # DTB read access violations +system.cpu2.dtb.read_accesses 231351 # DTB read accesses +system.cpu2.dtb.write_hits 2187859 # DTB write hits +system.cpu2.dtb.write_misses 3782 # DTB write misses system.cpu2.dtb.write_acv 156 # DTB write access violations -system.cpu2.dtb.write_accesses 84759 # DTB write accesses -system.cpu2.dtb.data_hits 5982406 # DTB hits -system.cpu2.dtb.data_misses 18744 # DTB misses -system.cpu2.dtb.data_acv 310 # DTB access violations -system.cpu2.dtb.data_accesses 316207 # DTB accesses -system.cpu2.itb.fetch_hits 533759 # ITB hits -system.cpu2.itb.fetch_misses 2736 # ITB misses -system.cpu2.itb.fetch_acv 191 # ITB acv -system.cpu2.itb.fetch_accesses 536495 # ITB accesses +system.cpu2.dtb.write_accesses 85049 # DTB write accesses +system.cpu2.dtb.data_hits 5987532 # DTB hits +system.cpu2.dtb.data_misses 18627 # DTB misses +system.cpu2.dtb.data_acv 316 # DTB access violations +system.cpu2.dtb.data_accesses 316400 # DTB accesses +system.cpu2.itb.fetch_hits 533981 # ITB hits +system.cpu2.itb.fetch_misses 2772 # ITB misses +system.cpu2.itb.fetch_acv 207 # ITB acv +system.cpu2.itb.fetch_accesses 536753 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1076,265 +1072,263 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numPwrStateTransitions 3116 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 1558 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 289379505.134788 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 445107312.150922 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 1558 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::min_value 3000 # Distribution of time spent in the clock gated state +system.cpu2.numPwrStateTransitions 3110 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 1555 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 290577901.929260 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 445615554.555058 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 1555 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::min_value 35500 # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 1558 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 1390745892000 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 450853269000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 30327275 # number of cpu cycles simulated +system.cpu2.pwrStateClkGateDist::total 1555 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 1390724556500 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 451848637500 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 30294700 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9354335 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 40099246 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10195062 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6043259 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18967134 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 549482 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 7 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 11119 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1939 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 54610 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 90342 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 596 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3095865 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 133552 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 28754585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.394534 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.444600 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9331724 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40046932 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10182069 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6040655 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18950980 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 546368 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 10813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1967 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 55421 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 90541 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 526 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3087771 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 132437 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 28714918 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.394639 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.444168 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 19879004 69.13% 69.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 339943 1.18% 70.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516791 1.80% 72.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4053539 14.10% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 887171 3.09% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 213563 0.74% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 261735 0.91% 90.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 444517 1.55% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2158322 7.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 19847963 69.12% 69.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 338255 1.18% 70.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516605 1.80% 72.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4056347 14.13% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 883774 3.08% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 213492 0.74% 90.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 260077 0.91% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 443832 1.55% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2154573 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 28754585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.336168 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.322217 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7569976 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 12996616 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7107544 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 570612 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 263955 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 225265 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 11264 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36283979 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 35882 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 263955 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7872857 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4931794 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5918579 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7355041 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2166486 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35279837 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 60983 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 402801 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 76926 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1084115 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23748051 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 43586446 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43526101 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56436 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20540056 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 3207995 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 542145 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 75307 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3912291 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3917277 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2333144 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 542030 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329847 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32377023 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 701408 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 31676973 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 27053 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 3928896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1754776 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 507029 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 28754585 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.101632 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.635117 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 28714918 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.336101 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.321912 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7553623 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 12980509 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7101757 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 570685 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 262482 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 224592 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 11278 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36245198 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 35745 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 262482 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7856240 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4908054 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5914164 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7349808 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2178317 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35245227 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 60989 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 402200 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 73644 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1098810 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23726835 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43551141 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43490937 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56291 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20541823 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 3185012 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 542390 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 75158 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3906024 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3910206 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2331407 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 534571 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 330323 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32351146 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 700049 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 31671278 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 26658 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 3899534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1737148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 505950 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 28714918 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.102956 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.635713 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17376990 60.43% 60.43% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2804831 9.75% 70.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1408095 4.90% 75.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4807285 16.72% 91.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1079199 3.75% 95.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 630267 2.19% 97.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 421060 1.46% 99.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 175258 0.61% 99.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 51600 0.18% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17343310 60.40% 60.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2798035 9.74% 70.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1407296 4.90% 75.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4809954 16.75% 91.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1078748 3.76% 95.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 629909 2.19% 97.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 420699 1.47% 99.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 175678 0.61% 99.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 51289 0.18% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 28754585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 28714918 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 83759 19.66% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 210235 49.34% 69.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 132097 31.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 83963 19.65% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 211212 49.43% 69.08% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 132122 30.92% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 25141274 79.37% 79.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20994 0.07% 79.44% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 79.44% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20528 0.06% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3966361 12.52% 92.03% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2221145 7.01% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 302997 0.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2449 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 25130857 79.35% 79.36% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21000 0.07% 79.42% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 79.42% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20519 0.06% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3970834 12.54% 92.03% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2221095 7.01% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 303300 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 31676973 # Type of FU issued -system.cpu2.iq.rate 1.044504 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 426091 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013451 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92299555 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 36885759 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 30885842 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 262120 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 128344 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 120451 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 31960571 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 140043 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 222851 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 31671278 # Type of FU issued +system.cpu2.iq.rate 1.045440 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 427297 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013492 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92249666 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36829058 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 30874313 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 261763 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 128201 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 120289 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 31956268 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 139858 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 223032 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 843917 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1448 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6897 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 272853 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 835467 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1428 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6657 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 271687 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4760 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 213103 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4727 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 223048 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 263955 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4308277 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 202891 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34565468 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 70386 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3917277 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2333144 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 625709 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 13182 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 148814 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6897 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 76158 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 205534 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 281692 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 31394525 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3819678 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 282448 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 262482 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4297358 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 190047 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34535423 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 71039 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3910206 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2331407 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 624892 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12907 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 136174 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6657 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 75410 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 204692 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 280102 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31389945 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3824957 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 281333 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1487037 # number of nop insts executed -system.cpu2.iew.exec_refs 6017890 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6848661 # Number of branches executed -system.cpu2.iew.exec_stores 2198212 # Number of stores executed -system.cpu2.iew.exec_rate 1.035191 # Inst execution rate -system.cpu2.iew.wb_sent 31083503 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31006293 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17785830 # num instructions producing a value -system.cpu2.iew.wb_consumers 21615859 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.022390 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.822814 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 4127890 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194379 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 252373 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28042775 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.083004 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.865926 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 1484228 # number of nop insts executed +system.cpu2.iew.exec_refs 6022953 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6845679 # Number of branches executed +system.cpu2.iew.exec_stores 2197996 # Number of stores executed +system.cpu2.iew.exec_rate 1.036153 # Inst execution rate +system.cpu2.iew.wb_sent 31070665 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30994602 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17781356 # num instructions producing a value +system.cpu2.iew.wb_consumers 21603769 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.023103 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.823067 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 4096171 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194099 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 251035 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28008857 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.084369 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.866736 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18161783 64.76% 64.76% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2276613 8.12% 72.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1151869 4.11% 76.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4491226 16.02% 93.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 562178 2.00% 95.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 204579 0.73% 95.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 167176 0.60% 96.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 177068 0.63% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 850283 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18128303 64.72% 64.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2274965 8.12% 72.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1151627 4.11% 76.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4494039 16.05% 93.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 560514 2.00% 95.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 204888 0.73% 95.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 167574 0.60% 96.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 175902 0.63% 96.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 851045 3.04% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28042775 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30370432 # Number of instructions committed -system.cpu2.commit.committedOps 30370432 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28008857 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30371950 # Number of instructions committed +system.cpu2.commit.committedOps 30371950 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5133651 # Number of memory references committed -system.cpu2.commit.loads 3073360 # Number of loads committed -system.cpu2.commit.membars 68499 # Number of memory barriers committed -system.cpu2.commit.branches 6541282 # Number of branches committed -system.cpu2.commit.fp_insts 116010 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28852886 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241096 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1223345 4.03% 4.03% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 23598567 77.70% 81.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20428 0.07% 81.80% # Class of committed instruction +system.cpu2.commit.refs 5134459 # Number of memory references committed +system.cpu2.commit.loads 3074739 # Number of loads committed +system.cpu2.commit.membars 68371 # Number of memory barriers committed +system.cpu2.commit.branches 6541536 # Number of branches committed +system.cpu2.commit.fp_insts 115785 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28855389 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240551 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1222737 4.03% 4.03% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 23599707 77.70% 81.73% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20441 0.07% 81.80% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20084 0.07% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20074 0.07% 81.86% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.86% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.86% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.86% # Class of committed instruction @@ -1360,29 +1354,29 @@ system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3141859 10.35% 92.21% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2061928 6.79% 99.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 302997 1.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3143110 10.35% 92.21% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2061357 6.79% 99.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 303300 1.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 30370432 # Class of committed instruction -system.cpu2.commit.bw_lim_events 850283 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 61616016 # The number of ROB reads -system.cpu2.rob.rob_writes 69709723 # The number of ROB writes -system.cpu2.timesIdled 166720 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1572690 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745481695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29149535 # Number of Instructions Simulated -system.cpu2.committedOps 29149535 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.040403 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.040403 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.961166 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.961166 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 41087551 # number of integer regfile reads -system.cpu2.int_regfile_writes 22005301 # number of integer regfile writes -system.cpu2.fp_regfile_reads 71153 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74234 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4377642 # number of misc regfile reads -system.cpu2.misc_regfile_writes 272877 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 30371950 # Class of committed instruction +system.cpu2.commit.bw_lim_events 851045 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 61550290 # The number of ROB reads +system.cpu2.rob.rob_writes 69643370 # The number of ROB writes +system.cpu2.timesIdled 166665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1579782 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747467532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29151661 # Number of Instructions Simulated +system.cpu2.committedOps 29151661 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.039210 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.039210 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.962269 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.962269 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 41082611 # number of integer regfile reads +system.cpu2.int_regfile_writes 21995152 # number of integer regfile writes +system.cpu2.fp_regfile_reads 71087 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74140 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4380582 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272883 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1395,12 +1389,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51362 # Transaction distribution -system.iobus.trans_dist::WriteResp 51362 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51363 # Transaction distribution +system.iobus.trans_dist::WriteResp 51363 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1409,11 +1403,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1825 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1422,42 +1416,42 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2373500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2361000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 135500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 133500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 56000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5872500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5888500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2528000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2490000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 89904673 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 89817179 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9173000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9132000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17450000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254561 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.262350 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1693898501000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254561 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078410 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078410 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::tsunami.ide 1.262350 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078897 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078897 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1466,14 +1460,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9598462 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9598462 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2019796211 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2019796211 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 2029394673 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 2029394673 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 2029394673 # number of overall miss cycles -system.iocache.overall_miss_latency::total 2029394673 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9479963 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9479963 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2017910216 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2017910216 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 2027390179 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 2027390179 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 2027390179 # number of overall miss cycles +system.iocache.overall_miss_latency::total 2027390179 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1490,14 +1484,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55482.439306 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 55482.439306 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48608.880704 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 48608.880704 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 48637.379820 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 48637.379820 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54797.473988 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54797.473988 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48563.491914 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48563.491914 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 48589.339221 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 48589.339221 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 48589.339221 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 48589.339221 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1506,487 +1500,464 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17350 # 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Average number of references to valid blocks. +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17264 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 17264 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 17333 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17333 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17333 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17333 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6029963 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6029963 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1153715348 # 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average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66909.670051 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 337759 # number of replacements +system.l2c.tags.tagsinuse 65519.967313 # Cycle average of tags in use +system.l2c.tags.total_refs 4324806 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 403281 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.724051 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54641.026539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2330.416055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2713.129703 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 574.927105 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 600.162086 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2250.445944 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2311.215132 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.833756 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035559 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009158 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034339 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.035266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998250 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 987 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5975 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2686 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55336 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38533534 # Number of tag accesses -system.l2c.tags.data_accesses 38533534 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 836681 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 836681 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 969577 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 969577 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 234482500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 352216500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 586699000 # number of overall MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.294118 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.172414 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407099 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.252377 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.137371 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.160920 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061975 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.029900 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.236601 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.110912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034332 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.236601 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.110912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034332 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50500 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66582.176189 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79447.540778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74005.704932 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73239.834499 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 65233.096881 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 65633.844617 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 65441.862601 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65946.703793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73712.701588 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70495.345745 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65946.703793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73712.701588 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70495.345745 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207323.165340 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205613.835377 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206293.600563 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91594.726562 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94478.674893 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 93304.548346 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 823847 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 379580 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 295138 # Transaction distribution -system.membus.trans_dist::WriteReq 9810 # Transaction distribution -system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117013 # Transaction distribution -system.membus.trans_dist::CleanEvict 261704 # Transaction distribution -system.membus.trans_dist::UpgradeReq 179 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 113 # Transaction distribution -system.membus.trans_dist::ReadExReq 115428 # Transaction distribution -system.membus.trans_dist::ReadExResp 115428 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288010 # Transaction distribution -system.membus.trans_dist::BadAddressError 16 # Transaction distribution +system.membus.trans_dist::ReadResp 295118 # Transaction distribution +system.membus.trans_dist::WriteReq 9811 # Transaction distribution +system.membus.trans_dist::WriteResp 9811 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117015 # Transaction distribution +system.membus.trans_dist::CleanEvict 261705 # Transaction distribution +system.membus.trans_dist::UpgradeReq 133 # Transaction distribution +system.membus.trans_dist::UpgradeResp 97 # Transaction distribution +system.membus.trans_dist::ReadExReq 115450 # Transaction distribution +system.membus.trans_dist::ReadExResp 115450 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287989 # Transaction distribution +system.membus.trans_dist::BadAddressError 15 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 24272 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143724 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 107800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 107800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1285464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30679232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33343552 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 157 # Total snoops (count) -system.membus.snoopTraffic 9856 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 742227 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001296 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.035978 # Request fanout histogram +system.membus.trans_dist::InvalidateResp 24288 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 30 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177609 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 107817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 107817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1285426 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30634176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30679752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33344136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 152 # Total snoops (count) +system.membus.snoopTraffic 9536 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 742383 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001299 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036012 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 741265 99.87% 99.87% # Request fanout histogram -system.membus.snoop_fanout::1 962 0.13% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 741419 99.87% 99.87% # Request fanout histogram +system.membus.snoop_fanout::1 964 0.13% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 742227 # Request fanout histogram -system.membus.reqLayer0.occupancy 10965500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 742383 # Request fanout histogram +system.membus.reqLayer0.occupancy 10929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 390337877 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 389109129 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 436169750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 434990750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 370538 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 365537 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4730181 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2364664 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1038 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1038 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 4730225 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2364683 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1647 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1041 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2070392 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 866358 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 969876 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 609667 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 58 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302472 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302472 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 970586 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1092680 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2910960 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4218835 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7129795 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124183936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142881728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 267065664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 338688 # Total snoops (count) -system.toL2Bus.snoopTraffic 4852416 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4114055 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.000998 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.031568 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2070475 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 866906 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 970146 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 608698 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302414 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302414 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 970849 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1092499 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 15 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 40 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2911790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4218095 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7129885 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124220224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142912456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 267132680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 338659 # Total snoops (count) +system.toL2Bus.snoopTraffic 4850432 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4115169 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000990 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.031456 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4109951 99.90% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4104 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4111093 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4076 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4114055 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1826321500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4115169 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1824758000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 98963 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 692196311 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 691417859 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 770446828 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 769604277 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2018,29 +1989,29 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |