diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
3 files changed, 4356 insertions, 4144 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index bc7291548..9c4d04cdf 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.905240 # Number of seconds simulated -sim_ticks 1905239522500 # Number of ticks simulated -final_tick 1905239522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.905651 # Number of seconds simulated +sim_ticks 1905651402000 # Number of ticks simulated +final_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125426 # Simulator instruction rate (inst/s) -host_op_rate 125426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4213194084 # Simulator tick rate (ticks/s) -host_mem_usage 351852 # Number of bytes of host memory used -host_seconds 452.21 # Real time elapsed on the host -sim_insts 56718526 # Number of instructions simulated -sim_ops 56718526 # Number of ops (including micro ops) simulated +host_inst_rate 124387 # Simulator instruction rate (inst/s) +host_op_rate 124387 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4179760275 # Simulator tick rate (ticks/s) +host_mem_usage 352908 # Number of bytes of host memory used +host_seconds 455.92 # Real time elapsed on the host +sim_insts 56710998 # Number of instructions simulated +sim_ops 56710998 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 764480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24384256 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 214080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 925440 # Number of bytes read from this memory -system.physmem.bytes_read::total 28937600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 764480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 214080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7885248 # Number of bytes written to this memory -system.physmem.bytes_written::total 7885248 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 381004 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14460 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452150 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123207 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123207 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 401251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12798525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1390557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 112364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 485734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15188432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 401251 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 112364 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4138717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4138717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4138717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 401251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12798525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1390557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 112364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 485734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19327149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 452150 # Number of read requests accepted -system.physmem.writeReqs 123207 # Number of write requests accepted -system.physmem.readBursts 452150 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123207 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28929984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 7883136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28937600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7885248 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory +system.physmem.bytes_read::total 28857792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory +system.physmem.bytes_written::total 7816896 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450903 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122139 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450903 # Number of read requests accepted +system.physmem.writeReqs 122139 # Number of write requests accepted +system.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue +system.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 5017 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28700 # Per bank write bursts -system.physmem.perBankRdBursts::1 28863 # Per bank write bursts -system.physmem.perBankRdBursts::2 29008 # Per bank write bursts -system.physmem.perBankRdBursts::3 28541 # Per bank write bursts -system.physmem.perBankRdBursts::4 28135 # Per bank write bursts -system.physmem.perBankRdBursts::5 28059 # Per bank write bursts -system.physmem.perBankRdBursts::6 27918 # Per bank write bursts -system.physmem.perBankRdBursts::7 27861 # Per bank write bursts -system.physmem.perBankRdBursts::8 27885 # Per bank write bursts -system.physmem.perBankRdBursts::9 28003 # Per bank write bursts -system.physmem.perBankRdBursts::10 27955 # Per bank write bursts -system.physmem.perBankRdBursts::11 28030 # Per bank write bursts -system.physmem.perBankRdBursts::12 28165 # Per bank write bursts -system.physmem.perBankRdBursts::13 28514 # Per bank write bursts -system.physmem.perBankRdBursts::14 28239 # Per bank write bursts -system.physmem.perBankRdBursts::15 28155 # Per bank write bursts -system.physmem.perBankWrBursts::0 8383 # Per bank write bursts -system.physmem.perBankWrBursts::1 8222 # Per bank write bursts -system.physmem.perBankWrBursts::2 8291 # Per bank write bursts -system.physmem.perBankWrBursts::3 7900 # Per bank write bursts -system.physmem.perBankWrBursts::4 7506 # Per bank write bursts -system.physmem.perBankWrBursts::5 7518 # Per bank write bursts -system.physmem.perBankWrBursts::6 7426 # Per bank write bursts -system.physmem.perBankWrBursts::7 7231 # Per bank write bursts -system.physmem.perBankWrBursts::8 7193 # Per bank write bursts -system.physmem.perBankWrBursts::9 7295 # Per bank write bursts -system.physmem.perBankWrBursts::10 7315 # Per bank write bursts -system.physmem.perBankWrBursts::11 7381 # Per bank write bursts -system.physmem.perBankWrBursts::12 7680 # Per bank write bursts -system.physmem.perBankWrBursts::13 8142 # Per bank write bursts -system.physmem.perBankWrBursts::14 8013 # Per bank write bursts -system.physmem.perBankWrBursts::15 7678 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28020 # Per bank write bursts +system.physmem.perBankRdBursts::1 28240 # Per bank write bursts +system.physmem.perBankRdBursts::2 28746 # Per bank write bursts +system.physmem.perBankRdBursts::3 28309 # Per bank write bursts +system.physmem.perBankRdBursts::4 27973 # Per bank write bursts +system.physmem.perBankRdBursts::5 28180 # Per bank write bursts +system.physmem.perBankRdBursts::6 28116 # Per bank write bursts +system.physmem.perBankRdBursts::7 27456 # Per bank write bursts +system.physmem.perBankRdBursts::8 27700 # Per bank write bursts +system.physmem.perBankRdBursts::9 28070 # Per bank write bursts +system.physmem.perBankRdBursts::10 27744 # Per bank write bursts +system.physmem.perBankRdBursts::11 28151 # Per bank write bursts +system.physmem.perBankRdBursts::12 28476 # Per bank write bursts +system.physmem.perBankRdBursts::13 28764 # Per bank write bursts +system.physmem.perBankRdBursts::14 28477 # Per bank write bursts +system.physmem.perBankRdBursts::15 28339 # Per bank write bursts +system.physmem.perBankWrBursts::0 7807 # Per bank write bursts +system.physmem.perBankWrBursts::1 7750 # Per bank write bursts +system.physmem.perBankWrBursts::2 8222 # Per bank write bursts +system.physmem.perBankWrBursts::3 7743 # Per bank write bursts +system.physmem.perBankWrBursts::4 7390 # Per bank write bursts +system.physmem.perBankWrBursts::5 7636 # Per bank write bursts +system.physmem.perBankWrBursts::6 7609 # Per bank write bursts +system.physmem.perBankWrBursts::7 6913 # Per bank write bursts +system.physmem.perBankWrBursts::8 6944 # Per bank write bursts +system.physmem.perBankWrBursts::9 7275 # Per bank write bursts +system.physmem.perBankWrBursts::10 7157 # Per bank write bursts +system.physmem.perBankWrBursts::11 7547 # Per bank write bursts +system.physmem.perBankWrBursts::12 7916 # Per bank write bursts +system.physmem.perBankWrBursts::13 8234 # Per bank write bursts +system.physmem.perBankWrBursts::14 8082 # Per bank write bursts +system.physmem.perBankWrBursts::15 7890 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 1905235063000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1905651381000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 452150 # Read request sizes (log2) +system.physmem.readPktSize::6 450903 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123207 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 319865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3977 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122139 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -158,360 +158,358 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 51367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 630.908404 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 404.510586 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 424.248985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9707 18.90% 18.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6974 13.58% 32.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3124 6.08% 38.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1892 3.68% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1518 2.96% 45.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 943 1.84% 47.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 823 1.60% 48.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 886 1.72% 50.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25500 49.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 51367 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7232 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 62.502074 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2469.163441 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 7229 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7232 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.031803 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.787924 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.763450 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6148 85.01% 85.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.48% 85.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 69 0.95% 86.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 422 5.84% 92.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 144 1.99% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 0.69% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.46% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 29 0.40% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 50 0.69% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 33 0.46% 96.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 22 0.30% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 30 0.41% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 23 0.32% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 33 0.46% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.14% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 7 0.10% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 5 0.07% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 3 0.04% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 4 0.06% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 6 0.08% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 7 0.10% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 5 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 2 0.03% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 2 0.03% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 9 0.12% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 8 0.11% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 6 0.08% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 4 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 3 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7232 # Writes before turning the bus around for reads -system.physmem.totQLat 10473139750 # Total ticks spent queuing -system.physmem.totMemAccLat 18209837250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2260155000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5476542500 # Total ticks spent accessing banks -system.physmem.avgQLat 23169.07 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 12115.41 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads +system.physmem.totQLat 8930594750 # Total ticks spent queuing +system.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40284.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.83 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.68 # Average write queue length when enqueuing -system.physmem.readRowHits 407908 # Number of row buffer hits during reads -system.physmem.writeRowHits 99848 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.04 # Row buffer hit rate for writes -system.physmem.avgGap 3311396.34 # Average gap between requests -system.physmem.pageHitRate 88.27 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19386335 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296672 # Transaction distribution -system.membus.trans_dist::ReadResp 296448 # Transaction distribution -system.membus.trans_dist::WriteReq 13044 # Transaction distribution -system.membus.trans_dist::WriteResp 13044 # Transaction distribution -system.membus.trans_dist::Writeback 123207 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9628 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5545 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5017 # Transaction distribution -system.membus.trans_dist::ReadExReq 163957 # Transaction distribution -system.membus.trans_dist::ReadExResp 163513 # Transaction distribution -system.membus.trans_dist::BadAddressError 224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40492 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 924104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 448 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 965044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124646 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124646 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1089690 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73787 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31516032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31589819 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36896635 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36896635 # Total data (bytes) -system.membus.snoop_data_through_bus 38976 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37949499 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing +system.physmem.readRowHits 407659 # Number of row buffer hits during reads +system.physmem.writeRowHits 98604 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes +system.physmem.avgGap 3325500.37 # Average gap between requests +system.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states +system.physmem.memoryStateTime::REF 63633700000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 37488657000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 19303809 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296468 # Transaction distribution +system.membus.trans_dist::ReadResp 296393 # Transaction distribution +system.membus.trans_dist::WriteReq 13039 # Transaction distribution +system.membus.trans_dist::WriteResp 13039 # Transaction distribution +system.membus.trans_dist::Writeback 122139 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9699 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4861 # Transaction distribution +system.membus.trans_dist::ReadExReq 162690 # Transaction distribution +system.membus.trans_dist::ReadExResp 162297 # Transaction distribution +system.membus.trans_dist::BadAddressError 75 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36748378 # Total data (bytes) +system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1621348498 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 283500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3837196476 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376708248 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 345233 # number of replacements -system.l2c.tags.tagsinuse 65245.285653 # Cycle average of tags in use -system.l2c.tags.total_refs 2551644 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410415 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.217229 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7106352750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53519.548176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4149.494238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5612.081999 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1358.843164 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 605.318076 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816643 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.020734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009236 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995564 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2472 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5440 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5794 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51245 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994598 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26808140 # Number of tag accesses -system.l2c.tags.data_accesses 26808140 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 890534 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 623023 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 181208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 171976 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1866741 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 807199 # number of Writeback hits -system.l2c.Writeback_hits::total 807199 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 179 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 196 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 375 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 42 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 156975 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 15152 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172127 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 890534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 779998 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 181208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 187128 # number of demand (read+write) hits -system.l2c.demand_hits::total 2038868 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 890534 # number of overall hits -system.l2c.overall_hits::cpu0.data 779998 # number of overall hits -system.l2c.overall_hits::cpu1.inst 181208 # number of overall hits -system.l2c.overall_hits::cpu1.data 187128 # number of overall hits -system.l2c.overall_hits::total 2038868 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11953 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272223 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3356 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1782 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289314 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3186 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 726 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3912 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 379 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 428 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 807 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109189 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13070 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122259 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11953 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 381412 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3356 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 14852 # number of demand (read+write) misses -system.l2c.demand_misses::total 411573 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11953 # number of overall misses -system.l2c.overall_misses::cpu0.data 381412 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3356 # number of overall misses -system.l2c.overall_misses::cpu1.data 14852 # number of overall misses -system.l2c.overall_misses::total 411573 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 917004250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17843471250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 269423486 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 137552496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19167451482 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1326945 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 933461 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2260406 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 265489 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2039412 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2304901 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9056624622 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1307071580 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10363696202 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 917004250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26900095872 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 269423486 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1444624076 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29531147684 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 917004250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26900095872 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 269423486 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1444624076 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29531147684 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 902487 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 895246 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 184564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 173758 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2156055 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 807199 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 807199 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3365 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 922 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4287 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 421 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.tags.replacements 343977 # number of replacements +system.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use +system.l2c.tags.total_refs 2582565 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27108862 # Number of tag accesses +system.l2c.tags.data_accesses 27108862 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits +system.l2c.Writeback_hits::total 822208 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits +system.l2c.demand_hits::total 2062288 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 867616 # number of overall hits +system.l2c.overall_hits::cpu0.data 891053 # number of overall hits +system.l2c.overall_hits::cpu1.inst 210128 # number of overall hits +system.l2c.overall_hits::cpu1.data 93491 # number of overall hits +system.l2c.overall_hits::total 2062288 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3729 # 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number of overall misses +system.l2c.overall_misses::cpu1.inst 1238 # number of overall misses +system.l2c.overall_misses::cpu1.data 6794 # number of overall misses +system.l2c.overall_misses::total 410154 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1067454245 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17881620237 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 96862500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 35356999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19081293981 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 964468 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 4567794 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 5532262 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 972461 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114995 # 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number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 96862500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 674854213 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1317 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 605687000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3995826500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270683 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006597 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133140 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940535 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.801822 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.896610 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.892308 # 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average ReadReq mshr uncacheable latency @@ -649,15 +647,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.475429 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.491978 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712299730000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.475429 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029714 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029714 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712295759000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.491978 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030749 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030749 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -671,14 +669,14 @@ system.iocache.demand_misses::tsunami.ide 41727 # n system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21363133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21363133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 13166015946 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 13166015946 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13187379079 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13187379079 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13187379079 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13187379079 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21492883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21492883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12499299192 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12499299192 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12520792075 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12520792075 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12520792075 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12520792075 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -695,24 +693,24 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122075.045714 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122075.045714 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316856.371438 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 316856.371438 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 316039.472739 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 316039.472739 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 316039.472739 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 316039.472739 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 391077 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122816.474286 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122816.474286 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 300811.012514 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 300811.012514 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 300064.516380 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 300064.516380 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 367481 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28468 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28552 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.737424 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.870587 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41523 # number of writebacks -system.iocache.writebacks::total 41523 # number of writebacks +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses @@ -721,14 +719,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41727 system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12262133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12262133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11002982450 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 11002982450 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 11015244583 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 11015244583 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 11015244583 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 11015244583 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -737,14 +735,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70069.331429 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70069.331429 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264800.309251 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 264800.309251 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263983.621708 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 263983.621708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263983.621708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 263983.621708 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -758,35 +756,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12197818 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10301308 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 323625 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8091894 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5160475 # Number of BTB hits +system.cpu0.branchPred.lookups 12477942 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 63.773389 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 773216 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29770 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8724392 # DTB read hits -system.cpu0.dtb.read_misses 30821 # DTB read misses -system.cpu0.dtb.read_acv 561 # DTB read access violations -system.cpu0.dtb.read_accesses 667825 # DTB read accesses -system.cpu0.dtb.write_hits 5867379 # DTB write hits -system.cpu0.dtb.write_misses 8333 # DTB write misses -system.cpu0.dtb.write_acv 362 # DTB write access violations -system.cpu0.dtb.write_accesses 233878 # DTB write accesses -system.cpu0.dtb.data_hits 14591771 # DTB hits -system.cpu0.dtb.data_misses 39154 # DTB misses -system.cpu0.dtb.data_acv 923 # DTB access violations -system.cpu0.dtb.data_accesses 901703 # DTB accesses -system.cpu0.itb.fetch_hits 1047253 # ITB hits -system.cpu0.itb.fetch_misses 31067 # ITB misses -system.cpu0.itb.fetch_acv 998 # ITB acv -system.cpu0.itb.fetch_accesses 1078320 # ITB accesses +system.cpu0.dtb.read_hits 8879185 # DTB read hits +system.cpu0.dtb.read_misses 30734 # DTB read misses +system.cpu0.dtb.read_acv 556 # DTB read access violations +system.cpu0.dtb.read_accesses 627584 # DTB read accesses +system.cpu0.dtb.write_hits 5815647 # DTB write hits +system.cpu0.dtb.write_misses 8173 # DTB write misses +system.cpu0.dtb.write_acv 357 # DTB write access violations +system.cpu0.dtb.write_accesses 210225 # DTB write accesses +system.cpu0.dtb.data_hits 14694832 # DTB hits +system.cpu0.dtb.data_misses 38907 # DTB misses +system.cpu0.dtb.data_acv 913 # DTB access violations +system.cpu0.dtb.data_accesses 837809 # DTB accesses +system.cpu0.itb.fetch_hits 998260 # ITB hits +system.cpu0.itb.fetch_misses 27519 # ITB misses +system.cpu0.itb.fetch_acv 894 # ITB acv +system.cpu0.itb.fetch_accesses 1025779 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -799,269 +797,304 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112262549 # number of cpu cycles simulated +system.cpu0.numCycles 116074371 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25337690 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 62232975 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12197818 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5933691 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11660813 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1669062 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34963299 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31852 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 204835 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 245581 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7519019 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 220862 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 73507816 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.846617 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.186991 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 61847003 84.14% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 769960 1.05% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1463561 1.99% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676221 0.92% 88.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2490968 3.39% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 505392 0.69% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 543861 0.74% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 933568 1.27% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4277282 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 73507816 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.108654 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.554352 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26369028 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34601594 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10599753 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 908827 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1028613 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 489342 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35202 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61098455 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 108348 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1028613 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27370799 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12650473 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18559497 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9975684 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3922748 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 57686354 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6807 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 465136 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1446625 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 38461887 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 70023385 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69867874 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 145011 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33864047 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4597832 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1504040 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 221397 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10820518 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9135753 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6149920 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1079808 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 706714 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 51077926 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1853906 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49994907 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 110749 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5661802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2962344 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1252355 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 73507816 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.680130 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328001 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 51188064 69.64% 69.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10233888 13.92% 83.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4604901 6.26% 89.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2962380 4.03% 93.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2331848 3.17% 97.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1189595 1.62% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 642601 0.87% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 303208 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51331 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 73507816 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 67972 10.01% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 320913 47.27% 57.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 290070 42.72% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34052559 68.11% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 53588 0.11% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 16727 0.03% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9088781 18.18% 86.44% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5934753 11.87% 98.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 842846 1.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49994907 # Type of FU issued -system.cpu0.iq.rate 0.445339 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 678955 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013580 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 173664474 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 58303886 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48932524 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 622859 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 301167 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 293964 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 50344041 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326051 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 531595 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued +system.cpu0.iq.rate 0.443500 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1104780 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2697 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 11676 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 443054 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13921 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 147330 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1028613 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8821962 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 743484 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 56052726 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 628552 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9135753 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6149920 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1633160 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 601804 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5465 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 11676 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 157790 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 354691 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 512481 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49615767 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8780349 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 379139 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3120894 # number of nop insts executed -system.cpu0.iew.exec_refs 14670742 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7826693 # Number of branches executed -system.cpu0.iew.exec_stores 5890393 # Number of stores executed -system.cpu0.iew.exec_rate 0.441962 # Inst execution rate -system.cpu0.iew.wb_sent 49317778 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 49226488 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24274382 # num instructions producing a value -system.cpu0.iew.wb_consumers 32670143 # num instructions consuming a value +system.cpu0.iew.exec_nop 3229636 # number of nop insts executed +system.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8136394 # Number of branches executed +system.cpu0.iew.exec_stores 5837466 # Number of stores executed +system.cpu0.iew.exec_rate 0.440174 # Inst execution rate +system.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25278333 # num instructions producing a value +system.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.438494 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743014 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6126865 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 601551 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 478401 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 72479203 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.687487 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.606917 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 53761554 74.18% 74.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7891628 10.89% 85.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4152119 5.73% 90.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2321486 3.20% 93.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1304265 1.80% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 530677 0.73% 96.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 447192 0.62% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 447640 0.62% 97.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1622642 2.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 72479203 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49828537 # Number of instructions committed -system.cpu0.commit.committedOps 49828537 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51248256 # Number of instructions committed +system.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13737839 # Number of memory references committed -system.cpu0.commit.loads 8030973 # Number of loads committed -system.cpu0.commit.membars 204358 # Number of memory barriers committed -system.cpu0.commit.branches 7461649 # Number of branches committed -system.cpu0.commit.fp_insts 291974 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46136165 # Number of committed integer instructions. -system.cpu0.commit.function_calls 636945 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1622642 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13810671 # Number of memory references committed +system.cpu0.commit.loads 8171492 # Number of loads committed +system.cpu0.commit.membars 199624 # Number of memory barriers committed +system.cpu0.commit.branches 7741114 # Number of branches committed +system.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47457125 # Number of committed integer instructions. +system.cpu0.commit.function_calls 657479 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126610557 # The number of ROB reads -system.cpu0.rob.rob_writes 112939421 # The number of ROB writes -system.cpu0.timesIdled 1039659 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38754733 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698211471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46979170 # Number of Instructions Simulated -system.cpu0.committedOps 46979170 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 46979170 # Number of Instructions Simulated -system.cpu0.cpi 2.389624 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.389624 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.418476 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.418476 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65113755 # number of integer regfile reads -system.cpu0.int_regfile_writes 35503571 # number of integer regfile writes -system.cpu0.fp_regfile_reads 144629 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146446 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1885764 # number of misc regfile reads -system.cpu0.misc_regfile_writes 851290 # number of misc regfile writes +system.cpu0.rob.rob_reads 130790454 # The number of ROB reads +system.cpu0.rob.rob_writes 116222813 # The number of ROB writes +system.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48300626 # Number of Instructions Simulated +system.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 48300626 # Number of Instructions Simulated +system.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67219449 # number of integer regfile reads +system.cpu0.int_regfile_writes 36695614 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128632 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130173 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads +system.cpu0.misc_regfile_writes 820377 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1093,83 +1126,83 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110236199 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2184890 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2184651 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13044 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13044 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 807199 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9705 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5617 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15322 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 337408 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295861 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1805066 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3017885 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 369158 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 600045 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5792154 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57759168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 115626954 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 11812096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23360753 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 208558971 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 208548411 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1477952 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4893610631 # Layer occupancy (ticks) +system.toL2Bus.throughput 111416521 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210926490 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4065813860 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5358512161 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 831641640 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 971081953 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1435731 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 54596 # Transaction distribution -system.iobus.trans_dist::WriteResp 54596 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11886 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 1435370 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 54591 # Transaction distribution +system.iobus.trans_dist::WriteResp 54591 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123946 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47544 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73787 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735411 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735411 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11236000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2735314 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1181,7 +1214,7 @@ system.iobus.reqLayer23.occupancy 13505000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1189,267 +1222,268 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 379995831 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27448000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43184752 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 901902 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.676111 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6573395 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 902414 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.284234 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26905725250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.676111 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995461 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995461 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8421597 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8421597 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6573395 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6573395 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6573395 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6573395 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6573395 # number of overall hits -system.cpu0.icache.overall_hits::total 6573395 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945623 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945623 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945623 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945623 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945623 # number of overall misses -system.cpu0.icache.overall_misses::total 945623 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13224491137 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13224491137 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13224491137 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13224491137 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13224491137 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13224491137 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7519018 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7519018 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7519018 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7519018 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7519018 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7519018 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125764 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125764 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125764 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125764 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125764 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125764 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13984.950807 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13984.950807 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13984.950807 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13984.950807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13984.950807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13984.950807 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3461 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 139 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 881127 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits +system.cpu0.icache.overall_hits::total 6795719 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses +system.cpu0.icache.overall_misses::total 926821 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.034722 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 139 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43044 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43044 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43044 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43044 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43044 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43044 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 902579 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 902579 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 902579 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 902579 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 902579 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 902579 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10909532635 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10909532635 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10909532635 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10909532635 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10909532635 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10909532635 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.120039 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.120039 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.120039 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12087.066766 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12087.066766 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12087.066766 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1164537 # number of replacements -system.cpu0.dcache.tags.tagsinuse 498.695388 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10555909 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1165049 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.060485 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26173000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.695388 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974014 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.974014 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1281204 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56283368 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56283368 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6422745 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6422745 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3752316 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3752316 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172180 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172180 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 196241 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 196241 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10175061 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10175061 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10175061 # number of overall hits -system.cpu0.dcache.overall_hits::total 10175061 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1468970 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1468970 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1742020 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1742020 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20433 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20433 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2875 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2875 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3210990 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3210990 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3210990 # number of overall misses -system.cpu0.dcache.overall_misses::total 3210990 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38326965830 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 38326965830 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76755016444 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 76755016444 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 286872989 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 286872989 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20380878 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20380878 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 115081982274 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 115081982274 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 115081982274 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 115081982274 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7891715 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7891715 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5494336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5494336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 199116 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199116 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13386051 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13386051 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13386051 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13386051 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186141 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.186141 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317057 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.317057 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106083 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.106083 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014439 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014439 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239876 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.239876 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239876 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.239876 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26091.047353 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26091.047353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44060.927225 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44060.927225 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14039.690158 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14039.690158 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7089.001043 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7089.001043 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35840.031353 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35840.031353 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35840.031353 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35840.031353 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2903843 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 789 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48428 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits +system.cpu0.dcache.overall_hits::total 10126574 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses +system.cpu0.dcache.overall_misses::total 3345621 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.962067 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 112.714286 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 644423 # number of writebacks -system.cpu0.dcache.writebacks::total 644423 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 578811 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 578811 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1469624 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1469624 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4269 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4269 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2048435 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2048435 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2048435 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2048435 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 890159 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 890159 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272396 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272396 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16164 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16164 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2875 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2875 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1162555 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1162555 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1162555 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1162555 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25660783347 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25660783347 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11256320137 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11256320137 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175450760 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175450760 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14630122 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14630122 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36917103484 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36917103484 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36917103484 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36917103484 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 999097000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 999097000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1765340999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1765340999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2764437999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2764437999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.112797 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.112797 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049578 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049578 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083920 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083920 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014439 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014439 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086848 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086848 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086848 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086848 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28827.190813 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28827.190813 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41323.367953 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41323.367953 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10854.414749 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10854.414749 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5088.738087 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5088.738087 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31755.145764 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31755.145764 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31755.145764 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31755.145764 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks +system.cpu0.dcache.writebacks::total 754427 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1457,35 +1491,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2770041 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2267711 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 80921 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1482926 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 969002 # Number of BTB hits +system.cpu1.branchPred.lookups 2485884 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 831190 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.343921 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 198874 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6522 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2016743 # DTB read hits -system.cpu1.dtb.read_misses 9789 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 278621 # DTB read accesses -system.cpu1.dtb.write_hits 1132288 # DTB write hits -system.cpu1.dtb.write_misses 1938 # DTB write misses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_accesses 105909 # DTB write accesses -system.cpu1.dtb.data_hits 3149031 # DTB hits -system.cpu1.dtb.data_misses 11727 # DTB misses -system.cpu1.dtb.data_acv 43 # DTB access violations -system.cpu1.dtb.data_accesses 384530 # DTB accesses -system.cpu1.itb.fetch_hits 369710 # ITB hits -system.cpu1.itb.fetch_misses 5636 # ITB misses -system.cpu1.itb.fetch_acv 119 # ITB acv -system.cpu1.itb.fetch_accesses 375346 # ITB accesses +system.cpu1.dtb.read_hits 1846757 # DTB read hits +system.cpu1.dtb.read_misses 10485 # DTB read misses +system.cpu1.dtb.read_acv 25 # DTB read access violations +system.cpu1.dtb.read_accesses 320297 # DTB read accesses +system.cpu1.dtb.write_hits 1188866 # DTB write hits +system.cpu1.dtb.write_misses 1998 # DTB write misses +system.cpu1.dtb.write_acv 67 # DTB write access violations +system.cpu1.dtb.write_accesses 130212 # DTB write accesses +system.cpu1.dtb.data_hits 3035623 # DTB hits +system.cpu1.dtb.data_misses 12483 # DTB misses +system.cpu1.dtb.data_acv 92 # DTB access violations +system.cpu1.dtb.data_accesses 450509 # DTB accesses +system.cpu1.itb.fetch_hits 420713 # ITB hits +system.cpu1.itb.fetch_misses 6600 # ITB misses +system.cpu1.itb.fetch_acv 223 # ITB acv +system.cpu1.itb.fetch_accesses 427313 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1498,519 +1532,553 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 18798992 # number of cpu cycles simulated +system.cpu1.numCycles 14964653 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5357256 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13511342 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2770041 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1167876 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2476292 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 427198 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 8263333 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26082 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 54640 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 162618 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1630522 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50477 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 16624070 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.812758 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.170685 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 14147778 85.10% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 131100 0.79% 85.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 332329 2.00% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 198517 1.19% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 395957 2.38% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 132924 0.80% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 159356 0.96% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 93423 0.56% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1032686 6.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 16624070 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.147351 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.718727 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5556172 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8353280 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2307081 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 131115 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 276421 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 130911 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7501 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 13245951 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 18855 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 276421 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5775463 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2664230 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4961239 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2147700 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 799015 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 12421307 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 241 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 220838 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 145988 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 8355946 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 15113763 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 15073339 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 35607 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7070748 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1285198 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 385003 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 30758 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2314294 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2123178 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1208247 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 244787 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 150121 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 10996175 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 428151 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10636944 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 28046 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1617836 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 831016 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 312637 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 16624070 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.639852 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.326685 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 12087523 72.71% 72.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1967089 11.83% 84.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 877391 5.28% 89.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 655455 3.94% 93.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 567827 3.42% 97.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 232884 1.40% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 149324 0.90% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 75580 0.45% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10997 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 16624070 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 16676 8.84% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 99378 52.65% 61.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 72683 38.51% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7118581 66.92% 66.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 18880 0.18% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 9739 0.09% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2093745 19.68% 86.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1155572 10.86% 97.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 235150 2.21% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10636944 # Type of FU issued -system.cpu1.iq.rate 0.565825 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 188737 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017744 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 37986289 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 12982235 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10383881 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 128452 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 62754 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 61527 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10755461 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 66702 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 101929 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued +system.cpu1.iq.rate 0.609525 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 306426 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 815 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2923 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 138344 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 4845 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 18286 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 276421 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2089253 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 85247 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 12015910 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 137996 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2123178 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1208247 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 388932 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 10076 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1666 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2923 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 39900 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 91880 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 131780 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10541126 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2031671 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 95818 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 591584 # number of nop insts executed -system.cpu1.iew.exec_refs 3170643 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1658996 # Number of branches executed -system.cpu1.iew.exec_stores 1138972 # Number of stores executed -system.cpu1.iew.exec_rate 0.560728 # Inst execution rate -system.cpu1.iew.wb_sent 10475567 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 10445408 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5214693 # num instructions producing a value -system.cpu1.iew.wb_consumers 7314185 # num instructions consuming a value +system.cpu1.iew.exec_nop 483081 # number of nop insts executed +system.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1345265 # Number of branches executed +system.cpu1.iew.exec_stores 1196645 # Number of stores executed +system.cpu1.iew.exec_rate 0.603549 # Inst execution rate +system.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4203498 # num instructions producing a value +system.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.555637 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712956 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1685534 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 115514 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 123376 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16347649 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.627728 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.542862 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12457643 76.20% 76.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1697144 10.38% 86.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 844179 5.16% 91.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 419187 2.56% 94.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 268727 1.64% 95.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 133453 0.82% 96.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 126834 0.78% 97.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 88227 0.54% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 312255 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16347649 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10261869 # Number of instructions committed -system.cpu1.commit.committedOps 10261869 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8834118 # Number of instructions committed +system.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2886655 # Number of memory references committed -system.cpu1.commit.loads 1816752 # Number of loads committed -system.cpu1.commit.membars 36648 # Number of memory barriers committed -system.cpu1.commit.branches 1542101 # Number of branches committed -system.cpu1.commit.fp_insts 60269 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9518406 # Number of committed integer instructions. -system.cpu1.commit.function_calls 159983 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 312255 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2811640 # Number of memory references committed +system.cpu1.commit.loads 1676136 # Number of loads committed +system.cpu1.commit.membars 41495 # Number of memory barriers committed +system.cpu1.commit.branches 1262292 # Number of branches committed +system.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8189363 # Number of committed integer instructions. +system.cpu1.commit.function_calls 139415 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction +system.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 27899142 # The number of ROB reads -system.cpu1.rob.rob_writes 24169847 # The number of ROB writes -system.cpu1.timesIdled 181051 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2174922 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3790987217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9739356 # Number of Instructions Simulated -system.cpu1.committedOps 9739356 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 9739356 # Number of Instructions Simulated -system.cpu1.cpi 1.930209 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.930209 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.518079 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.518079 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13792462 # number of integer regfile reads -system.cpu1.int_regfile_writes 7586165 # number of integer regfile writes -system.cpu1.fp_regfile_reads 35303 # number of floating regfile reads -system.cpu1.fp_regfile_writes 34737 # number of floating regfile writes -system.cpu1.misc_regfile_reads 829246 # number of misc regfile reads -system.cpu1.misc_regfile_writes 174995 # number of misc regfile writes -system.cpu1.icache.tags.replacements 184023 # number of replacements -system.cpu1.icache.tags.tagsinuse 502.144736 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1436916 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 184535 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.786685 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1712232500000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 502.144736 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980751 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980751 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 23736453 # The number of ROB reads +system.cpu1.rob.rob_writes 20710450 # The number of ROB writes +system.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8410372 # Number of Instructions Simulated +system.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8410372 # Number of Instructions Simulated +system.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11653751 # number of integer regfile reads +system.cpu1.int_regfile_writes 6367365 # number of integer regfile writes +system.cpu1.fp_regfile_reads 51509 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51143 # number of floating regfile writes +system.cpu1.misc_regfile_reads 926936 # number of misc regfile reads +system.cpu1.misc_regfile_writes 206554 # number of misc regfile writes +system.cpu1.icache.tags.replacements 210820 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1815116 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1815116 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1436916 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1436916 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1436916 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1436916 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1436916 # number of overall hits -system.cpu1.icache.overall_hits::total 1436916 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 193606 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 193606 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 193606 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 193606 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 193606 # number of overall misses -system.cpu1.icache.overall_misses::total 193606 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2794361223 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2794361223 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2794361223 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2794361223 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2794361223 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2794361223 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1630522 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1630522 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1630522 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1630522 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1630522 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1630522 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.118739 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.118739 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.118739 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.118739 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.118739 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.118739 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14433.236692 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14433.236692 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14433.236692 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14433.236692 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14433.236692 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14433.236692 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1663 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits +system.cpu1.icache.overall_hits::total 1201520 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses +system.cpu1.icache.overall_misses::total 219211 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.154295 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154295 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.154295 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13453.418898 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13453.418898 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 63 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.396825 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9012 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 9012 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 9012 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 9012 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 9012 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 9012 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 184594 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 184594 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 184594 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 184594 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 184594 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 184594 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2304763360 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2304763360 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2304763360 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2304763360 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2304763360 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2304763360 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.113212 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.113212 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.113212 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12485.581113 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12485.581113 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12485.581113 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7818 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7818 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7818 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7818 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7818 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7818 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211393 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 211393 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 211393 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 211393 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 211393 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 211393 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 203792 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.930753 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2483389 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 204116 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 12.166557 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 43808643250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.930753 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960802 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.960802 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12059624 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12059624 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1586410 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1586410 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 857564 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 857564 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 22125 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 22125 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 21120 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 21120 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2443974 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2443974 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2443974 # number of overall hits -system.cpu1.dcache.overall_hits::total 2443974 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 285731 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 285731 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 181299 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 181299 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4484 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4484 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2742 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2742 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 467030 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 467030 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 467030 # number of overall misses -system.cpu1.dcache.overall_misses::total 467030 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4578373047 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4578373047 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10436073649 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10436073649 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56388497 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 56388497 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20553927 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 20553927 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15014446696 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15014446696 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15014446696 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15014446696 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1872141 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1872141 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1038863 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1038863 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 26609 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 26609 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 23862 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 23862 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2911004 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2911004 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2911004 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2911004 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.152623 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.152623 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174517 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.174517 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.168514 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.168514 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.114911 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.114911 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160436 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.160436 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160436 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.160436 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16023.368297 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16023.368297 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 57562.775575 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 57562.775575 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12575.489964 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12575.489964 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7495.961707 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7495.961707 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32148.784224 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32148.784224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32148.784224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32148.784224 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 370227 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 102235 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1521331 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 890954 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 890954 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30283 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 30283 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29173 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 29173 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2412285 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2412285 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2412285 # number of overall hits +system.cpu1.dcache.overall_hits::total 2412285 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 196472 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 196472 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 206616 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 206616 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5011 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5011 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2898 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2898 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 403088 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 403088 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 403088 # number of overall misses +system.cpu1.dcache.overall_misses::total 403088 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2745758970 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2745758970 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6806020354 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6806020354 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50048997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 50048997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21170434 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 21170434 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9551779324 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9551779324 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9551779324 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9551779324 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1717803 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1717803 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1097570 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1097570 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 35294 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 35294 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32071 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 32071 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2815373 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2815373 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2815373 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2815373 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114374 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114374 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188249 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.188249 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.141979 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.141979 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090362 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090362 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143174 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.143174 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143174 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.143174 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9987.826182 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9987.826182 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7305.187716 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7305.187716 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23696.511243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23696.511243 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 206242 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6127 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 60.425494 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 162776 # number of writebacks -system.cpu1.dcache.writebacks::total 162776 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 104604 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 104604 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148843 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 148843 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 899 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 899 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 253447 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 253447 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 253447 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 253447 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 181127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32456 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 32456 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3585 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3585 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2742 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2742 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 213583 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 213583 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 213583 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 213583 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2418933900 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2418933900 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1545787184 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1545787184 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26756251 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 26756251 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15069073 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15069073 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3964721084 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3964721084 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3964721084 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3964721084 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485705000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485705000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 998872003 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 998872003 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1484577003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1484577003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096749 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096749 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031242 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031242 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.134729 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.134729 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.114911 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.114911 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.073371 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.073371 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.073371 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.073371 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13354.905122 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13354.905122 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47627.162435 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47627.162435 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7463.389400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7463.389400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5495.650255 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5495.650255 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18562.905681 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18562.905681 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18562.905681 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18562.905681 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks +system.cpu1.dcache.writebacks::total 67781 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2019,161 +2087,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5026 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 189626 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 66604 40.25% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.08% 40.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.16% 41.49% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 191 0.12% 41.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 96634 58.39% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 165488 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 65244 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.45% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 191 0.14% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 65055 49.08% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 132549 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865394285500 97.91% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63356500 0.00% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 573165000 0.03% 97.94% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 85999500 0.00% 97.95% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39121861000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1905238667500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.979581 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.673210 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.800958 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 232 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 211 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 273 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3846 2.21% 2.37% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.39% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed -system.cpu0.kern.callpal::swpipl 158278 90.80% 93.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6346 3.64% 96.84% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.84% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.84% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.85% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.85% # number of callpals executed -system.cpu0.kern.callpal::rti 4961 2.85% 99.70% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.22% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 174309 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7462 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1354 # number of protection mode switches +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed +system.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 169959 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1353 -system.cpu0.kern.mode_good::user 1354 +system.cpu0.kern.mode_good::kernel 1286 +system.cpu0.kern.mode_good::user 1287 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181319 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.307055 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1903211741000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2026918500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3847 # number of times the context was actually changed +system.cpu0.kern.swap_context 3530 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3999 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 49848 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 15658 37.06% 37.06% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 4.55% 41.62% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 273 0.65% 42.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 24392 57.74% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 42247 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 15641 47.10% 47.10% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 5.79% 52.90% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 273 0.82% 53.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15369 46.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 33207 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871713408000 98.26% 98.26% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533048500 0.03% 98.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 128777500 0.01% 98.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 32519855000 1.71% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1904895089000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998914 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630084 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.786020 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed -system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed -system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 94 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 115 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 191 0.44% 0.44% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.44% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed -system.cpu1.kern.callpal::swpctx 742 1.70% 2.15% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.15% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 2.17% # number of callpals executed -system.cpu1.kern.callpal::swpipl 37463 85.96% 88.13% # number of callpals executed -system.cpu1.kern.callpal::rdps 2409 5.53% 93.66% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.66% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.67% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.68% # number of callpals executed -system.cpu1.kern.callpal::rti 2587 5.94% 99.62% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.28% 99.90% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.10% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed +system.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed +system.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed +system.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed +system.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 43580 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 937 # number of protection mode switches -system.cpu1.kern.mode_switch::user 383 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2395 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 617 -system.cpu1.kern.mode_good::user 383 -system.cpu1.kern.mode_good::idle 234 -system.cpu1.kern.mode_switch_good::kernel 0.658485 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 48076 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches +system.cpu1.kern.mode_switch::user 460 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 662 +system.cpu1.kern.mode_good::user 460 +system.cpu1.kern.mode_good::idle 202 +system.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.097704 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.332167 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 34875641000 1.83% 1.83% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 708299500 0.04% 1.87% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868990228500 98.13% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 743 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1068 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 0b1609ec3..272c07d73 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,128 +1,128 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860192 # Number of seconds simulated -sim_ticks 1860191785500 # Number of ticks simulated -final_tick 1860191785500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860188 # Number of seconds simulated +sim_ticks 1860187818000 # Number of ticks simulated +final_tick 1860187818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128947 # Simulator instruction rate (inst/s) -host_op_rate 128947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4527634915 # Simulator tick rate (ticks/s) -host_mem_usage 347764 # Number of bytes of host memory used -host_seconds 410.85 # Real time elapsed on the host -sim_insts 52978349 # Number of instructions simulated -sim_ops 52978349 # Number of ops (including micro ops) simulated +host_inst_rate 129673 # Simulator instruction rate (inst/s) +host_op_rate 129673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4553007725 # Simulator tick rate (ticks/s) +host_mem_usage 348812 # Number of bytes of host memory used +host_seconds 408.56 # Real time elapsed on the host +sim_insts 52979638 # Number of instructions simulated +sim_ops 52979638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 963264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 963200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881344 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28492800 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15051 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516608 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388771 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445200 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13373486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15317130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13373486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19357247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445200 # Number of read requests accepted -system.physmem.writeReqs 117428 # Number of write requests accepted -system.physmem.readBursts 445200 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117428 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28485504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7513728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28492800 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7515392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 445263 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117447 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117447 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13375716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15319331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517797 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517797 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13375716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19360110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445263 # Number of read requests accepted +system.physmem.writeReqs 117447 # Number of write requests accepted +system.physmem.readBursts 445263 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117447 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28490624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 7515520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28496832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7516608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 178 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28210 # Per bank write bursts -system.physmem.perBankRdBursts::1 27995 # Per bank write bursts -system.physmem.perBankRdBursts::2 28357 # Per bank write bursts -system.physmem.perBankRdBursts::3 27829 # Per bank write bursts -system.physmem.perBankRdBursts::4 27761 # Per bank write bursts -system.physmem.perBankRdBursts::5 27267 # Per bank write bursts -system.physmem.perBankRdBursts::6 27371 # Per bank write bursts -system.physmem.perBankRdBursts::7 27375 # Per bank write bursts -system.physmem.perBankRdBursts::8 27696 # Per bank write bursts -system.physmem.perBankRdBursts::9 27269 # Per bank write bursts -system.physmem.perBankRdBursts::10 28017 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 171 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28211 # Per bank write bursts +system.physmem.perBankRdBursts::1 27992 # Per bank write bursts +system.physmem.perBankRdBursts::2 28433 # Per bank write bursts +system.physmem.perBankRdBursts::3 27987 # Per bank write bursts +system.physmem.perBankRdBursts::4 27796 # Per bank write bursts +system.physmem.perBankRdBursts::5 27217 # Per bank write bursts +system.physmem.perBankRdBursts::6 27269 # Per bank write bursts +system.physmem.perBankRdBursts::7 27319 # Per bank write bursts +system.physmem.perBankRdBursts::8 27690 # Per bank write bursts +system.physmem.perBankRdBursts::9 27272 # Per bank write bursts +system.physmem.perBankRdBursts::10 28021 # Per bank write bursts system.physmem.perBankRdBursts::11 27509 # Per bank write bursts -system.physmem.perBankRdBursts::12 27546 # Per bank write bursts -system.physmem.perBankRdBursts::13 28232 # Per bank write bursts -system.physmem.perBankRdBursts::14 28342 # Per bank write bursts -system.physmem.perBankRdBursts::15 28310 # Per bank write bursts -system.physmem.perBankWrBursts::0 7920 # Per bank write bursts -system.physmem.perBankWrBursts::1 7516 # Per bank write bursts -system.physmem.perBankWrBursts::2 7873 # Per bank write bursts -system.physmem.perBankWrBursts::3 7373 # Per bank write bursts -system.physmem.perBankWrBursts::4 7309 # Per bank write bursts -system.physmem.perBankWrBursts::5 6720 # Per bank write bursts -system.physmem.perBankWrBursts::6 6881 # Per bank write bursts -system.physmem.perBankWrBursts::7 6774 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts -system.physmem.perBankWrBursts::9 6679 # Per bank write bursts -system.physmem.perBankWrBursts::10 7411 # Per bank write bursts -system.physmem.perBankWrBursts::11 6967 # Per bank write bursts -system.physmem.perBankWrBursts::12 7107 # Per bank write bursts -system.physmem.perBankWrBursts::13 7877 # Per bank write bursts -system.physmem.perBankWrBursts::14 8064 # Per bank write bursts -system.physmem.perBankWrBursts::15 7795 # Per bank write bursts +system.physmem.perBankRdBursts::12 27548 # Per bank write bursts +system.physmem.perBankRdBursts::13 28237 # Per bank write bursts +system.physmem.perBankRdBursts::14 28335 # Per bank write bursts +system.physmem.perBankRdBursts::15 28330 # Per bank write bursts +system.physmem.perBankWrBursts::0 7921 # Per bank write bursts +system.physmem.perBankWrBursts::1 7511 # Per bank write bursts +system.physmem.perBankWrBursts::2 7946 # Per bank write bursts +system.physmem.perBankWrBursts::3 7492 # Per bank write bursts +system.physmem.perBankWrBursts::4 7346 # Per bank write bursts +system.physmem.perBankWrBursts::5 6678 # Per bank write bursts +system.physmem.perBankWrBursts::6 6778 # Per bank write bursts +system.physmem.perBankWrBursts::7 6711 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts +system.physmem.perBankWrBursts::9 6681 # Per bank write bursts +system.physmem.perBankWrBursts::10 7414 # Per bank write bursts +system.physmem.perBankWrBursts::11 6966 # Per bank write bursts +system.physmem.perBankWrBursts::12 7109 # Per bank write bursts +system.physmem.perBankWrBursts::13 7879 # Per bank write bursts +system.physmem.perBankWrBursts::14 8056 # Per bank write bursts +system.physmem.perBankWrBursts::15 7812 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 1860186344000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1860182401000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445200 # Read request sizes (log2) +system.physmem.readPktSize::6 445263 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117428 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 322906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1891 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117447 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2540 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -148,132 +148,129 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 651.388927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 428.580055 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.495686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8350 17.18% 17.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6347 13.06% 30.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2940 6.05% 36.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1813 3.73% 40.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1501 3.09% 43.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 899 1.85% 44.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 723 1.49% 46.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 886 1.82% 48.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25144 51.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48603 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6893 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.568403 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2543.170744 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6890 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1100 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63749 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 564.805095 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 351.189585 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.649920 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13350 20.94% 20.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10335 16.21% 37.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4789 7.51% 44.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2797 4.39% 49.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2437 3.82% 52.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.47% 55.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1469 2.30% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1613 2.53% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25383 39.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63749 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6887 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 64.637723 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 16.523346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2544.314640 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6884 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6893 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6893 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.032062 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.789521 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.768510 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5850 84.87% 84.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 28 0.41% 85.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 70 1.02% 86.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 418 6.06% 92.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 134 1.94% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 49 0.71% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 24 0.35% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.32% 95.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 53 0.77% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 38 0.55% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.29% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 34 0.49% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 19 0.28% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 34 0.49% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 7 0.10% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.15% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.03% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 3 0.04% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 6 0.09% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 5 0.07% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 5 0.07% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 8 0.12% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 2 0.03% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 5 0.07% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 6 0.09% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 6 0.09% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 4 0.06% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 3 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 6 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6893 # Writes before turning the bus around for reads -system.physmem.totQLat 10196532000 # Total ticks spent queuing -system.physmem.totMemAccLat 17805650750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225430000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5383688750 # Total ticks spent accessing banks -system.physmem.avgQLat 22909.13 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 12095.84 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6887 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6887 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.050966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.814496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.834643 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5493 79.76% 79.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 28 0.41% 80.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 690 10.02% 90.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 216 3.14% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 116 1.68% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 20 0.29% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 25 0.36% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 93 1.35% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 19 0.28% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 44 0.64% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 11 0.16% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 7 0.10% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 8 0.12% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 16 0.23% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.03% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 14 0.20% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 9 0.13% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.01% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.01% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 3 0.04% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.03% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.01% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.01% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 2 0.03% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 7 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 4 0.06% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 3 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 1 0.01% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 3 0.04% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 3 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 7 0.10% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.01% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 7 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 17 0.25% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6887 # Writes before turning the bus around for reads +system.physmem.totQLat 8647566500 # Total ticks spent queuing +system.physmem.totMemAccLat 16994429000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225830000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19425.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40004.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 38175.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s @@ -281,60 +278,64 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.57 # Average write queue length when enqueuing -system.physmem.readRowHits 402462 # Number of row buffer hits during reads -system.physmem.writeRowHits 96189 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.91 # Row buffer hit rate for writes -system.physmem.avgGap 3306245.59 # Average gap between requests -system.physmem.pageHitRate 88.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19400105 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295926 # Transaction distribution -system.membus.trans_dist::ReadResp 295846 # Transaction distribution +system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.02 # Average write queue length when enqueuing +system.physmem.readRowHits 403062 # Number of row buffer hits during reads +system.physmem.writeRowHits 95784 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.56 # Row buffer hit rate for writes +system.physmem.avgGap 3305756.79 # Average gap between requests +system.physmem.pageHitRate 88.67 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761433244000 # Time in different power states +system.physmem.memoryStateTime::REF 62115560000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 36633312250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 19402968 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295944 # Transaction distribution +system.membus.trans_dist::ReadResp 295866 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117428 # Transaction distribution -system.membus.trans_dist::UpgradeReq 181 # Transaction distribution -system.membus.trans_dist::UpgradeResp 181 # Transaction distribution -system.membus.trans_dist::ReadExReq 156840 # Transaction distribution -system.membus.trans_dist::ReadExResp 156840 # Transaction distribution -system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.trans_dist::Writeback 117447 # Transaction distribution +system.membus.trans_dist::UpgradeReq 174 # Transaction distribution +system.membus.trans_dist::UpgradeResp 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 156883 # Transaction distribution +system.membus.trans_dist::ReadExResp 156883 # Transaction distribution +system.membus.trans_dist::BadAddressError 78 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699136 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30743276 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704384 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748524 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36052332 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36052332 # Total data (bytes) +system.membus.tot_pkt_size::total 36057580 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36057580 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29929000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29864500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1552530249 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1548275500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 100500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 98000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3767548549 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3770327047 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376726994 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376611244 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261130 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261115 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710337661000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261130 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078821 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078821 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710335896000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261115 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -348,14 +349,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 13194182648 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 13194182648 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13215316531 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13215316531 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13215316531 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13215316531 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21272883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21272883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12456693929 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12456693929 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12477966812 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12477966812 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12477966812 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12477966812 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -372,19 +373,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 317534.237774 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 316724.182888 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 316724.182888 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 393531 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122964.641618 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299785.664445 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 299052.529946 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 299052.529946 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 365915 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28535 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28370 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.791169 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.897956 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -398,14 +399,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11031075660 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 11031075660 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 11043212543 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 11043212543 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 11043212543 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 11043212543 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12274883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12274883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10293819441 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10293819441 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10306094324 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10306094324 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10306094324 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10306094324 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -414,14 +415,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -435,36 +436,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13847711 # Number of BP lookups -system.cpu.branchPred.condPredicted 11622265 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 397151 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9355929 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5809145 # Number of BTB hits +system.cpu.branchPred.lookups 13846630 # Number of BP lookups +system.cpu.branchPred.condPredicted 11622667 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 398238 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9513264 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5817388 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.090520 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 903416 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38861 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.150284 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 900921 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39034 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9926060 # DTB read hits -system.cpu.dtb.read_misses 41229 # DTB read misses -system.cpu.dtb.read_acv 545 # DTB read access violations -system.cpu.dtb.read_accesses 943227 # DTB read accesses -system.cpu.dtb.write_hits 6592681 # DTB write hits -system.cpu.dtb.write_misses 10567 # DTB write misses -system.cpu.dtb.write_acv 408 # DTB write access violations -system.cpu.dtb.write_accesses 338977 # DTB write accesses -system.cpu.dtb.data_hits 16518741 # DTB hits -system.cpu.dtb.data_misses 51796 # DTB misses -system.cpu.dtb.data_acv 953 # DTB access violations -system.cpu.dtb.data_accesses 1282204 # DTB accesses -system.cpu.itb.fetch_hits 1307907 # ITB hits -system.cpu.itb.fetch_misses 36763 # ITB misses -system.cpu.itb.fetch_acv 1058 # ITB acv -system.cpu.itb.fetch_accesses 1344670 # ITB accesses +system.cpu.dtb.read_hits 9912884 # DTB read hits +system.cpu.dtb.read_misses 41215 # DTB read misses +system.cpu.dtb.read_acv 553 # DTB read access violations +system.cpu.dtb.read_accesses 941108 # DTB read accesses +system.cpu.dtb.write_hits 6599017 # DTB write hits +system.cpu.dtb.write_misses 10339 # DTB write misses +system.cpu.dtb.write_acv 401 # DTB write access violations +system.cpu.dtb.write_accesses 338138 # DTB write accesses +system.cpu.dtb.data_hits 16511901 # DTB hits +system.cpu.dtb.data_misses 51554 # DTB misses +system.cpu.dtb.data_acv 954 # DTB access violations +system.cpu.dtb.data_accesses 1279246 # DTB accesses +system.cpu.itb.fetch_hits 1308304 # ITB hits +system.cpu.itb.fetch_misses 36786 # ITB misses +system.cpu.itb.fetch_acv 1079 # ITB acv +system.cpu.itb.fetch_accesses 1345090 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -477,269 +478,304 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122133073 # number of cpu cycles simulated +system.cpu.numCycles 121969353 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28029052 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70711644 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13847711 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6712561 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13244944 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1986135 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38034896 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253831 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364385 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8541461 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263003 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81242947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.213979 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28022459 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70674133 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13846630 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6718309 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13243332 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1983249 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37995640 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254581 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 364654 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8542175 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264688 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81194854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.870426 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.213908 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67998003 83.70% 83.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 851901 1.05% 84.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1695578 2.09% 86.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 822984 1.01% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2755109 3.39% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 560259 0.69% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 643349 0.79% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1008302 1.24% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4907462 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67951522 83.69% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 854853 1.05% 84.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1698258 2.09% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 823227 1.01% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2753963 3.39% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 558188 0.69% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 642929 0.79% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1006595 1.24% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4905319 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81242947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113382 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.578972 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29204589 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37726390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12112827 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 958015 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1241125 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 582779 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42656 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69393384 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129440 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1241125 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30348079 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14012797 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20034433 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11321379 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4285132 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65602946 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7156 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505213 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1511728 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43797820 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79654521 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79475437 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166633 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179156 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5618656 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682920 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240154 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12205182 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10434201 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6904424 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1321264 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 860087 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58162225 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2049609 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56784496 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 110090 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6876207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3554384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1388666 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81242947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.698947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361354 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81194854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113525 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.579442 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29206421 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37679452 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12104138 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 965352 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1239490 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585042 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69357398 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129450 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1239490 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30354385 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13996332 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19984766 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11324382 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4295497 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65588313 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7118 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505148 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1530678 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43795306 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79617271 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79438234 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180209 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5615089 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682372 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239607 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12205686 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10422971 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6895231 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1319326 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 854507 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58152614 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2049745 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56795087 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 97937 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6861282 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503589 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1388801 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81194854 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.699491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361721 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56591956 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10816248 13.31% 82.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5164366 6.36% 89.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3390360 4.17% 93.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2636798 3.25% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1463129 1.80% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 751413 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332295 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96382 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56519522 69.61% 69.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10856431 13.37% 82.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5145956 6.34% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3402319 4.19% 93.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2626681 3.24% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1459376 1.80% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 753323 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 333723 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 97523 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81242947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81194854 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91428 11.57% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372699 47.16% 58.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326088 41.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 92642 11.69% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372744 47.05% 58.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326922 41.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38710597 68.17% 68.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61705 0.11% 68.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10355398 18.24% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6671255 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38726894 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61723 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10344006 18.21% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6676923 11.76% 98.33% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56784496 # Type of FU issued -system.cpu.iq.rate 0.464940 # Inst issue rate -system.cpu.iq.fu_busy_cnt 790215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013916 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195020122 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66766340 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55549754 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692121 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 335594 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327937 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57205980 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 599867 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56795087 # Type of FU issued +system.cpu.iq.rate 0.465650 # Inst issue rate +system.cpu.iq.fu_busy_cnt 792308 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013950 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194982001 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66741051 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55566428 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693271 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336387 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327889 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57217918 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362191 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598643 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1342082 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3325 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14250 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 526611 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1330641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3245 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 517313 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17915 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 172386 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17932 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 166827 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1241125 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10205447 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 698563 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63733516 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684669 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10434201 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6904424 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805473 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512478 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17546 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14250 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 200257 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411476 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 611733 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56321962 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9995488 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 462533 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1239490 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10213175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 697716 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63724678 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 681593 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10422971 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6895231 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805950 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512370 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16905 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202448 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409860 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 612308 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56329043 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9982328 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466043 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3521682 # number of nop insts executed -system.cpu.iew.exec_refs 16613940 # number of memory reference insts executed -system.cpu.iew.exec_branches 8922207 # Number of branches executed -system.cpu.iew.exec_stores 6618452 # Number of stores executed -system.cpu.iew.exec_rate 0.461152 # Inst execution rate -system.cpu.iew.wb_sent 55993079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55877691 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27722224 # num instructions producing a value -system.cpu.iew.wb_consumers 37565081 # num instructions consuming a value +system.cpu.iew.exec_nop 3522319 # number of nop insts executed +system.cpu.iew.exec_refs 16606918 # number of memory reference insts executed +system.cpu.iew.exec_branches 8922931 # Number of branches executed +system.cpu.iew.exec_stores 6624590 # Number of stores executed +system.cpu.iew.exec_rate 0.461829 # Inst execution rate +system.cpu.iew.wb_sent 56008659 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55894317 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27713107 # num instructions producing a value +system.cpu.iew.wb_consumers 37520284 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.457515 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737979 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458265 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738617 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7447390 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660943 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 565908 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80001822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702098 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.631989 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7436889 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660944 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566942 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79955364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.702522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.631936 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59240837 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8588333 10.74% 84.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4609463 5.76% 90.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2533581 3.17% 93.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1517845 1.90% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611107 0.76% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522353 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 526375 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851928 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59166975 74.00% 74.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8627079 10.79% 84.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4603678 5.76% 90.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2536989 3.17% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1507337 1.89% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611638 0.76% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 523619 0.65% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 528614 0.66% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1849435 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80001822 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56169084 # Number of instructions committed -system.cpu.commit.committedOps 56169084 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79955364 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170432 # Number of instructions committed +system.cpu.commit.committedOps 56170432 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15469932 # Number of memory references committed -system.cpu.commit.loads 9092119 # Number of loads committed -system.cpu.commit.membars 226344 # Number of memory barriers committed -system.cpu.commit.branches 8439731 # Number of branches committed +system.cpu.commit.refs 15470248 # Number of memory references committed +system.cpu.commit.loads 9092330 # Number of loads committed +system.cpu.commit.membars 226348 # Number of memory barriers committed +system.cpu.commit.branches 8439871 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52018783 # Number of committed integer instructions. -system.cpu.commit.function_calls 740550 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851928 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52020070 # Number of committed integer instructions. +system.cpu.commit.function_calls 740568 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198067 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36230888 64.50% 70.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318678 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383871 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949012 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 56170432 # Class of committed instruction +system.cpu.commit.bw_lim_events 1849435 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141516799 # The number of ROB reads -system.cpu.rob.rob_writes 128475885 # The number of ROB writes -system.cpu.timesIdled 1198400 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40890126 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598244060 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52978349 # Number of Instructions Simulated -system.cpu.committedOps 52978349 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52978349 # Number of Instructions Simulated -system.cpu.cpi 2.305339 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.305339 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433776 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433776 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73853807 # number of integer regfile reads -system.cpu.int_regfile_writes 40298046 # number of integer regfile writes -system.cpu.fp_regfile_reads 166062 # number of floating regfile reads -system.cpu.fp_regfile_writes 167446 # number of floating regfile writes -system.cpu.misc_regfile_reads 2027357 # number of misc regfile reads -system.cpu.misc_regfile_writes 938942 # number of misc regfile writes +system.cpu.rob.rob_reads 141463709 # The number of ROB reads +system.cpu.rob.rob_writes 128455843 # The number of ROB writes +system.cpu.timesIdled 1197783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40774499 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598399845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979638 # Number of Instructions Simulated +system.cpu.committedOps 52979638 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979638 # Number of Instructions Simulated +system.cpu.cpi 2.302193 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302193 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434368 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434368 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73867254 # number of integer regfile reads +system.cpu.int_regfile_writes 40307997 # number of integer regfile writes +system.cpu.fp_regfile_reads 166020 # number of floating regfile reads +system.cpu.fp_regfile_writes 167441 # number of floating regfile writes +system.cpu.misc_regfile_reads 2027897 # number of misc regfile reads +system.cpu.misc_regfile_writes 938938 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -771,7 +807,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454553 # Throughput (bytes/s) +system.iobus.throughput 1454556 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51149 # Transaction distribution @@ -831,241 +867,241 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380111537 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380172568 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43192006 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43172756 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111856774 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2116112 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2116015 # Transaction distribution +system.cpu.toL2Bus.throughput 111944057 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2118154 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2118059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840946 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342408 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2017437 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3676056 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5693493 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64554304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143513388 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208067692 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208057644 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17408 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2478840496 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 64 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020220 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677927 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5698147 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64643392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586284 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208229676 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208219628 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17344 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2480508998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1516414125 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1518532368 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186111163 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2189805164 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1008048 # number of replacements -system.cpu.icache.tags.tagsinuse 509.665585 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7476650 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1008556 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.413222 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26682759250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.665585 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1009436 # number of replacements +system.cpu.icache.tags.tagsinuse 509.668112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7476172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1009944 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.402561 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26651967250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.668112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995446 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995446 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9550236 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9550236 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7476651 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7476651 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7476651 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7476651 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7476651 # number of overall hits -system.cpu.icache.overall_hits::total 7476651 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064809 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064809 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064809 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064809 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064809 # number of overall misses -system.cpu.icache.overall_misses::total 1064809 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14791038698 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14791038698 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14791038698 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14791038698 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14791038698 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14791038698 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8541460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8541460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8541460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8541460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8541460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8541460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124664 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124664 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124664 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124664 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124664 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124664 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13890.790459 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13890.790459 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13890.790459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13890.790459 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5929 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 286 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9552342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9552342 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7476173 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7476173 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7476173 # 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average WriteReq mshr uncacheable latency @@ -1147,168 +1183,168 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1400496 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994513 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11811358 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401008 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.430614 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25856000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994513 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1401230 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994514 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11803041 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401742 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.420266 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25812000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994514 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 417 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63734677 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63734677 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7206132 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7206132 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203012 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186466 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186466 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215516 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215516 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15158747 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15158747 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15158747 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15158747 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200309 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200309 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316316 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316316 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108475 # 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miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247643 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247643 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247643 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247643 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31490.266682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31490.266682 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3050951 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 663 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 86776 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31136.036672 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31136.036672 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3013190 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 80012 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.158926 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 94.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.659226 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 118.428571 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # 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number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39167885344 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39167885344 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39167885344 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39167885344 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424097000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424097000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997590998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997590998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421687998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421687998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120220 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120220 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5146 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5146 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2368528 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2368528 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2368528 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2368528 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083943 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083943 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300342 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300342 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17597 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17597 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384285 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384285 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384285 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384285 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275514507 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275514507 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11674414609 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11674414609 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201282500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201282500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38949929116 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38949929116 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38949929116 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38949929116 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424067500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424067500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997567998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997567998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421635498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421635498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120352 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120352 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084296 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084296 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091347 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091347 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1329,11 +1365,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817851866500 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64172000 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 559556500 0.03% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41715361500 2.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860190956500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1817873983000 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64184500 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 553817500 0.03% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41694992500 2.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860186977500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1387,19 +1423,19 @@ system.cpu.kern.callpal::rti 5104 2.66% 99.64% # nu system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191963 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29573655500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2713841000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827903452000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29561208000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2704677000 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827921084500 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index d0170b803..14b9e6b0f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,146 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842694 # Number of seconds simulated -sim_ticks 1842693728000 # Number of ticks simulated -final_tick 1842693728000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.843672 # Number of seconds simulated +sim_ticks 1843672389000 # Number of ticks simulated +final_tick 1843672389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239111 # Simulator instruction rate (inst/s) -host_op_rate 239111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5964368765 # Simulator tick rate (ticks/s) -host_mem_usage 346744 # Number of bytes of host memory used -host_seconds 308.95 # Real time elapsed on the host -sim_insts 73873335 # Number of instructions simulated -sim_ops 73873335 # Number of ops (including micro ops) simulated +host_inst_rate 195444 # Simulator instruction rate (inst/s) +host_op_rate 195444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4916161077 # Simulator tick rate (ticks/s) +host_mem_usage 347768 # Number of bytes of host memory used +host_seconds 375.02 # Real time elapsed on the host +sim_insts 73296119 # Number of instructions simulated +sim_ops 73296119 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 489024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20126208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 488384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20120896 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 143680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2232768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 285376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2509376 # Number of bytes read from this memory -system.physmem.bytes_read::total 28438784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 489024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 143680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 285376 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2228608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 281856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2520448 # Number of bytes read from this memory +system.physmem.bytes_read::total 28440384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 488384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 281856 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 918080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7463104 # Number of bytes written to this memory -system.physmem.bytes_written::total 7463104 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7641 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314472 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 7465920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7465920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314389 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2245 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34887 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39209 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444356 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116611 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116611 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10922167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1211687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 154869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1361798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15433267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 154869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4050105 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4050105 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4050105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10922167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1211687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 154869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1361798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19483372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 97691 # Number of read requests accepted -system.physmem.writeReqs 44282 # Number of write requests accepted -system.physmem.readBursts 97691 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44282 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6250944 # Total number of bytes read from DRAM +system.physmem.num_reads::cpu1.inst 2310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34822 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4404 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39382 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444381 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116655 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116655 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 264897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10913488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1438624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1208787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 152877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1367080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15425942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 264897 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80188 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 152877 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 497963 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4049483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4049483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4049483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 264897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10913488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1438624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1208787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 152877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1367080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19475425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98065 # Number of read requests accepted +system.physmem.writeReqs 44647 # Number of write requests accepted +system.physmem.readBursts 98065 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44647 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6274880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1280 # Total number of bytes read from write queue -system.physmem.bytesWritten 2832576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6252224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2834048 # Total written bytes from the system interface side +system.physmem.bytesWritten 2856000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6276160 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2857408 # Total written bytes from the system interface side system.physmem.servicedByWrQ 20 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6114 # Per bank write bursts -system.physmem.perBankRdBursts::1 5899 # Per bank write bursts -system.physmem.perBankRdBursts::2 6060 # Per bank write bursts -system.physmem.perBankRdBursts::3 6276 # Per bank write bursts -system.physmem.perBankRdBursts::4 5549 # Per bank write bursts -system.physmem.perBankRdBursts::5 6233 # Per bank write bursts -system.physmem.perBankRdBursts::6 6082 # Per bank write bursts -system.physmem.perBankRdBursts::7 6075 # Per bank write bursts -system.physmem.perBankRdBursts::8 6372 # Per bank write bursts -system.physmem.perBankRdBursts::9 6119 # Per bank write bursts -system.physmem.perBankRdBursts::10 6443 # Per bank write bursts -system.physmem.perBankRdBursts::11 5953 # Per bank write bursts -system.physmem.perBankRdBursts::12 5846 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 43 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6107 # Per bank write bursts +system.physmem.perBankRdBursts::1 5922 # Per bank write bursts +system.physmem.perBankRdBursts::2 6220 # Per bank write bursts +system.physmem.perBankRdBursts::3 6321 # Per bank write bursts +system.physmem.perBankRdBursts::4 5635 # Per bank write bursts +system.physmem.perBankRdBursts::5 6235 # Per bank write bursts +system.physmem.perBankRdBursts::6 5931 # Per bank write bursts +system.physmem.perBankRdBursts::7 6044 # Per bank write bursts +system.physmem.perBankRdBursts::8 6533 # Per bank write bursts +system.physmem.perBankRdBursts::9 6108 # Per bank write bursts +system.physmem.perBankRdBursts::10 6507 # Per bank write bursts +system.physmem.perBankRdBursts::11 5966 # Per bank write bursts +system.physmem.perBankRdBursts::12 5866 # Per bank write bursts system.physmem.perBankRdBursts::13 6273 # Per bank write bursts -system.physmem.perBankRdBursts::14 6335 # Per bank write bursts -system.physmem.perBankRdBursts::15 6042 # Per bank write bursts -system.physmem.perBankWrBursts::0 2746 # Per bank write bursts -system.physmem.perBankWrBursts::1 2526 # Per bank write bursts -system.physmem.perBankWrBursts::2 2727 # Per bank write bursts -system.physmem.perBankWrBursts::3 3010 # Per bank write bursts -system.physmem.perBankWrBursts::4 2533 # Per bank write bursts -system.physmem.perBankWrBursts::5 2968 # Per bank write bursts -system.physmem.perBankWrBursts::6 2994 # Per bank write bursts -system.physmem.perBankWrBursts::7 2697 # Per bank write bursts -system.physmem.perBankWrBursts::8 3092 # Per bank write bursts -system.physmem.perBankWrBursts::9 2617 # Per bank write bursts -system.physmem.perBankWrBursts::10 2969 # Per bank write bursts -system.physmem.perBankWrBursts::11 2522 # Per bank write bursts -system.physmem.perBankWrBursts::12 2428 # Per bank write bursts -system.physmem.perBankWrBursts::13 2745 # Per bank write bursts +system.physmem.perBankRdBursts::14 6336 # Per bank write bursts +system.physmem.perBankRdBursts::15 6041 # Per bank write bursts +system.physmem.perBankWrBursts::0 2748 # Per bank write bursts +system.physmem.perBankWrBursts::1 2555 # Per bank write bursts +system.physmem.perBankWrBursts::2 2839 # Per bank write bursts +system.physmem.perBankWrBursts::3 3065 # Per bank write bursts +system.physmem.perBankWrBursts::4 2620 # Per bank write bursts +system.physmem.perBankWrBursts::5 2963 # Per bank write bursts +system.physmem.perBankWrBursts::6 2854 # Per bank write bursts +system.physmem.perBankWrBursts::7 2670 # Per bank write bursts +system.physmem.perBankWrBursts::8 3259 # Per bank write bursts +system.physmem.perBankWrBursts::9 2627 # Per bank write bursts +system.physmem.perBankWrBursts::10 3029 # Per bank write bursts +system.physmem.perBankWrBursts::11 2539 # Per bank write bursts +system.physmem.perBankWrBursts::12 2431 # Per bank write bursts +system.physmem.perBankWrBursts::13 2744 # Per bank write bursts system.physmem.perBankWrBursts::14 2948 # Per bank write bursts -system.physmem.perBankWrBursts::15 2737 # Per bank write bursts +system.physmem.perBankWrBursts::15 2734 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 1841681402500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 1842660063500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 97691 # Read request sizes (log2) +system.physmem.readPktSize::6 98065 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44282 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 495 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44647 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8078 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 373 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -153,13 +153,13 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see @@ -168,376 +168,368 @@ system.physmem.wrQLenPdf::11 35 # Wh system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 15110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 511.250298 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 300.938727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 421.415256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3831 25.35% 25.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2740 18.13% 43.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1074 7.11% 50.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 703 4.65% 55.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 520 3.44% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 360 2.38% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 225 1.49% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 226 1.50% 64.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5431 35.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 15110 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.985220 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 914.533013 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2569 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 417.545272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 236.447646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 397.078129 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6878 31.45% 31.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4663 21.32% 52.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1715 7.84% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 976 4.46% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 897 4.10% 69.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 495 2.26% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 365 1.67% 73.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 382 1.75% 74.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5497 25.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21868 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.446906 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 907.093650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2616 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2571 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.214702 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.506808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.396297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 28 1.09% 1.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 8 0.31% 1.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 1 0.04% 1.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 1.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 1.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.04% 1.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.08% 1.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 2 0.08% 1.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 1 0.04% 1.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 1 0.04% 1.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1798 69.93% 71.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 69 2.68% 74.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 74 2.88% 77.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 370 14.39% 91.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 34 1.32% 93.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.74% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 12 0.47% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 7 0.27% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 34 1.32% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 15 0.58% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.19% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.58% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 11 0.43% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 14 0.54% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.16% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 5 0.19% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 6 0.23% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.12% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.04% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.04% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.08% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 2 0.08% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 3 0.12% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.16% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 3 0.12% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 5 0.19% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 2 0.08% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 2 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 2 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 2 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2571 # Writes before turning the bus around for reads -system.physmem.totQLat 3372876000 # Total ticks spent queuing -system.physmem.totMemAccLat 5050468500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 488355000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1189237500 # Total ticks spent accessing banks -system.physmem.avgQLat 34533.03 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 12175.95 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 2618 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.045455 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.392541 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.534822 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1 25 0.95% 0.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2-3 9 0.34% 1.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-5 2 0.08% 1.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6-7 3 0.11% 1.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-9 2 0.08% 1.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10-11 1 0.04% 1.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14-15 1 0.04% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 1908 72.88% 74.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 472 18.03% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 41 1.57% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 56 2.14% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 26 0.99% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 16 0.61% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 10 0.38% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 14 0.53% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 7 0.27% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 1 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 3 0.11% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 4 0.15% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.04% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 11 0.42% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 1 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2618 # Writes before turning the bus around for reads +system.physmem.totQLat 2942753000 # Total ticks spent queuing +system.physmem.totMemAccLat 4781096750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 490225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30014.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51708.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48764.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.13 # Average write queue length when enqueuing -system.physmem.readRowHits 85060 # Number of row buffer hits during reads -system.physmem.writeRowHits 35225 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.22 # Average write queue length when enqueuing +system.physmem.readRowHits 85384 # Number of row buffer hits during reads +system.physmem.writeRowHits 35418 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.55 # Row buffer hit rate for writes -system.physmem.avgGap 12972053.86 # Average gap between requests -system.physmem.pageHitRate 84.74 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19527312 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44337 # Transaction distribution -system.membus.trans_dist::ReadResp 44306 # Transaction distribution -system.membus.trans_dist::WriteReq 3779 # Transaction distribution -system.membus.trans_dist::WriteResp 3779 # Transaction distribution -system.membus.trans_dist::Writeback 44282 # Transaction distribution -system.membus.trans_dist::UpgradeReq 42 # Transaction distribution -system.membus.trans_dist::UpgradeResp 42 # Transaction distribution -system.membus.trans_dist::ReadExReq 56476 # Transaction distribution -system.membus.trans_dist::ReadExResp 56476 # Transaction distribution -system.membus.trans_dist::BadAddressError 31 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13428 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 62 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 202679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 253391 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15748 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6926464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6942212 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9102020 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35972872 # Total data (bytes) -system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12574500 # Layer occupancy (ticks) +system.physmem.writeRowHitRate 79.33 # Row buffer hit rate for writes +system.physmem.avgGap 12911738.77 # Average gap between requests +system.physmem.pageHitRate 84.66 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1768578867000 # Time in different power states +system.physmem.memoryStateTime::REF 61564100000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 13524513000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 19519346 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44419 # Transaction distribution +system.membus.trans_dist::ReadResp 44389 # Transaction distribution +system.membus.trans_dist::WriteReq 3765 # Transaction distribution +system.membus.trans_dist::WriteResp 3765 # Transaction distribution +system.membus.trans_dist::Writeback 44647 # Transaction distribution +system.membus.trans_dist::UpgradeReq 46 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46 # Transaction distribution +system.membus.trans_dist::ReadExReq 56746 # Transaction distribution +system.membus.trans_dist::ReadExResp 56746 # Transaction distribution +system.membus.trans_dist::BadAddressError 30 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13356 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 202958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 51481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 254439 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15715 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6940992 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6956707 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2192576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2192576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9149283 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35977232 # Total data (bytes) +system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12506000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 513408250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 516947250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 40000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 37500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 761373958 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 762242703 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 153163000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 155440000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337430 # number of replacements -system.l2c.tags.tagsinuse 65422.148259 # Cycle average of tags in use -system.l2c.tags.total_refs 2473441 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402593 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.143775 # Average number of references to valid blocks. +system.l2c.tags.replacements 337456 # number of replacements +system.l2c.tags.tagsinuse 65422.465864 # Cycle average of tags in use +system.l2c.tags.total_refs 2473240 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402619 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.142879 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54880.563920 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2458.853214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2711.613848 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 517.416897 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 618.305247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2161.633442 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2073.761691 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.837411 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.037519 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007895 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009435 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032984 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.031643 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998263 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54816.531838 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2443.286445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2722.487240 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 580.950396 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 624.587700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2109.099829 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2125.522416 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.836434 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008865 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009530 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.032433 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998268 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1047 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5588 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2973 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55387 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1026 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5608 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55383 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26153114 # Number of tag accesses -system.l2c.tags.data_accesses 26153114 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 521024 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493028 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 125251 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 84722 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 291154 # 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number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 93137 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26426 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67420 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186983 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 521024 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 586165 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 125251 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 111148 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 291154 # 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average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68850.496873 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63001.464470 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60133.983983 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55109.460870 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63495.118074 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62277.572254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59199.154841 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60133.983983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55109.460870 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63495.118074 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62277.572254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59199.154841 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -648,14 +640,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254944 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.262765 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694864715000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254944 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078434 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078434 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694865594000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.262765 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078923 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078923 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -669,14 +661,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5375933278 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5375933278 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5385236741 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5385236741 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5385236741 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5385236741 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9418062 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9418062 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5145673458 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5145673458 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5155091520 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5155091520 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5155091520 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5155091520 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -693,56 +685,56 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 129378.448161 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 129378.448161 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 129064.990797 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129064.990797 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 129064.990797 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129064.990797 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 158120 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54439.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54439.664740 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 123836.962312 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123836.962312 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 123549.227561 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123549.227561 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 123549.227561 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123549.227561 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 151978 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11558 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11614 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.680568 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.085759 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4496386278 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4496386278 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 4502100741 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4502100741 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 4502100741 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4502100741 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 266121.346946 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 266121.346946 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 265375.817330 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 265375.817330 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 265375.817330 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 265375.817330 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 17152 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 17152 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 17222 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17222 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17222 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17222 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5777062 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5777062 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4252886458 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4252886458 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4258663520 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4258663520 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4258663520 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4258663520 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.412784 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.412784 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.412750 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.412750 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82529.457143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82529.457143 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247952.801889 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247952.801889 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -760,22 +752,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4928404 # DTB read hits +system.cpu0.dtb.read_hits 4916751 # DTB read hits system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 428233 # DTB read accesses -system.cpu0.dtb.write_hits 3518338 # DTB write hits +system.cpu0.dtb.write_hits 3511411 # DTB write hits system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 163777 # DTB write accesses -system.cpu0.dtb.data_hits 8446742 # DTB hits +system.cpu0.dtb.data_hits 8428162 # DTB hits system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations system.cpu0.dtb.data_accesses 592010 # DTB accesses -system.cpu0.itb.fetch_hits 2763962 # ITB hits +system.cpu0.itb.fetch_hits 2761691 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2766996 # ITB accesses +system.cpu0.itb.fetch_accesses 2764725 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -788,52 +780,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928692350 # number of cpu cycles simulated +system.cpu0.numCycles 928579533 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 34273964 # Number of instructions committed -system.cpu0.committedOps 34273964 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 32130742 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169948 # Number of float alu accesses -system.cpu0.num_func_calls 813899 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4819398 # number of instructions that are conditional controls -system.cpu0.num_int_insts 32130742 # number of integer instructions -system.cpu0.num_fp_insts 169948 # number of float instructions -system.cpu0.num_int_register_reads 45237353 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23423813 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87792 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89256 # number of times the floating registers were written -system.cpu0.num_mem_refs 8476912 # number of memory refs -system.cpu0.num_load_insts 4949798 # Number of load instructions -system.cpu0.num_store_insts 3527114 # Number of store instructions -system.cpu0.num_idle_cycles 904863863.789935 # Number of idle cycles -system.cpu0.num_busy_cycles 23828486.210065 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025658 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974342 # Percentage of idle cycles -system.cpu0.Branches 5897308 # Number of branches fetched +system.cpu0.committedInsts 33817210 # Number of instructions committed +system.cpu0.committedOps 33817210 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31677975 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169596 # Number of float alu accesses +system.cpu0.num_func_calls 812570 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4683135 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31677975 # number of integer instructions +system.cpu0.num_fp_insts 169596 # number of float instructions +system.cpu0.num_int_register_reads 44495639 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23114141 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87595 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89102 # number of times the floating registers were written +system.cpu0.num_mem_refs 8458293 # number of memory refs +system.cpu0.num_load_insts 4938120 # Number of load instructions +system.cpu0.num_store_insts 3520173 # Number of store instructions +system.cpu0.num_idle_cycles 904460149.841647 # Number of idle cycles +system.cpu0.num_busy_cycles 24119383.158353 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025974 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974026 # Percentage of idle cycles +system.cpu0.Branches 5759211 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1618304 4.78% 4.78% # Class of executed instruction +system.cpu0.op_class::IntAlu 23033604 68.10% 72.88% # Class of executed instruction +system.cpu0.op_class::IntMult 32432 0.10% 72.98% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.98% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12174 0.04% 73.01% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 73.01% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 73.01% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 73.01% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1606 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::MemRead 5072252 15.00% 88.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 3523323 10.42% 98.43% # Class of executed instruction +system.cpu0.op_class::IprAccess 530494 1.57% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 33824189 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6415 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211374 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74800 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6417 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211389 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182573 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73433 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148948 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819462416000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38889500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365010500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22826642500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842692958500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1820445327500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38826000 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365496000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22821970000 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1843671619500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -869,33 +896,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175314 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192229 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1907 -system.cpu0.kern.mode_good::user 1737 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches +system.cpu0.kern.callpal::total 192243 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 +system.cpu0.kern.mode_good::user 1739 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29759204500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2578304000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810355445500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29786667000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2578002500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1811306945500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -927,458 +954,460 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110509038 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 784786 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 784740 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3779 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3779 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372271 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution +system.toL2Bus.throughput 110441912 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 785832 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 785787 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3765 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3765 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372222 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150355 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133459 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 31 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2216252 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27078976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55338308 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82417284 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203623496 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10816 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2138093500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150766 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133614 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 848294 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370287 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2218581 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27145024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55347363 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82492387 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203607824 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10880 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2138460500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1905810483 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1910550337 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2232783145 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2233740752 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469145 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 3004 # Transaction distribution -system.iobus.trans_dist::ReadResp 3004 # Transaction distribution -system.iobus.trans_dist::WriteReq 20675 # Transaction distribution -system.iobus.trans_dist::WriteResp 20675 # Transaction distribution +system.iobus.throughput 1468369 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2983 # Transaction distribution +system.iobus.trans_dist::ReadResp 2983 # Transaction distribution +system.iobus.trans_dist::WriteReq 20917 # Transaction distribution +system.iobus.trans_dist::WriteResp 20917 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8488 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8382 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2408 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13428 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34444 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34444 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47800 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4191 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1098540 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2707184 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1099184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1099184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1114899 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2707192 # Total data (bytes) system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6326000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6246000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1819000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 154493741 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 156921520 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9649000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9591000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17628000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17887000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 951123 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.189701 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 44044625 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 951634 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 46.283156 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10406456250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 252.370031 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 94.623296 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.196374 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.492910 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.184811 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.320696 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998417 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 950608 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.189792 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43374256 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 951119 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.603396 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10403794250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.164377 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 98.345392 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 161.680023 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490555 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.192081 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.315781 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998418 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45964526 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45964526 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 33752258 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8060384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2231983 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44044625 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33752258 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8060384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2231983 # 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average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.178497 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12199.372070 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.178497 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12199.372070 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.178497 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1392490 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13295207 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393002 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.544284 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1392627 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13291421 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393139 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.540628 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 249.168016 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 132.479618 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 130.350177 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.486656 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.258749 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.254590 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 251.446594 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 129.524111 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.027107 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.491107 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.252977 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255912 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63289936 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63289936 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4090319 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1090270 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2387407 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7567996 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3221527 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 836656 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1285562 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5343745 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117421 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19406 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47293 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184120 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126604 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21447 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51238 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199289 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7311846 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1926926 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3672969 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12911741 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7311846 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1926926 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3672969 # number of overall hits -system.cpu0.dcache.overall_hits::total 12911741 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 721875 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 99348 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 531757 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1352980 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169301 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 44567 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 593518 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 807386 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9749 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2170 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6797 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18716 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63293161 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63293161 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4078776 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1086651 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2400445 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7565872 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3215108 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 831895 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1295006 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5342009 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117088 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19357 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47741 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184186 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126296 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21393 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51592 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7293884 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1918546 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3695451 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12907881 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7293884 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1918546 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3695451 # number of overall hits +system.cpu0.dcache.overall_hits::total 12907881 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 722029 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 99123 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 533441 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1354593 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 169072 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44217 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 597048 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 810337 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9771 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2167 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6787 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18725 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 891176 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 143915 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1125275 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2160366 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 891176 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 143915 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1125275 # number of overall misses -system.cpu0.dcache.overall_misses::total 2160366 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2256659500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9313664253 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11570323753 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1642839260 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18220741943 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19863581203 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28601250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 101979747 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 130580997 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 891101 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 143340 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1130489 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2164930 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 891101 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 143340 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1130489 # number of overall misses +system.cpu0.dcache.overall_misses::total 2164930 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2252505500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9329560863 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11582066363 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1640569260 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17995165012 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19635734272 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28565250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 103170749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 131735999 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3899498760 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27534406196 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31433904956 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3899498760 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27534406196 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31433904956 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4812194 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1189618 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2919164 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8920976 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3390828 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 881223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1879080 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6151131 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127170 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21576 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54090 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 202836 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126604 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21447 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51239 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199290 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8203022 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2070841 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4798244 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15072107 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8203022 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2070841 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4798244 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15072107 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150010 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083513 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182161 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151663 # 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number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296463000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 608356000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 365040500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 428466000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 793506500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 661503500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 740359000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1401862500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083594 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085963 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039385 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050574 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047182 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021659 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100575 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099593 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037257 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000020 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050470 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047127 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021680 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100678 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099820 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037504 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069496 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070997 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032150 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069496 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070997 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032150 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20639.031485 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16811.977655 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17894.118381 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34679.443086 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29666.299104 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31343.317591 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11179.608295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12106.553369 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11840.380177 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032158 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032158 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20648.179535 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16797.792678 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17884.127168 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34917.310989 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29164.763848 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31071.742023 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11181.241347 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12266.948374 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.785808 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24987.007887 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20157.361413 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21591.728791 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24987.007887 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20157.361413 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21591.728791 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1393,22 +1422,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1209129 # DTB read hits +system.cpu1.dtb.read_hits 1205243 # DTB read hits system.cpu1.dtb.read_misses 1367 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations system.cpu1.dtb.read_accesses 142945 # DTB read accesses -system.cpu1.dtb.write_hits 903134 # DTB write hits +system.cpu1.dtb.write_hits 897974 # DTB write hits system.cpu1.dtb.write_misses 185 # DTB write misses system.cpu1.dtb.write_acv 23 # DTB write access violations system.cpu1.dtb.write_accesses 58533 # DTB write accesses -system.cpu1.dtb.data_hits 2112263 # DTB hits +system.cpu1.dtb.data_hits 2103217 # DTB hits system.cpu1.dtb.data_misses 1552 # DTB misses system.cpu1.dtb.data_acv 57 # DTB access violations system.cpu1.dtb.data_accesses 201478 # DTB accesses -system.cpu1.itb.fetch_hits 860790 # ITB hits +system.cpu1.itb.fetch_hits 859888 # ITB hits system.cpu1.itb.fetch_misses 693 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 861483 # ITB accesses +system.cpu1.itb.fetch_accesses 860581 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1421,29 +1450,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953612854 # number of cpu cycles simulated +system.cpu1.numCycles 953622390 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8186270 # Number of instructions committed -system.cpu1.committedOps 8186270 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7639715 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45422 # Number of float alu accesses -system.cpu1.num_func_calls 213980 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1089106 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7639715 # number of integer instructions -system.cpu1.num_fp_insts 45422 # number of float instructions -system.cpu1.num_int_register_reads 10757840 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5542682 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24502 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24833 # number of times the floating registers were written -system.cpu1.num_mem_refs 2119540 # number of memory refs -system.cpu1.num_load_insts 1214044 # Number of load instructions -system.cpu1.num_store_insts 905496 # Number of store instructions -system.cpu1.num_idle_cycles 923510145.865154 # Number of idle cycles -system.cpu1.num_busy_cycles 30102708.134846 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031567 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968433 # Percentage of idle cycles -system.cpu1.Branches 1370105 # Number of branches fetched +system.cpu1.committedInsts 7961300 # Number of instructions committed +system.cpu1.committedOps 7961300 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7416956 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45099 # Number of float alu accesses +system.cpu1.num_func_calls 213358 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1019863 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7416956 # number of integer instructions +system.cpu1.num_fp_insts 45099 # number of float instructions +system.cpu1.num_int_register_reads 10395465 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5394572 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24307 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24707 # number of times the floating registers were written +system.cpu1.num_mem_refs 2110464 # number of memory refs +system.cpu1.num_load_insts 1210140 # Number of load instructions +system.cpu1.num_store_insts 900324 # Number of store instructions +system.cpu1.num_idle_cycles 923192460.103175 # Number of idle cycles +system.cpu1.num_busy_cycles 30429929.896825 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031910 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968090 # Percentage of idle cycles +system.cpu1.Branches 1300058 # Number of branches fetched +system.cpu1.op_class::No_OpClass 413905 5.20% 5.20% # Class of executed instruction +system.cpu1.op_class::IntAlu 5261386 66.07% 71.27% # Class of executed instruction +system.cpu1.op_class::IntMult 8416 0.11% 71.38% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.38% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5003 0.06% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::MemRead 1239389 15.56% 87.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 901545 11.32% 98.34% # Class of executed instruction +system.cpu1.op_class::IprAccess 132455 1.66% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 7962909 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1461,35 +1525,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9158053 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8481927 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 123683 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7604727 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6560922 # Number of BTB hits +system.cpu2.branchPred.lookups 9178120 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8499449 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 123200 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7695654 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6571533 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 86.274261 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 280761 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13305 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.392781 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 282084 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 12342 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3175061 # DTB read hits -system.cpu2.dtb.read_misses 11717 # DTB read misses +system.cpu2.dtb.read_hits 3191151 # DTB read hits +system.cpu2.dtb.read_misses 11650 # DTB read misses system.cpu2.dtb.read_acv 122 # DTB read access violations -system.cpu2.dtb.read_accesses 217137 # DTB read accesses -system.cpu2.dtb.write_hits 2001578 # DTB write hits -system.cpu2.dtb.write_misses 2618 # DTB write misses -system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 82142 # DTB write accesses -system.cpu2.dtb.data_hits 5176639 # DTB hits -system.cpu2.dtb.data_misses 14335 # DTB misses -system.cpu2.dtb.data_acv 228 # DTB access violations -system.cpu2.dtb.data_accesses 299279 # DTB accesses -system.cpu2.itb.fetch_hits 368924 # ITB hits -system.cpu2.itb.fetch_misses 5740 # ITB misses -system.cpu2.itb.fetch_acv 243 # ITB acv -system.cpu2.itb.fetch_accesses 374664 # ITB accesses +system.cpu2.dtb.read_accesses 216295 # DTB read accesses +system.cpu2.dtb.write_hits 2013879 # DTB write hits +system.cpu2.dtb.write_misses 2626 # DTB write misses +system.cpu2.dtb.write_acv 104 # DTB write access violations +system.cpu2.dtb.write_accesses 81955 # DTB write accesses +system.cpu2.dtb.data_hits 5205030 # DTB hits +system.cpu2.dtb.data_misses 14276 # DTB misses +system.cpu2.dtb.data_acv 226 # DTB access violations +system.cpu2.dtb.data_accesses 298250 # DTB accesses +system.cpu2.itb.fetch_hits 370022 # ITB hits +system.cpu2.itb.fetch_misses 5569 # ITB misses +system.cpu2.itb.fetch_acv 246 # ITB acv +system.cpu2.itb.fetch_accesses 375591 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1502,270 +1566,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31279022 # number of cpu cycles simulated +system.cpu2.numCycles 31335688 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8287542 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37055340 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9158053 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6841683 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8878582 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 603474 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9658598 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 9919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63764 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 87901 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 585 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2543899 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 85179 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27382085 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.353269 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.291783 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8331242 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37157937 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9178120 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6853617 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8899845 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 601293 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9656250 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 62491 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87858 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 258 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2554389 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 85437 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27441825 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.354062 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.292990 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18503503 67.58% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 267960 0.98% 68.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 427466 1.56% 70.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5038940 18.40% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 758703 2.77% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 165190 0.60% 91.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 190909 0.70% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 425900 1.56% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1603514 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18541980 67.57% 67.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269924 0.98% 68.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 430608 1.57% 70.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5041958 18.37% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 762355 2.78% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165901 0.60% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 191104 0.70% 92.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 428586 1.56% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1609409 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27382085 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.292786 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.184671 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8439244 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9737555 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8269995 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 308345 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 381075 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165536 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12831 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36664015 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39751 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 381075 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8796739 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2804819 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5741072 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8142606 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1269911 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35531036 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2469 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 231647 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 446543 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23808302 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44475961 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44419812 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52401 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22020270 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1788032 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 498319 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 58753 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3705896 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3335757 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2091143 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 366529 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 285241 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 33051386 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 616780 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32598005 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 35098 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2143170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1082478 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 435207 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27382085 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.190487 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.575531 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27441825 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.292897 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.185802 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8480872 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9736053 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8290323 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308881 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 379812 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165178 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12521 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36770346 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39237 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 379812 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8839767 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2783657 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5759458 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8162466 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1270789 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35635356 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2433 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 230404 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 445807 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23881418 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44614948 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44558512 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52675 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22098169 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1783249 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 500707 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 58904 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3714662 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3352351 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2102718 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 368829 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 261079 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33144056 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 620028 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32694445 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 35243 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2135274 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1079120 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 437376 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27441825 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.191409 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.576872 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15085778 55.09% 55.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3054879 11.16% 66.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1548873 5.66% 71.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5868849 21.43% 93.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 901287 3.29% 96.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 476925 1.74% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 288026 1.05% 99.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 138840 0.51% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18628 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15111094 55.07% 55.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3067205 11.18% 66.24% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1556680 5.67% 71.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5872597 21.40% 93.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 904620 3.30% 96.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 481374 1.75% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286422 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 142457 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 19376 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27382085 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27441825 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33655 13.83% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 111431 45.78% 59.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 98340 40.40% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33866 13.68% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112679 45.53% 59.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100956 40.79% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26953534 82.68% 82.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 19910 0.06% 82.75% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8410 0.03% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3301438 10.13% 92.91% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2024047 6.21% 99.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 287006 0.88% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27019317 82.64% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20282 0.06% 82.71% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.71% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8426 0.03% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3318398 10.15% 92.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2035966 6.23% 99.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288396 0.88% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32598005 # Type of FU issued -system.cpu2.iq.rate 1.042168 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 243426 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007468 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92623863 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35700994 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32205742 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 232756 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114085 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110215 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32717888 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121103 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 185687 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32694445 # Type of FU issued +system.cpu2.iq.rate 1.043361 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 247501 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007570 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92879210 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35788610 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32300559 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234249 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114557 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110717 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32817438 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122068 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 187489 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 410803 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1083 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3827 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 157383 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 409544 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 984 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3929 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 155635 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4176 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 27619 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4136 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 26287 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 381075 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2023183 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 204607 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34934170 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 220301 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3335757 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2091143 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 547666 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 141469 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2123 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3827 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63090 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.iewSquashCycles 379812 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2011431 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204809 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35034427 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 220433 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3352351 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2102718 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 550753 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 142349 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2108 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3929 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63003 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 127121 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 190211 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32442083 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3195032 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 155922 # Number of squashed instructions skipped in execute +system.cpu2.iew.branchMispredicts 190124 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32537756 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3211080 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 156689 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1266004 # number of nop insts executed -system.cpu2.iew.exec_refs 5203645 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7597485 # Number of branches executed -system.cpu2.iew.exec_stores 2008613 # Number of stores executed -system.cpu2.iew.exec_rate 1.037183 # Inst execution rate -system.cpu2.iew.wb_sent 32348485 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32315957 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18839799 # num instructions producing a value -system.cpu2.iew.wb_consumers 22025525 # num instructions consuming a value +system.cpu2.iew.exec_nop 1270343 # number of nop insts executed +system.cpu2.iew.exec_refs 5232018 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7610407 # Number of branches executed +system.cpu2.iew.exec_stores 2020938 # Number of stores executed +system.cpu2.iew.exec_rate 1.038361 # Inst execution rate +system.cpu2.iew.wb_sent 32444193 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32411276 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18891849 # num instructions producing a value +system.cpu2.iew.wb_consumers 22089477 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.033151 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.855362 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.034325 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.855242 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2315429 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 181573 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 175784 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27001010 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.206363 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.845727 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2305077 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182652 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 175963 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27062013 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.207707 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.849174 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16087817 59.58% 59.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2320535 8.59% 68.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1221811 4.53% 72.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5612171 20.79% 93.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 500601 1.85% 95.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 184383 0.68% 96.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 174610 0.65% 96.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 192284 0.71% 97.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 706798 2.62% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16121128 59.57% 59.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2330838 8.61% 68.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1224813 4.53% 72.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5615394 20.75% 93.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 503174 1.86% 95.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185895 0.69% 96.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 176248 0.65% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179513 0.66% 97.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 725010 2.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27001010 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32573021 # Number of instructions committed -system.cpu2.commit.committedOps 32573021 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27062013 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32682976 # Number of instructions committed +system.cpu2.commit.committedOps 32682976 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4858714 # Number of memory references committed -system.cpu2.commit.loads 2924954 # Number of loads committed -system.cpu2.commit.membars 63567 # Number of memory barriers committed -system.cpu2.commit.branches 7451291 # Number of branches committed -system.cpu2.commit.fp_insts 109021 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31134232 # Number of committed integer instructions. -system.cpu2.commit.function_calls 227850 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 706798 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4889890 # Number of memory references committed +system.cpu2.commit.loads 2942807 # Number of loads committed +system.cpu2.commit.membars 63964 # Number of memory barriers committed +system.cpu2.commit.branches 7465437 # Number of branches committed +system.cpu2.commit.fp_insts 109562 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31237309 # Number of committed integer instructions. +system.cpu2.commit.function_calls 229028 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1167807 3.57% 3.57% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26241804 80.29% 83.87% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 19886 0.06% 83.93% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 8426 0.03% 83.95% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.95% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.95% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.95% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3006771 9.20% 93.16% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 1948666 5.96% 99.12% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 288396 0.88% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 32682976 # Class of committed instruction +system.cpu2.commit.bw_lim_events 725010 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 61108801 # The number of ROB reads -system.cpu2.rob.rob_writes 70157468 # The number of ROB writes -system.cpu2.timesIdled 244589 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3896937 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746488839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31413101 # Number of Instructions Simulated -system.cpu2.committedOps 31413101 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31413101 # Number of Instructions Simulated -system.cpu2.cpi 0.995732 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.995732 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.004287 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.004287 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42678646 # number of integer regfile reads -system.cpu2.int_regfile_writes 22701958 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67399 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67744 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5400058 # number of misc regfile reads -system.cpu2.misc_regfile_writes 256035 # number of misc regfile writes +system.cpu2.rob.rob_reads 61251181 # The number of ROB reads +system.cpu2.rob.rob_writes 70355425 # The number of ROB writes +system.cpu2.timesIdled 245354 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3893863 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1748379581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31517609 # Number of Instructions Simulated +system.cpu2.committedOps 31517609 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31517609 # Number of Instructions Simulated +system.cpu2.cpi 0.994228 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.994228 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.005806 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.005806 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42812311 # number of integer regfile reads +system.cpu2.int_regfile_writes 22772429 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67678 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67966 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5406368 # number of misc regfile reads +system.cpu2.misc_regfile_writes 257490 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |