diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
3 files changed, 4528 insertions, 3695 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 56627054e..8de825134 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896442 # Number of seconds simulated -sim_ticks 1896441913500 # Number of ticks simulated -final_tick 1896441913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903702 # Number of seconds simulated +sim_ticks 1903702212500 # Number of ticks simulated +final_tick 1903702212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132187 # Simulator instruction rate (inst/s) -host_op_rate 132187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4418345683 # Simulator tick rate (ticks/s) -host_mem_usage 311512 # Number of bytes of host memory used -host_seconds 429.22 # Real time elapsed on the host -sim_insts 56737124 # Number of instructions simulated -sim_ops 56737124 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 937984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24915648 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 39872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 337088 # Number of bytes read from this memory -system.physmem.bytes_read::total 28881280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 937984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 39872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7850944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7850944 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389307 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5267 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451270 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122671 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122671 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 494602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13138102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1397716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 177748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15229193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 494602 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4139828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4139828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4139828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 494602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13138102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 177748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19369021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451270 # Total number of read requests seen -system.physmem.writeReqs 122671 # Total number of write requests seen -system.physmem.cpureqs 578881 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28881280 # Total number of bytes read from memory -system.physmem.bytesWritten 7850944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28881280 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7850944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4936 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28331 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28037 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28154 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27902 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28043 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7715 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7756 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7541 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7897 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7761 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7706 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7423 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis +host_inst_rate 94355 # Simulator instruction rate (inst/s) +host_op_rate 94355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3162860632 # Simulator tick rate (ticks/s) +host_mem_usage 314400 # Number of bytes of host memory used +host_seconds 601.89 # Real time elapsed on the host +sim_insts 56791782 # Number of instructions simulated +sim_ops 56791782 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 898816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24768192 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 430592 # Number of bytes read from this memory +system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 898816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7790720 # Number of bytes written to this memory +system.physmem.bytes_written::total 7790720 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387003 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6728 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121730 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121730 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 472141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13010539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 226187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15141931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 472141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4092405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4092405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4092405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 472141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13010539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 226187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19234336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450402 # Total number of read requests seen +system.physmem.writeReqs 121730 # Total number of write requests seen +system.physmem.cpureqs 577215 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28825728 # Total number of bytes read from memory +system.physmem.bytesWritten 7790720 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7790720 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5081 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28209 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27366 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28620 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7522 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7235 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7644 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6897 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7004 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7923 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7633 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8079 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry -system.physmem.totGap 1896440622000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry +system.physmem.totGap 1903701167000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451270 # Categorize read packet sizes +system.physmem.readPktSize::6 450402 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 122671 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 320077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59739 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121730 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -138,224 +138,395 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.physmem.totQLat 7836942250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15642141000 # Sum of mem lat for all requests -system.physmem.totBusLat 2256015000 # Total cycles spent in databus access -system.physmem.totBankLat 5549183750 # Total cycles spent in bank access -system.physmem.avgQLat 17368.99 # Average queueing delay per request -system.physmem.avgBankLat 12298.64 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 910.430717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.153261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2362.806871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14303 35.57% 35.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6082 15.12% 50.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3751 9.33% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2511 6.24% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1745 4.34% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1426 3.55% 74.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1071 2.66% 76.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 838 2.08% 78.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 669 1.66% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 518 1.29% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 558 1.39% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 522 1.30% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 270 0.67% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 231 0.57% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 190 0.47% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 283 0.70% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 119 0.30% 87.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 115 0.29% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 106 0.26% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 202 0.50% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 170 0.42% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 105 0.26% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 478 1.19% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 629 1.56% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 105 0.26% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 36 0.09% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 35 0.09% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 97 0.24% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 7 0.02% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 13 0.03% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 52 0.13% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 1 0.00% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.76% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40212 # Bytes accessed per row activation +system.physmem.totQLat 6402871500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13861687750 # Sum of mem lat for all requests +system.physmem.totBusLat 2251705000 # Total cycles spent in databus access +system.physmem.totBankLat 5207111250 # Total cycles spent in bank access +system.physmem.avgQLat 14217.83 # Average queueing delay per request +system.physmem.avgBankLat 11562.60 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34667.64 # Average memory access latency -system.physmem.avgRdBW 15.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.14 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30780.43 # Average memory access latency +system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.84 # Average write queue length over time -system.physmem.readRowHits 423356 # Number of row buffer hits during reads -system.physmem.writeRowHits 94009 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.64 # Row buffer hit rate for writes -system.physmem.avgGap 3304243.16 # Average gap between requests -system.l2c.replacements 344349 # number of replacements -system.l2c.tagsinuse 65273.956353 # Cycle average of tags in use -system.l2c.total_refs 2577923 # Total number of references to valid blocks. -system.l2c.sampled_refs 409542 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.294649 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53748.349121 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5295.726441 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5975.264441 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 194.705269 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 59.911080 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820135 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080806 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006036 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133237 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940601 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795359 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.892390 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914343 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949219 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.931953 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428583 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.186907 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.401253 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.063410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165793 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016172 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005427 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.063410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165793 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50443.521644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72273.242630 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 51731.979750 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10071.008172 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.064545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.386869 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.803922 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.115226 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.849735 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68696.865849 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 97466.194672 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70212.348628 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -493,39 +664,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.474409 # Cycle average of tags in use +system.iocache.replacements 41695 # number of replacements +system.iocache.tagsinuse 0.492474 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1705455708000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.474409 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029651 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029651 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.warmup_cycle 1710349466000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.492474 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030780 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030780 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21041998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21041998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10633425431 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10633425431 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10654467429 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10654467429 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10654467429 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10654467429 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21568883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21568883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10518241771 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10518241771 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10539810654 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10539810654 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10539810654 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10539810654 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -534,40 +705,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120931.022989 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255906.464936 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255906.464936 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255343.608997 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255343.608997 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285994 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123250.760000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123250.760000 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 253134.428451 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 253134.428451 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 252589.705802 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 252589.705802 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 276539 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27316 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27281 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.469835 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.136689 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11993249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8471449424 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8471449424 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8483442673 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8483442673 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8483442673 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8483442673 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12468133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8356835276 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8356835276 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8369303409 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8369303409 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8369303409 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8369303409 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -576,14 +747,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68926.718391 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68926.718391 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203875.852522 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203875.852522 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71246.474286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71246.474286 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 201117.522045 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 201117.522045 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -597,35 +768,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12584062 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10588139 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 341886 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8301483 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5323497 # Number of BTB hits +system.cpu0.branchPred.lookups 12372167 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10430268 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 327512 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8051050 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5251093 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.127060 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 804999 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33376 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.222462 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 787082 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28165 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8950032 # DTB read hits -system.cpu0.dtb.read_misses 34820 # DTB read misses -system.cpu0.dtb.read_acv 539 # DTB read access violations -system.cpu0.dtb.read_accesses 674081 # DTB read accesses -system.cpu0.dtb.write_hits 5877992 # DTB write hits -system.cpu0.dtb.write_misses 8366 # DTB write misses -system.cpu0.dtb.write_acv 348 # DTB write access violations -system.cpu0.dtb.write_accesses 235610 # DTB write accesses -system.cpu0.dtb.data_hits 14828024 # DTB hits -system.cpu0.dtb.data_misses 43186 # DTB misses -system.cpu0.dtb.data_acv 887 # DTB access violations -system.cpu0.dtb.data_accesses 909691 # DTB accesses -system.cpu0.itb.fetch_hits 1040487 # ITB hits -system.cpu0.itb.fetch_misses 31672 # ITB misses -system.cpu0.itb.fetch_acv 1020 # ITB acv -system.cpu0.itb.fetch_accesses 1072159 # ITB accesses +system.cpu0.dtb.read_hits 8811099 # DTB read hits +system.cpu0.dtb.read_misses 30390 # DTB read misses +system.cpu0.dtb.read_acv 555 # DTB read access violations +system.cpu0.dtb.read_accesses 626499 # DTB read accesses +system.cpu0.dtb.write_hits 5759352 # DTB write hits +system.cpu0.dtb.write_misses 7345 # DTB write misses +system.cpu0.dtb.write_acv 331 # DTB write access violations +system.cpu0.dtb.write_accesses 208988 # DTB write accesses +system.cpu0.dtb.data_hits 14570451 # DTB hits +system.cpu0.dtb.data_misses 37735 # DTB misses +system.cpu0.dtb.data_acv 886 # DTB access violations +system.cpu0.dtb.data_accesses 835487 # DTB accesses +system.cpu0.itb.fetch_hits 988720 # ITB hits +system.cpu0.itb.fetch_misses 28459 # ITB misses +system.cpu0.itb.fetch_acv 940 # ITB acv +system.cpu0.itb.fetch_accesses 1017179 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,269 +809,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 103751291 # number of cpu cycles simulated +system.cpu0.numCycles 113576100 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25592047 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 64430414 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12584062 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6128496 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12114182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1732019 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37108557 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 208707 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 355709 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 408 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7808396 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 232068 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76528583 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.841913 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.179850 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24795587 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63494847 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12372167 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6038175 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11937811 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1694344 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37245698 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31806 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195246 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 359396 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7671411 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 221670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 75653727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.839282 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.177028 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64414401 84.17% 84.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 777905 1.02% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1574114 2.06% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 716339 0.94% 88.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2604704 3.40% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 529326 0.69% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 586322 0.77% 93.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 831890 1.09% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4493582 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63715916 84.22% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 763032 1.01% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1559362 2.06% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 696709 0.92% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2577784 3.41% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 516509 0.68% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 573501 0.76% 93.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 819035 1.08% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4431879 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76528583 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121291 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.621008 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26850978 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36641611 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11018000 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 937421 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1080572 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 523116 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36832 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63252649 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 110299 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1080572 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27872767 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14726920 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18377517 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10342666 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4128139 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59880890 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6989 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 638699 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1446922 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 40104744 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72926681 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72541237 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 385444 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35232895 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4871841 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1468873 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 214348 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11259122 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9368607 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6150188 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1144221 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 763596 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53152910 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1825418 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51980474 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87912 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5962808 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3052808 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1237037 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76528583 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.679230 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328773 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 75653727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.108933 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.559051 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26076145 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36746783 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10850479 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 927296 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1053023 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507905 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35356 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62314637 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105308 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1053023 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27090322 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15013520 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18214120 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10165522 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4117218 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58954969 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7221 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 636497 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1465868 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39489312 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71817747 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71438623 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 379124 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34689683 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4799621 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1442009 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 210125 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11209509 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9215492 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6028586 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1140138 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 729797 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52283270 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1794569 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51124724 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87475 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5854476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3047065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1215266 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 75653727 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.675773 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.327184 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53422858 69.81% 69.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10519380 13.75% 83.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4737419 6.19% 89.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3110993 4.07% 93.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2482363 3.24% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1230781 1.61% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 656198 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 315996 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52595 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52928215 69.96% 69.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10364815 13.70% 83.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4648030 6.14% 89.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3048990 4.03% 93.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2439160 3.22% 97.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1210231 1.60% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 645067 0.85% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 315070 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54149 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76528583 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 75653727 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 81649 11.89% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 319979 46.59% 58.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285231 41.53% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82277 12.13% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 315255 46.46% 58.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 280962 41.41% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3782 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35814992 68.90% 68.91% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57898 0.11% 69.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.02% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15714 0.03% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9315059 17.92% 86.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5946213 11.44% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 824933 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35245093 68.94% 68.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56186 0.11% 69.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15594 0.03% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9165347 17.93% 87.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5826893 11.40% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 809947 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51980474 # Type of FU issued -system.cpu0.iq.rate 0.501010 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 686859 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013214 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 180712322 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60686814 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50945996 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 551979 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267326 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260492 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52374713 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288838 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 545458 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51124724 # Type of FU issued +system.cpu0.iq.rate 0.450136 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 678494 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 178124739 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59681238 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50082929 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 544404 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 263662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 256861 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51514533 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 284900 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 542155 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1121947 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2762 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13266 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 454260 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1111126 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3856 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12844 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 447697 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18544 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 124618 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 153340 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1080572 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10513662 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 794213 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58228726 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 618999 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9368607 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6150188 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1608738 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 580049 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5099 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13266 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 168319 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356582 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 524901 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51585627 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9008604 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 394846 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1053023 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10729289 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 792549 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57283617 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 622169 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9215492 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6028586 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1581349 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 577410 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6280 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12844 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 162347 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 348099 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 510446 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50735914 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8864635 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 388809 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3250398 # number of nop insts executed -system.cpu0.iew.exec_refs 14908735 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8218209 # Number of branches executed -system.cpu0.iew.exec_stores 5900131 # Number of stores executed -system.cpu0.iew.exec_rate 0.497205 # Inst execution rate -system.cpu0.iew.wb_sent 51301062 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51206488 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25493361 # num instructions producing a value -system.cpu0.iew.wb_consumers 34352042 # num instructions consuming a value +system.cpu0.iew.exec_nop 3205778 # number of nop insts executed +system.cpu0.iew.exec_refs 14644864 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8078425 # Number of branches executed +system.cpu0.iew.exec_stores 5780229 # Number of stores executed +system.cpu0.iew.exec_rate 0.446713 # Inst execution rate +system.cpu0.iew.wb_sent 50428595 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50339790 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25084021 # num instructions producing a value +system.cpu0.iew.wb_consumers 33790368 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.493550 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742121 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443225 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742342 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6443785 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 588381 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 491234 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75448011 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685042 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.601476 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6311482 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 579303 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 475138 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 74600704 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681919 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.596319 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56013876 74.24% 74.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8117892 10.76% 85.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4422865 5.86% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2392310 3.17% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1343441 1.78% 95.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 564278 0.75% 96.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 477580 0.63% 97.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 442296 0.59% 97.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1673473 2.22% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55419889 74.29% 74.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8033545 10.77% 85.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4371447 5.86% 90.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2356278 3.16% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1324268 1.78% 95.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 555518 0.74% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 469565 0.63% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 427219 0.57% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1642975 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75448011 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51685042 # Number of instructions committed -system.cpu0.commit.committedOps 51685042 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 74600704 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50871658 # Number of instructions committed +system.cpu0.commit.committedOps 50871658 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13942588 # Number of memory references committed -system.cpu0.commit.loads 8246660 # Number of loads committed -system.cpu0.commit.membars 199926 # Number of memory barriers committed -system.cpu0.commit.branches 7810095 # Number of branches committed -system.cpu0.commit.fp_insts 258326 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47876421 # Number of committed integer instructions. -system.cpu0.commit.function_calls 664533 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1673473 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13685255 # Number of memory references committed +system.cpu0.commit.loads 8104366 # Number of loads committed +system.cpu0.commit.membars 196950 # Number of memory barriers committed +system.cpu0.commit.branches 7686240 # Number of branches committed +system.cpu0.commit.fp_insts 254806 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47114322 # Number of committed integer instructions. +system.cpu0.commit.function_calls 650737 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1642975 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 131700376 # The number of ROB reads -system.cpu0.rob.rob_writes 117338865 # The number of ROB writes -system.cpu0.timesIdled 1069961 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27222708 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3689125904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48725185 # Number of Instructions Simulated -system.cpu0.committedOps 48725185 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 48725185 # Number of Instructions Simulated -system.cpu0.cpi 2.129315 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.129315 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.469634 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.469634 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67898060 # number of integer regfile reads -system.cpu0.int_regfile_writes 37063784 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127956 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129360 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1719000 # number of misc regfile reads -system.cpu0.misc_regfile_writes 824833 # number of misc regfile writes +system.cpu0.rob.rob_reads 129943858 # The number of ROB reads +system.cpu0.rob.rob_writes 115419344 # The number of ROB writes +system.cpu0.timesIdled 1091777 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 37922373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693821721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47948786 # Number of Instructions Simulated +system.cpu0.committedOps 47948786 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47948786 # Number of Instructions Simulated +system.cpu0.cpi 2.368696 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.368696 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.422173 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.422173 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66777793 # number of integer regfile reads +system.cpu0.int_regfile_writes 36448823 # number of integer regfile writes +system.cpu0.fp_regfile_reads 126128 # number of floating regfile reads +system.cpu0.fp_regfile_writes 127569 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1693303 # number of misc regfile reads +system.cpu0.misc_regfile_writes 810480 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,245 +1103,375 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 889638 # number of replacements -system.cpu0.icache.tagsinuse 510.303457 # Cycle average of tags in use -system.cpu0.icache.total_refs 6872883 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 890147 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.721065 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20517812000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.303457 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996686 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996686 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6872883 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6872883 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6872883 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6872883 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6872883 # number of overall hits -system.cpu0.icache.overall_hits::total 6872883 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 935512 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 935512 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 935512 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 935512 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 935512 # number of overall misses -system.cpu0.icache.overall_misses::total 935512 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13284271991 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13284271991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13284271991 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13284271991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13284271991 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13284271991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808395 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7808395 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7808395 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7808395 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7808395 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7808395 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119808 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119808 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119808 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119808 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119808 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119808 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14200.001701 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14200.001701 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14200.001701 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14200.001701 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5547 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 2537 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.240741 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 845.666667 # average number of cycles each access was blocked +system.toL2Bus.throughput 111431458 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2199741 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2199647 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13135 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13135 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 819443 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10566 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6236 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16802 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343057 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301508 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1737096 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3343563 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 452207 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 314296 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5847162 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 55584064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 129094452 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 14469760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 11514982 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 210663258 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210652954 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1479360 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4959879460 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3910967404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5778463419 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1017961113 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 540290711 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 1437243 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 54687 # Transaction distribution +system.iobus.trans_dist::WriteResp 54687 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 124112 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 74458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2736082 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2736082 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11417000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 378279654 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 27523000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.replacements 867916 # number of replacements +system.cpu0.icache.tagsinuse 509.785268 # Cycle average of tags in use +system.cpu0.icache.total_refs 6758563 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 868427 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.782534 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25769681000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.785268 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995674 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995674 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6758564 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6758564 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6758564 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6758564 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6758564 # number of overall hits +system.cpu0.icache.overall_hits::total 6758564 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 912847 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 912847 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 912847 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 912847 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 912847 # number of overall misses +system.cpu0.icache.overall_misses::total 912847 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13149310993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13149310993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13149310993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13149310993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13149310993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13149310993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7671411 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7671411 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7671411 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7671411 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7671411 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7671411 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118993 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118993 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118993 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118993 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118993 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118993 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14404.726086 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14404.726086 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14404.726086 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14404.726086 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3418 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 152 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.486842 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45203 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45203 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45203 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45203 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45203 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45203 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 890309 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 890309 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 890309 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 890309 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 890309 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 890309 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10926647992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10926647992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10926647992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10926647992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10926647992 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10926647992 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114019 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.114019 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.114019 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12272.871545 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44252 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44252 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 44252 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44252 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 44252 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44252 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868595 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 868595 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 868595 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 868595 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 868595 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 868595 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814937089 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814937089 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814937089 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10814937089 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814937089 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10814937089 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113225 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113225 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12451.069934 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1284134 # number of replacements -system.cpu0.dcache.tagsinuse 505.722211 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10611019 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1284646 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.259878 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.722211 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987739 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987739 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6528989 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6528989 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3717707 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3717707 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164546 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164546 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188999 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 188999 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10246696 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10246696 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10246696 # number of overall hits -system.cpu0.dcache.overall_hits::total 10246696 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1596925 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1596925 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1771522 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1771522 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2763 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2763 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3368447 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3368447 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3368447 # number of overall misses -system.cpu0.dcache.overall_misses::total 3368447 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34533208000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34533208000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68837486976 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 68837486976 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 293802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20678500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20678500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 103370694976 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 103370694976 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 103370694976 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 103370694976 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8125914 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8125914 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5489229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5489229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 184964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 184964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13615143 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13615143 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13615143 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13615143 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196523 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.196523 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322727 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322727 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110389 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110389 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014408 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014408 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247404 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247404 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247404 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247404 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21624.815192 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21624.815192 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38857.822243 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38857.822243 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14389.362327 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14389.362327 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7484.075280 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7484.075280 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30687.938678 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30687.938678 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2260715 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 49054 # number of cycles access was blocked +system.cpu0.dcache.replacements 1271376 # number of replacements +system.cpu0.dcache.tagsinuse 505.686526 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10390956 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1271888 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.169710 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 25830000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.686526 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987669 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987669 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6393137 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6393137 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3639350 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3639350 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 161427 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 161427 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185616 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 185616 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10032487 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10032487 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10032487 # number of overall hits +system.cpu0.dcache.overall_hits::total 10032487 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1573505 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1573505 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1738147 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1738147 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20045 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20045 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3020 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3020 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3311652 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3311652 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3311652 # number of overall misses +system.cpu0.dcache.overall_misses::total 3311652 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39654304500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39654304500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77521243901 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77521243901 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 292960500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 292960500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 22204000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 22204000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117175548401 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117175548401 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117175548401 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117175548401 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7966642 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7966642 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5377497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5377497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181472 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 181472 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 188636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13344139 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13344139 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13344139 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13344139 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197512 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323226 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323226 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110458 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110458 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248173 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248173 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248173 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248173 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25201.257384 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25201.257384 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44599.935392 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44599.935392 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14615.140933 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14615.140933 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7352.317881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7352.317881 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35382.808460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35382.808460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35382.808460 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2842539 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 840 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 51698 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 46.086252 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 54.983539 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 120 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 757117 # number of writebacks -system.cpu0.dcache.writebacks::total 757117 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 591865 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 591865 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494302 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1494302 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4660 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4660 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2086167 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2086167 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2086167 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2086167 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1005060 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1005060 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 277220 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 277220 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15758 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15758 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2763 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2763 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1282280 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1282280 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1282280 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1282280 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21590310000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21590310000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10033221203 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10033221203 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 180646500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 180646500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15152500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15152500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31623531203 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31623531203 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31623531203 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31623531203 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465155500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465155500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167706499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167706499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3632861999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3632861999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123686 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123686 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085195 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085195 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014408 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014408 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094180 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094180 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21481.613038 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21481.613038 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36192.270410 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36192.270410 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11463.796167 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11463.796167 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5484.075280 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5484.075280 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 746874 # number of writebacks +system.cpu0.dcache.writebacks::total 746874 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 575080 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 575080 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465992 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1465992 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2041072 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2041072 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2041072 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2041072 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 998425 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 998425 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272155 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272155 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3020 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3020 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1270580 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1270580 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1270580 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1270580 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26454916051 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26454916051 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11388682739 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11388682739 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172348003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172348003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 16164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 16164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 37843598790 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 37843598790 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 37843598790 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 37843598790 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459347502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459347502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2156087498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2156087498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3615435000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3615435000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085876 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085876 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095216 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095216 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26496.648272 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26496.648272 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41846.310885 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41846.310885 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11059.291774 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11059.291774 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5352.317881 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5352.317881 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1178,35 +1479,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2374472 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1973565 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 63683 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1357670 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 789569 # Number of BTB hits +system.cpu1.branchPred.lookups 2604526 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2153409 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 75247 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1513707 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 876072 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 58.156179 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 159848 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6979 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.875930 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 179167 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7740 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1755569 # DTB read hits -system.cpu1.dtb.read_misses 9259 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 277737 # DTB read accesses -system.cpu1.dtb.write_hits 1124169 # DTB write hits -system.cpu1.dtb.write_misses 1775 # DTB write misses -system.cpu1.dtb.write_acv 38 # DTB write access violations -system.cpu1.dtb.write_accesses 104346 # DTB write accesses -system.cpu1.dtb.data_hits 2879738 # DTB hits -system.cpu1.dtb.data_misses 11034 # DTB misses -system.cpu1.dtb.data_acv 44 # DTB access violations -system.cpu1.dtb.data_accesses 382083 # DTB accesses -system.cpu1.itb.fetch_hits 378886 # ITB hits -system.cpu1.itb.fetch_misses 5643 # ITB misses -system.cpu1.itb.fetch_acv 144 # ITB acv -system.cpu1.itb.fetch_accesses 384529 # ITB accesses +system.cpu1.dtb.read_hits 1932131 # DTB read hits +system.cpu1.dtb.read_misses 10237 # DTB read misses +system.cpu1.dtb.read_acv 25 # DTB read access violations +system.cpu1.dtb.read_accesses 320506 # DTB read accesses +system.cpu1.dtb.write_hits 1251341 # DTB write hits +system.cpu1.dtb.write_misses 1962 # DTB write misses +system.cpu1.dtb.write_acv 65 # DTB write access violations +system.cpu1.dtb.write_accesses 130037 # DTB write accesses +system.cpu1.dtb.data_hits 3183472 # DTB hits +system.cpu1.dtb.data_misses 12199 # DTB misses +system.cpu1.dtb.data_acv 90 # DTB access violations +system.cpu1.dtb.data_accesses 450543 # DTB accesses +system.cpu1.itb.fetch_hits 430844 # ITB hits +system.cpu1.itb.fetch_misses 6753 # ITB misses +system.cpu1.itb.fetch_acv 212 # ITB acv +system.cpu1.itb.fetch_accesses 437597 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1219,512 +1520,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14403389 # number of cpu cycles simulated +system.cpu1.numCycles 15794943 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5507969 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11118541 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2374472 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 949417 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1985955 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 349018 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 5777579 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25749 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 54503 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 55745 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1323443 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 42238 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 13629786 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.815753 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.191288 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6044274 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12313553 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2604526 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1055239 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2204838 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 395965 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6209579 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26246 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 62195 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 53260 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1481011 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50405 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14852690 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.829045 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.204427 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11643831 85.43% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 125140 0.92% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 217081 1.59% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 155934 1.14% 89.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 266080 1.95% 91.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 106134 0.78% 91.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 117650 0.86% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 192941 1.42% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 804995 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12647852 85.16% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 141564 0.95% 86.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 235652 1.59% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 175889 1.18% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 303768 2.05% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 119285 0.80% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 129403 0.87% 92.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 209113 1.41% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 890164 5.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13629786 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164855 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.771939 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5440584 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6013692 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1859543 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 99467 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 216499 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 99353 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5852 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10916304 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 17556 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 216499 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5632614 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 346968 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5076489 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1765081 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 592133 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10097386 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55596 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 134498 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 6632848 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12019300 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 11877082 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 142218 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5717715 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 915133 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 422143 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 38586 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1845577 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1850340 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1191384 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 164933 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 85198 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8855097 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 461396 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8635428 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27588 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1251794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 621930 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 331901 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13629786 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.633570 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.306468 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14852690 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164896 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.779588 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5971093 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6462269 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2062064 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 112088 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 245175 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 113398 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7205 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12081319 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21458 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 245175 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6179272 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 425366 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5395094 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1962879 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 644902 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11197795 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 57093 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 157527 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7361429 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13363056 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13213666 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 149390 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6300177 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1061252 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 451071 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 42573 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1993362 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2041709 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1326014 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 180090 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 100258 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9822573 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 491625 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9565946 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 29815 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1410113 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 705464 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 352077 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14852690 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644055 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.318534 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9807862 71.96% 71.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1774840 13.02% 84.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 743934 5.46% 90.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 492954 3.62% 94.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 425816 3.12% 97.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 193635 1.42% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 119802 0.88% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 63937 0.47% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 7006 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10648951 71.70% 71.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1930050 12.99% 84.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 818337 5.51% 90.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 551122 3.71% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 476075 3.21% 97.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 213789 1.44% 98.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 136394 0.92% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 69529 0.47% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8443 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13629786 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14852690 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2819 1.60% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 95112 53.88% 55.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 78586 44.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3207 1.63% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 106178 53.97% 55.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 87357 44.40% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5368636 62.17% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14579 0.17% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10813 0.13% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1836056 21.26% 83.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1146030 13.27% 97.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 254037 2.94% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5966011 62.37% 62.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16243 0.17% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10971 0.11% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2021702 21.13% 83.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1274955 13.33% 97.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 270775 2.83% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8635428 # Type of FU issued -system.cpu1.iq.rate 0.599541 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 176517 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020441 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 30899211 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10469267 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8392820 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 205536 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 100351 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 97198 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8701253 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 107174 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 85247 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9565946 # Type of FU issued +system.cpu1.iq.rate 0.605633 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 196742 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020567 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 33995446 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11620704 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9288457 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 215693 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 105258 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 101999 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9646700 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 112462 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 92569 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 244767 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 715 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1400 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 111607 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 282729 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1535 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1711 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 123624 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 264 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 323 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 14236 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 216499 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 208020 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 39541 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9780313 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 131211 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1850340 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1191384 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 418145 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33976 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1692 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1400 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28557 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 89287 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117844 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8559872 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1771461 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 75556 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 245175 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 256542 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 43339 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10829040 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 147658 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2041709 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1326014 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 444647 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 36382 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1620 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1711 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 33953 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 99696 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 133649 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9473535 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1949759 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 92411 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 463820 # number of nop insts executed -system.cpu1.iew.exec_refs 2903123 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1270722 # Number of branches executed -system.cpu1.iew.exec_stores 1131662 # Number of stores executed -system.cpu1.iew.exec_rate 0.594296 # Inst execution rate -system.cpu1.iew.wb_sent 8515413 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8490018 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3998147 # num instructions producing a value -system.cpu1.iew.wb_consumers 5641896 # num instructions consuming a value +system.cpu1.iew.exec_nop 514842 # number of nop insts executed +system.cpu1.iew.exec_refs 3209162 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1413585 # Number of branches executed +system.cpu1.iew.exec_stores 1259403 # Number of stores executed +system.cpu1.iew.exec_rate 0.599783 # Inst execution rate +system.cpu1.iew.wb_sent 9417236 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9390456 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4401006 # num instructions producing a value +system.cpu1.iew.wb_consumers 6190652 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.589446 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708653 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.594523 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710912 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1285480 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 129495 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 111745 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13413287 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.628190 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.573982 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1449457 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 139548 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 125475 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14607515 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.636458 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.578813 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10261662 76.50% 76.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1478959 11.03% 87.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 542849 4.05% 91.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 333012 2.48% 94.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 234215 1.75% 95.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 91771 0.68% 96.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 99946 0.75% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 99972 0.75% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 270901 2.02% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11126487 76.17% 76.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1625013 11.12% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 604004 4.13% 91.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 371910 2.55% 93.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 263907 1.81% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 102565 0.70% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 109537 0.75% 97.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 110097 0.75% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 293995 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13413287 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8426096 # Number of instructions committed -system.cpu1.commit.committedOps 8426096 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14607515 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9297065 # Number of instructions committed +system.cpu1.commit.committedOps 9297065 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2685350 # Number of memory references committed -system.cpu1.commit.loads 1605573 # Number of loads committed -system.cpu1.commit.membars 41432 # Number of memory barriers committed -system.cpu1.commit.branches 1197085 # Number of branches committed -system.cpu1.commit.fp_insts 95994 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7795496 # Number of committed integer instructions. -system.cpu1.commit.function_calls 132738 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 270901 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2961370 # Number of memory references committed +system.cpu1.commit.loads 1758980 # Number of loads committed +system.cpu1.commit.membars 44792 # Number of memory barriers committed +system.cpu1.commit.branches 1328076 # Number of branches committed +system.cpu1.commit.fp_insts 100787 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8610735 # Number of committed integer instructions. +system.cpu1.commit.function_calls 147103 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 293995 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 22771832 # The number of ROB reads -system.cpu1.rob.rob_writes 19637981 # The number of ROB writes -system.cpu1.timesIdled 118769 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 773603 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3777797828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8011939 # Number of Instructions Simulated -system.cpu1.committedOps 8011939 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8011939 # Number of Instructions Simulated -system.cpu1.cpi 1.797741 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.797741 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556254 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556254 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11010177 # number of integer regfile reads -system.cpu1.int_regfile_writes 6039470 # number of integer regfile writes -system.cpu1.fp_regfile_reads 53089 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52904 # number of floating regfile writes -system.cpu1.misc_regfile_reads 494875 # number of misc regfile reads -system.cpu1.misc_regfile_writes 202385 # number of misc regfile writes -system.cpu1.icache.replacements 202443 # number of replacements -system.cpu1.icache.tagsinuse 470.727745 # Cycle average of tags in use -system.cpu1.icache.total_refs 1113774 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 202955 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.487788 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1886714019000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.727745 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919390 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919390 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1113774 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1113774 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1113774 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1113774 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1113774 # number of overall hits -system.cpu1.icache.overall_hits::total 1113774 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 209669 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 209669 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 209669 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 209669 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 209669 # number of overall misses -system.cpu1.icache.overall_misses::total 209669 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2812457500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2812457500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2812457500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2812457500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2812457500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2812457500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1323443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1323443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1323443 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1323443 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1323443 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1323443 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158427 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.158427 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158427 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.158427 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158427 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.158427 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13413.797462 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13413.797462 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13413.797462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13413.797462 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 72 # number of cycles access was blocked +system.cpu1.rob.rob_reads 24970897 # The number of ROB reads +system.cpu1.rob.rob_writes 21736671 # The number of ROB writes +system.cpu1.timesIdled 134601 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 942253 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3790981004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8842996 # Number of Instructions Simulated +system.cpu1.committedOps 8842996 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8842996 # Number of Instructions Simulated +system.cpu1.cpi 1.786153 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.786153 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.559862 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.559862 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12205153 # number of integer regfile reads +system.cpu1.int_regfile_writes 6674473 # number of integer regfile writes +system.cpu1.fp_regfile_reads 55471 # number of floating regfile reads +system.cpu1.fp_regfile_writes 55305 # number of floating regfile writes +system.cpu1.misc_regfile_reads 527113 # number of misc regfile reads +system.cpu1.misc_regfile_writes 218222 # number of misc regfile writes +system.cpu1.icache.replacements 225540 # number of replacements +system.cpu1.icache.tagsinuse 470.721925 # Cycle average of tags in use +system.cpu1.icache.total_refs 1246547 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 226052 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.514426 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1877726350000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.721925 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919379 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919379 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1246547 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1246547 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1246547 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1246547 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1246547 # number of overall hits +system.cpu1.icache.overall_hits::total 1246547 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 234464 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 234464 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 234464 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 234464 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 234464 # number of overall misses +system.cpu1.icache.overall_misses::total 234464 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3166624000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3166624000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3166624000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3166624000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3166624000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3166624000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1481011 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1481011 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1481011 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1481011 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1481011 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1481011 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158313 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.158313 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158313 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.158313 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158313 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.158313 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.800464 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.800464 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13505.800464 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13505.800464 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.777778 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6654 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6654 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6654 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6654 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6654 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6654 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 203015 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 203015 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 203015 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 203015 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 203015 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 203015 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2347033500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2347033500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2347033500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2347033500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2347033500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2347033500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.153399 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.153399 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.153399 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11560.887127 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8347 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8347 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8347 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8347 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8347 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8347 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 226117 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 226117 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 226117 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 226117 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 226117 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 226117 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2628094387 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2628094387 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2628094387 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2628094387 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2628094387 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2628094387 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152677 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.152677 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.152677 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11622.719154 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 95898 # number of replacements -system.cpu1.dcache.tagsinuse 491.044785 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2359205 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 96213 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.520647 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39003208000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.044785 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.959072 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.959072 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1444297 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1444297 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 860369 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 860369 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29709 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29709 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28445 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 28445 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2304666 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2304666 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2304666 # number of overall hits -system.cpu1.dcache.overall_hits::total 2304666 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 191100 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 191100 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 182257 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 182257 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4958 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4958 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3002 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3002 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 373357 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 373357 # 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Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 43858959000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 491.736427 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.960423 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.960423 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1587502 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1587502 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 943251 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 943251 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32579 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 32579 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 31559 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 31559 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2530753 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2530753 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2530753 # number of overall hits +system.cpu1.dcache.overall_hits::total 2530753 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 209244 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 209244 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 218379 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 218379 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5510 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5510 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3216 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3216 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 427623 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 427623 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 427623 # number of overall misses +system.cpu1.dcache.overall_misses::total 427623 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2938034500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2938034500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7305073698 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7305073698 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 55149000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 55149000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 23385500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 23385500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10243108198 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10243108198 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10243108198 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10243108198 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1796746 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1796746 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1161630 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1161630 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38089 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 38089 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 34775 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 34775 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2958376 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2958376 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2958376 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2958376 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.116457 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.116457 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187994 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.187994 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.144661 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.144661 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092480 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092480 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.144547 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.144547 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.144547 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.144547 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14041.188756 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14041.188756 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33451.356119 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33451.356119 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10008.892922 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10008.892922 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7271.610697 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7271.610697 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23953.595101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23953.595101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23953.595101 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 227083 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3033 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4054 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 58.786020 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.014554 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 62482 # number of writebacks -system.cpu1.dcache.writebacks::total 62482 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 119560 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 119560 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148811 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 148811 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 417 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 417 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 268371 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 268371 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 268371 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 268371 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 71540 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 71540 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 33446 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 33446 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4541 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4541 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3000 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3000 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 104986 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 104986 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 104986 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 104986 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 843257000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 843257000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 841845993 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 841845993 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 36401500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 36401500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16047000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16047000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1685102993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1685102993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1685102993 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1685102993 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 603885500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 603885500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 621984000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 621984000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032079 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032079 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130989 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130989 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095399 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095399 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039203 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039203 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11787.209952 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11787.209952 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25170.304162 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25170.304162 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8016.185862 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8016.185862 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5349 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5349 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 72569 # number of writebacks +system.cpu1.dcache.writebacks::total 72569 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129770 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 129770 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 179212 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 179212 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 594 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 594 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 308982 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 308982 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 308982 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 308982 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79474 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 79474 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39167 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 39167 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4916 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4916 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3216 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3216 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 118641 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 118641 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 118641 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 118641 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 893939249 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 893939249 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081571527 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081571527 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37210004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37210004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16953500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16953500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1975510776 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1975510776 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1975510776 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1975510776 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23615501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23615501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 628297501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 628297501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 651913002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 651913002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044232 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044232 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.129066 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.129066 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092480 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092480 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040103 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040103 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11248.197511 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11248.197511 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27614.357163 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27614.357163 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7569.162734 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7569.162734 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5271.610697 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5271.610697 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1733,161 +2030,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6633 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 185817 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65566 40.59% 40.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.19% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 201 0.12% 41.99% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93709 58.01% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 161530 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64589 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 1.47% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 201 0.15% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64388 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131232 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1860847795500 98.12% 98.12% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64543000 0.00% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567978500 0.03% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 98193500 0.01% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34862560000 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896441070500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.985099 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6605 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 182638 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64421 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.21% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 210 0.13% 41.93% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92368 58.07% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 159055 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63463 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.49% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 210 0.16% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63253 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128982 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863089530500 97.87% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64074500 0.00% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567937500 0.03% 97.90% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 100797000 0.01% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39879064000 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903701403500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.985129 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.687106 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812431 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684793 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810927 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 211 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3552 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wripir 302 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3478 2.07% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 154681 90.79% 93.08% # number of callpals executed -system.cpu0.kern.callpal::rdps 6653 3.90% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.99% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rti 4593 2.70% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170374 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7193 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::swpipl 152288 90.83% 93.12% # number of callpals executed +system.cpu0.kern.callpal::rdps 6536 3.90% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::rti 4500 2.68% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 345 0.21% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 167660 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7044 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1285 +system.cpu0.kern.mode_good::user 1286 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.190324 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.182425 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.319865 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894375479500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2065583000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.308643 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901692288000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2009107500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3553 # number of times the context was actually changed +system.cpu0.kern.swap_context 3479 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2383 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 53842 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16791 36.23% 36.23% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 4.14% 40.37% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 284 0.61% 40.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27352 59.01% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 46348 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16391 47.23% 47.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 5.54% 52.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.82% 53.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16107 46.41% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34703 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871184919000 98.69% 98.69% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531151500 0.03% 98.71% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 127549500 0.01% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24258165000 1.28% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896101785000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976178 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 57331 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18009 36.73% 36.73% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.92% 40.65% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 302 0.62% 41.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28797 58.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49032 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17590 47.41% 47.41% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 5.19% 52.59% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 302 0.81% 53.41% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17288 46.59% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37104 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1873168497000 98.41% 98.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531845000 0.03% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 136792000 0.01% 98.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29552054000 1.55% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903389188000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976734 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.588878 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.748749 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.600340 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.756730 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 115 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 201 0.42% 0.42% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.43% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.43% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1067 2.24% 2.67% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.67% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.69% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41171 86.33% 89.01% # number of callpals executed -system.cpu1.kern.callpal::rdps 2098 4.40% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2971 6.23% 99.66% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.25% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 210 0.41% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1165 2.30% 2.72% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.73% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.75% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43701 86.29% 89.04% # number of callpals executed +system.cpu1.kern.callpal::rdps 2223 4.39% 93.43% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.43% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.44% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.44% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.44% # number of callpals executed +system.cpu1.kern.callpal::rti 3104 6.13% 99.57% # number of callpals executed +system.cpu1.kern.callpal::callsys 172 0.34% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 47692 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1242 # number of protection mode switches -system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2406 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 576 -system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 208 -system.cpu1.kern.mode_switch_good::kernel 0.463768 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 50643 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1414 # number of protection mode switches +system.cpu1.kern.mode_switch::user 459 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2447 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 685 +system.cpu1.kern.mode_good::user 459 +system.cpu1.kern.mode_good::idle 226 +system.cpu1.kern.mode_switch_good::kernel 0.484441 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086451 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286853 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4070064000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 689483000 0.04% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1891020032000 99.75% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1068 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.092358 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.317130 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4654463000 0.24% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 807268500 0.04% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1897916233000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1166 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 1410f747e..6711c23df 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,124 +1,124 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854316 # Number of seconds simulated -sim_ticks 1854315535000 # Number of ticks simulated -final_tick 1854315535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859220 # Number of seconds simulated +sim_ticks 1859219766000 # Number of ticks simulated +final_tick 1859219766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136218 # Simulator instruction rate (inst/s) -host_op_rate 136218 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4770234092 # Simulator tick rate (ticks/s) -host_mem_usage 308432 # Number of bytes of host memory used -host_seconds 388.73 # Real time elapsed on the host -sim_insts 52951550 # Number of instructions simulated -sim_ops 52951550 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 963520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28493120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7502080 # Number of bytes written to this memory -system.physmem.bytes_written::total 7502080 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15055 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445205 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117220 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117220 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13415866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15365842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045741 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045741 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13415866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19411583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445205 # Total number of read requests seen -system.physmem.writeReqs 117220 # Total number of write requests seen -system.physmem.cpureqs 562608 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28493120 # Total number of bytes read from memory -system.physmem.bytesWritten 7502080 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28493120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7502080 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27978 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28085 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27720 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7553 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7293 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7144 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6986 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7373 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7381 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7497 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7211 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7256 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7369 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7178 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7195 # Track writes on a per bank basis +host_inst_rate 91264 # Simulator instruction rate (inst/s) +host_op_rate 91264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3202546943 # Simulator tick rate (ticks/s) +host_mem_usage 310256 # Number of bytes of host memory used +host_seconds 580.54 # Real time elapsed on the host +sim_insts 52982774 # Number of instructions simulated +sim_ops 52982774 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879168 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28495424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388737 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445241 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13381510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1426560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15326550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4042229 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4042229 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4042229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13381510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1426560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19368779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445241 # Total number of read requests seen +system.physmem.writeReqs 117428 # Total number of write requests seen +system.physmem.cpureqs 562841 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28495424 # Total number of bytes read from memory +system.physmem.bytesWritten 7515392 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28495424 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7515392 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27975 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27225 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28226 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28320 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7499 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7517 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6762 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7320 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6981 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8048 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7826 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854310136000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry +system.physmem.totGap 1859214351000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445205 # Categorize read packet sizes +system.physmem.readPktSize::6 445241 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117220 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117428 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 330939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -128,68 +128,248 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.totQLat 7478299000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15194295250 # Sum of mem lat for all requests -system.physmem.totBusLat 2225745000 # Total cycles spent in databus access -system.physmem.totBankLat 5490251250 # Total cycles spent in bank access -system.physmem.avgQLat 16799.54 # Average queueing delay per request -system.physmem.avgBankLat 12333.51 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 37468 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 960.941176 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 233.799958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2437.428145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 12972 34.62% 34.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5555 14.83% 49.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3417 9.12% 58.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2277 6.08% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1679 4.48% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1428 3.81% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 991 2.64% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 802 2.14% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 632 1.69% 79.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 550 1.47% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 599 1.60% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 534 1.43% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 276 0.74% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 243 0.65% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 192 0.51% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 257 0.69% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 103 0.27% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 109 0.29% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 145 0.39% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 226 0.60% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 117 0.31% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 450 1.20% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 603 1.61% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 73 0.19% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 37 0.10% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 34 0.09% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 78 0.21% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 30 0.08% 92.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 11 0.03% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 8 0.02% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 42 0.11% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 24 0.06% 92.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 2 0.01% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 6 0.02% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 2 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 2 0.01% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 2 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 2 0.01% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 2 0.01% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2434 6.50% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 3 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 7 0.02% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 2 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17283 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37468 # Bytes accessed per row activation +system.physmem.totQLat 6065400750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13430024500 # Sum of mem lat for all requests +system.physmem.totBusLat 2225905000 # Total cycles spent in databus access +system.physmem.totBankLat 5138718750 # Total cycles spent in bank access +system.physmem.avgQLat 13624.57 # Average queueing delay per request +system.physmem.avgBankLat 11542.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34133.05 # Average memory access latency -system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30167.56 # Average memory access latency +system.physmem.avgRdBW 15.33 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.33 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 7.57 # Average write queue length over time -system.physmem.readRowHits 417721 # Number of row buffer hits during reads -system.physmem.writeRowHits 91342 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.92 # Row buffer hit rate for writes -system.physmem.avgGap 3296990.95 # Average gap between requests +system.physmem.avgWrQLen 11.93 # Average write queue length over time +system.physmem.readRowHits 430163 # Number of row buffer hits during reads +system.physmem.writeRowHits 94965 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes +system.physmem.avgGap 3304277.21 # Average gap between requests +system.membus.throughput 19411663 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296022 # Transaction distribution +system.membus.trans_dist::ReadResp 295937 # Transaction distribution +system.membus.trans_dist::WriteReq 9598 # Transaction distribution +system.membus.trans_dist::WriteResp 9598 # Transaction distribution +system.membus.trans_dist::Writeback 117428 # Transaction distribution +system.membus.trans_dist::UpgradeReq 173 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 156790 # Transaction distribution +system.membus.trans_dist::ReadExResp 156790 # Transaction distribution +system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1008811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042037 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745908 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 36010816 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36054964 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36054964 # Total data (bytes) +system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 29876000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1541728249 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer2.occupancy 108500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3763624798 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 376221741 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265062 # Cycle average of tags in use +system.iocache.tagsinuse 1.261712 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704476481000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265062 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709369770000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.261712 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078857 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078857 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -198,14 +378,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10641558911 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10641558911 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10662486909 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10662486909 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10662486909 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10662486909 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10471007269 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10471007269 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10492350152 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10492350152 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10492350152 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10492350152 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -222,19 +402,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256102.207138 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256102.207138 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255541.927118 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255541.927118 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285704 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251997.672049 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251997.672049 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 251464.353553 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 251464.353553 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 273612 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27220 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27136 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.496106 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.082989 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -248,14 +428,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8479547437 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8479547437 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8491478686 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8491478686 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8491478686 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8491478686 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8309607278 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8309607278 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8321953411 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8321953411 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8321953411 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8321953411 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -264,14 +444,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204070.741168 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204070.741168 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199980.922170 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199980.922170 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -285,35 +465,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13835452 # Number of BP lookups -system.cpu.branchPred.condPredicted 11604498 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 397875 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9360236 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5805061 # Number of BTB hits +system.cpu.branchPred.lookups 13839600 # Number of BP lookups +system.cpu.branchPred.condPredicted 11609173 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399191 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9510547 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5805743 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.018319 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 907052 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38979 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.045311 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906368 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39168 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9913942 # DTB read hits -system.cpu.dtb.read_misses 41971 # DTB read misses -system.cpu.dtb.read_acv 559 # DTB read access violations -system.cpu.dtb.read_accesses 941163 # DTB read accesses -system.cpu.dtb.write_hits 6591840 # DTB write hits -system.cpu.dtb.write_misses 10659 # DTB write misses +system.cpu.dtb.read_hits 9923550 # DTB read hits +system.cpu.dtb.read_misses 41274 # DTB read misses +system.cpu.dtb.read_acv 543 # DTB read access violations +system.cpu.dtb.read_accesses 941562 # DTB read accesses +system.cpu.dtb.write_hits 6598688 # DTB write hits +system.cpu.dtb.write_misses 10641 # DTB write misses system.cpu.dtb.write_acv 411 # DTB write access violations -system.cpu.dtb.write_accesses 337869 # DTB write accesses -system.cpu.dtb.data_hits 16505782 # DTB hits -system.cpu.dtb.data_misses 52630 # DTB misses -system.cpu.dtb.data_acv 970 # DTB access violations -system.cpu.dtb.data_accesses 1279032 # DTB accesses -system.cpu.itb.fetch_hits 1304387 # ITB hits -system.cpu.itb.fetch_misses 38101 # ITB misses -system.cpu.itb.fetch_acv 1094 # ITB acv -system.cpu.itb.fetch_accesses 1342488 # ITB accesses +system.cpu.dtb.write_accesses 338433 # DTB write accesses +system.cpu.dtb.data_hits 16522238 # DTB hits +system.cpu.dtb.data_misses 51915 # DTB misses +system.cpu.dtb.data_acv 954 # DTB access violations +system.cpu.dtb.data_accesses 1279995 # DTB accesses +system.cpu.itb.fetch_hits 1308614 # ITB hits +system.cpu.itb.fetch_misses 36742 # ITB misses +system.cpu.itb.fetch_acv 1058 # ITB acv +system.cpu.itb.fetch_accesses 1345356 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,269 +506,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108709176 # number of cpu cycles simulated +system.cpu.numCycles 120145786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28075681 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70625770 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13835452 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6712113 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13231336 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1982002 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37359508 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254255 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 361301 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 440 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8540739 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263307 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80598838 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.876263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28059248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70722559 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13839600 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6712111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13258692 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1994060 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38168658 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32286 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254324 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 364483 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8570347 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266679 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81425482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.868556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211321 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67367502 83.58% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 852306 1.06% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1694888 2.10% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 821828 1.02% 87.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2746821 3.41% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 564765 0.70% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 643702 0.80% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011325 1.25% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4895701 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68166790 83.72% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 854823 1.05% 84.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1706158 2.10% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 819634 1.01% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2757548 3.39% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561946 0.69% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 649151 0.80% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1013766 1.25% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4895666 6.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80598838 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127270 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.649676 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29246161 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37051175 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12098296 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 961855 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1241350 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 583461 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42570 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69332672 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129212 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1241350 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30366961 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13601503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19800886 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11334089 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4254047 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65583694 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7011 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505967 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1480663 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43793573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79610392 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79131107 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479285 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38157493 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5636072 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682036 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239674 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12118674 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10434139 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6898397 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1310169 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 877649 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58153519 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2049469 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56771792 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 109314 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6892902 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3544978 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1388546 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80598838 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365163 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81425482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115190 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.588640 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29284437 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37811275 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12102091 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 982484 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1245194 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 583690 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42726 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69419384 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129751 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1245194 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30419678 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14066203 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19996824 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11337239 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4360342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65632842 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7067 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 503743 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1590486 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43821413 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79676034 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79196502 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479532 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38182467 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5638938 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682867 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239802 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12252220 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10440672 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6902467 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1316833 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 861587 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58171642 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2051698 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56802904 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 100593 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6885118 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3554028 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390714 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81425482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359574 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55952160 69.42% 69.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10819456 13.42% 82.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5161521 6.40% 89.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3379007 4.19% 93.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2642777 3.28% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1459621 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 760708 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 329892 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 93696 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56719527 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10865996 13.34% 83.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5212450 6.40% 89.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3349939 4.11% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2634366 3.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1460723 1.79% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 752656 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 333424 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96401 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80598838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81425482 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91294 11.60% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373063 47.40% 59.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322658 41.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 93250 11.76% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372953 47.03% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326761 41.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38708062 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10346391 18.22% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6670119 11.75% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949001 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38720727 68.17% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61725 0.11% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10357561 18.23% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6677285 11.76% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56771792 # Type of FU issued -system.cpu.iq.rate 0.522236 # Inst issue rate -system.cpu.iq.fu_busy_cnt 787015 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013863 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194345553 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66772978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55538078 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693197 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336730 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327888 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57189578 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361943 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56802904 # Type of FU issued +system.cpu.iq.rate 0.472783 # Inst issue rate +system.cpu.iq.fu_busy_cnt 792964 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013960 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195231977 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66785301 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55558093 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692869 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336906 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327947 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57227049 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361533 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 597916 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1346178 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3275 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14144 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 522891 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1347952 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3269 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 524235 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17954 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 174426 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17914 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 199705 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1241350 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9930800 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684897 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63726259 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 676325 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10434139 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6898397 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805166 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512910 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18627 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14144 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 201347 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411340 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612687 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56305820 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9984116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 465971 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1245194 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10207267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 699182 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63757422 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 685568 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10440672 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6902467 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1806514 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512114 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18348 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 200766 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410779 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 611545 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56334870 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9992999 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 468033 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3523271 # number of nop insts executed -system.cpu.iew.exec_refs 16601850 # number of memory reference insts executed -system.cpu.iew.exec_branches 8919814 # Number of branches executed -system.cpu.iew.exec_stores 6617734 # Number of stores executed -system.cpu.iew.exec_rate 0.517949 # Inst execution rate -system.cpu.iew.wb_sent 55981553 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55865966 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27748179 # num instructions producing a value -system.cpu.iew.wb_consumers 37603022 # num instructions consuming a value +system.cpu.iew.exec_nop 3534082 # number of nop insts executed +system.cpu.iew.exec_refs 16617553 # number of memory reference insts executed +system.cpu.iew.exec_branches 8923539 # Number of branches executed +system.cpu.iew.exec_stores 6624554 # Number of stores executed +system.cpu.iew.exec_rate 0.468888 # Inst execution rate +system.cpu.iew.wb_sent 55999832 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55886040 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27701007 # num instructions producing a value +system.cpu.iew.wb_consumers 37529982 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.513903 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737924 # average fanout of values written-back +system.cpu.iew.wb_rate 0.465152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7467988 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660923 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566730 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79357488 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.707446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.635929 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7465540 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660984 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 567902 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80180288 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629829 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58581738 73.82% 73.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8607533 10.85% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4610804 5.81% 90.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2534837 3.19% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1515398 1.91% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 609514 0.77% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522093 0.66% 97.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 538800 0.68% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1836771 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59372363 74.05% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8630775 10.76% 84.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4656269 5.81% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2498281 3.12% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1510890 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 609736 0.76% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 522635 0.65% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 527296 0.66% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1852043 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79357488 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56141140 # Number of instructions committed -system.cpu.commit.committedOps 56141140 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80180288 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56173622 # Number of instructions committed +system.cpu.commit.committedOps 56173622 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15463467 # Number of memory references committed -system.cpu.commit.loads 9087961 # Number of loads committed -system.cpu.commit.membars 226334 # Number of memory barriers committed -system.cpu.commit.branches 8436593 # Number of branches committed +system.cpu.commit.refs 15470952 # Number of memory references committed +system.cpu.commit.loads 9092720 # Number of loads committed +system.cpu.commit.membars 226359 # Number of memory barriers committed +system.cpu.commit.branches 8440448 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51992006 # Number of committed integer instructions. -system.cpu.commit.function_calls 740231 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1836771 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52023156 # Number of committed integer instructions. +system.cpu.commit.function_calls 740622 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1852043 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140880188 # The number of ROB reads -system.cpu.rob.rob_writes 128461324 # The number of ROB writes -system.cpu.timesIdled 1178621 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28110338 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599915455 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52951550 # Number of Instructions Simulated -system.cpu.committedOps 52951550 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52951550 # Number of Instructions Simulated -system.cpu.cpi 2.052993 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.052993 # CPI: Total CPI of All Threads -system.cpu.ipc 0.487094 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.487094 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73826909 # number of integer regfile reads -system.cpu.int_regfile_writes 40289801 # number of integer regfile writes -system.cpu.fp_regfile_reads 166028 # number of floating regfile reads -system.cpu.fp_regfile_writes 167439 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985478 # number of misc regfile reads -system.cpu.misc_regfile_writes 938924 # number of misc regfile writes +system.cpu.rob.rob_reads 141717845 # The number of ROB reads +system.cpu.rob.rob_writes 128525319 # The number of ROB writes +system.cpu.timesIdled 1192872 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38720304 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598287306 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52982774 # Number of Instructions Simulated +system.cpu.committedOps 52982774 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52982774 # Number of Instructions Simulated +system.cpu.cpi 2.267639 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.267639 # CPI: Total CPI of All Threads +system.cpu.ipc 0.440987 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.440987 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73877727 # number of integer regfile reads +system.cpu.int_regfile_writes 40299404 # number of integer regfile writes +system.cpu.fp_regfile_reads 166073 # number of floating regfile reads +system.cpu.fp_regfile_writes 167447 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985193 # number of misc regfile reads +system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -620,193 +800,319 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1007426 # number of replacements -system.cpu.icache.tagsinuse 510.288426 # Cycle average of tags in use -system.cpu.icache.total_refs 7476565 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1007934 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.417713 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20275724000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.288426 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7476566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7476566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7476566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7476566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7476566 # number of overall hits -system.cpu.icache.overall_hits::total 7476566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064170 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064170 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064170 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064170 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064170 # number of overall misses -system.cpu.icache.overall_misses::total 1064170 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14673680991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14673680991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14673680991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14673680991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14673680991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14673680991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8540736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8540736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8540736 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8540736 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8540736 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8540736 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124599 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124599 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124599 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124599 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124599 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124599 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13788.850457 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13788.850457 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13788.850457 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13788.850457 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6348 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 862 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked +system.iobus.throughput 1455318 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7103 # Transaction distribution +system.iobus.trans_dist::ReadResp 7103 # Transaction distribution +system.iobus.trans_dist::WriteReq 51150 # Transaction distribution +system.iobus.trans_dist::WriteResp 51150 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2705756 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 378262152 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.throughput 112025274 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2118762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2118660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 68 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3678751 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 5699466 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64659008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143612852 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 208271860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208261812 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17792 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2480878498 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1516366019 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2115023448 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.icache.replacements 1009685 # number of replacements +system.cpu.icache.tagsinuse 509.751691 # Cycle average of tags in use +system.cpu.icache.total_refs 7503411 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1010193 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.427700 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 25536785000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.751691 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.995609 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.995609 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7503412 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7503412 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7503412 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7503412 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7503412 # number of overall hits +system.cpu.icache.overall_hits::total 7503412 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066934 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066934 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1066934 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1066934 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1066934 # number of overall misses +system.cpu.icache.overall_misses::total 1066934 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15003433992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15003433992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15003433992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15003433992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15003433992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15003433992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8570346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8570346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8570346 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8570346 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8570346 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8570346 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124491 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124491 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124491 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124491 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124491 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124491 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14062.195030 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14062.195030 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14062.195030 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14062.195030 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14062.195030 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14062.195030 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6693 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 179 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 211 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.899497 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 862 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.720379 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 179 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56016 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12024926992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12024926992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12024926992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12024926992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12024926992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118041 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118041 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118041 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118041 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118041 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12286930976 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12286930976 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12286930976 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117897 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.117897 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.117897 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12160.245538 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882603500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216560000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216560000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248679 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.546875 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.546875 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383345 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383345 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277584 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167583 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167583 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73762.929496 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50409.455221 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56860.023379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38119.936673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38817.887341 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68710.931156 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68710.931156 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73762.929496 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55834.371691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56502.344004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73762.929496 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55834.371691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56502.344004 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -896,161 +1202,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1400143 # number of replacements -system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use -system.cpu.dcache.total_refs 11810847 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1400655 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.432374 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21808000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7205070 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7205070 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204085 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204085 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 185954 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 185954 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108895 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000023 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246981 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246981 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246981 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246981 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18816.932059 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18816.932059 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33465.791477 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33465.791477 # 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number of cycles access was blocked +system.cpu.dcache.replacements 1401615 # number of replacements +system.cpu.dcache.tagsinuse 511.994565 # Cycle average of tags in use +system.cpu.dcache.total_refs 11806786 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1402127 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.420625 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 25214000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994565 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7200855 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7200855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4204221 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4204221 # 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number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3747844 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3747844 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3747844 # number of overall misses +system.cpu.dcache.overall_misses::total 3747844 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39515383000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39515383000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 75738860769 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 75738860769 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 321949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 65000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 65000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115254243769 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115254243769 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115254243769 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115254243769 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9004912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9004912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6148008 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6148008 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208694 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208694 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15152920 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15152920 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15152920 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15152920 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200341 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200341 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316165 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316165 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109002 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109002 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247335 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247335 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247335 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247335 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21903.622225 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21903.622225 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38964.588594 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38964.588594 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14152.848602 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14152.848602 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16250 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30752.145439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30752.145439 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2955693 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 101444 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.724285 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 154.428571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.136203 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840025 # number of writebacks -system.cpu.dcache.writebacks::total 840025 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717752 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717752 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640976 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1640976 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5261 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5261 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2358728 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2358728 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2358728 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2358728 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300236 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300236 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17463 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17463 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383340 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383340 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383340 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383340 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21322279500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21322279500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9864847262 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9864847262 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 66500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 66500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187126762 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31187126762 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187126762 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31187126762 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423835500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423835500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997377498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997377498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421212998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421212998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120266 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120266 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048856 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048856 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083684 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083684 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091302 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091302 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19686.271586 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19686.271586 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32856.976718 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32856.976718 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11496.363740 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11496.363740 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13300 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840976 # number of writebacks +system.cpu.dcache.writebacks::total 840976 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719736 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 719736 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643409 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643409 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5171 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5171 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2363145 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2363145 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2363145 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2363145 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084321 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084321 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300378 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300378 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17577 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17577 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384699 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384699 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384699 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384699 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26518641540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26518641540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11550001786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11550001786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 202636005 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 202636005 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 57000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 57000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38068643326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38068643326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38068643326 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38068643326 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424047000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424047000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997793498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997793498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421840498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421840498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048858 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084224 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084224 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091382 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091382 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24456.449280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24456.449280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38451.556992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38451.556992 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11528.474996 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11528.474996 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1059,28 +1365,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211001 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182232 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818327594000 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63775000 0.00% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 558444000 0.03% 98.09% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35364889500 1.91% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854314702500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817988566000 97.78% 97.78% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64092000 0.00% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554660500 0.03% 97.82% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 40611610500 2.18% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859218929000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1119,29 +1425,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175117 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191961 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191976 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326381 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326328 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394218 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29464996000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2711269000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822138429500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29661883000 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2771562000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826785476000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 3510035fa..936d08062 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841721 # Number of seconds simulated -sim_ticks 1841721066000 # Number of ticks simulated -final_tick 1841721066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842698 # Number of seconds simulated +sim_ticks 1842697801000 # Number of ticks simulated +final_tick 1842697801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 314597 # Simulator instruction rate (inst/s) -host_op_rate 314597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8282501609 # Simulator tick rate (ticks/s) -host_mem_usage 307380 # Number of bytes of host memory used -host_seconds 222.36 # Real time elapsed on the host -sim_insts 69954713 # Number of instructions simulated -sim_ops 69954713 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19360768 # Number of bytes read from this memory +host_inst_rate 215096 # Simulator instruction rate (inst/s) +host_op_rate 215096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5452418287 # Simulator tick rate (ticks/s) +host_mem_usage 309280 # Number of bytes of host memory used +host_seconds 337.96 # Real time elapsed on the host +sim_insts 72693799 # Number of instructions simulated +sim_ops 72693799 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 487424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20019264 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2811776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2696640 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7466048 # Number of bytes written to this memory -system.physmem.bytes_written::total 7466048 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302512 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 147904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2316480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 282624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2529216 # Number of bytes read from this memory +system.physmem.bytes_read::total 28435264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 487424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 282624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 917952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory +system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 312801 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42135 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444383 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116657 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116657 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10512324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1526711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1464196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15442356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053843 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053843 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10512324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1526711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1464196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19496199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109805 # Total number of read requests seen -system.physmem.writeReqs 45348 # Total number of write requests seen -system.physmem.cpureqs 155202 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7027520 # Total number of bytes read from memory -system.physmem.bytesWritten 2902272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7027520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2902272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6891 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6837 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6841 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2758 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2749 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2776 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3031 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3192 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2803 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis +system.physmem.num_reads::cpu1.inst 2311 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 36195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39519 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444301 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 264517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10864106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1257113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 153375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1372561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15431322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 264517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 153375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498157 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 264517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10864106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1257113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 153375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1372561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19479509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 99716 # Total number of read requests seen +system.physmem.writeReqs 44920 # Total number of write requests seen +system.physmem.cpureqs 144680 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6381824 # Total number of bytes read from memory +system.physmem.bytesWritten 2874880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6381824 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2874880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6258 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6396 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6492 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6146 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2882 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2846 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2624 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3004 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3022 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2472 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2760 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840708761500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1841685476500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109805 # Categorize read packet sizes +system.physmem.readPktSize::6 99716 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 45348 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 80824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44920 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 68031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,242 +148,369 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.totQLat 2404806500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4407346500 # Sum of mem lat for all requests -system.physmem.totBusLat 549000000 # Total cycles spent in databus access -system.physmem.totBankLat 1453540000 # Total cycles spent in bank access -system.physmem.avgQLat 21901.70 # Average queueing delay per request -system.physmem.avgBankLat 13238.07 # Average bank access latency per request +system.physmem.wrQLenPdf::0 1388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 15781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 586.280717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.240853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1929.214074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 6626 41.99% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2550 16.16% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1431 9.07% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 896 5.68% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 638 4.04% 76.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 562 3.56% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 391 2.48% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 301 1.91% 84.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 260 1.65% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 205 1.30% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 214 1.36% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 213 1.35% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 77 0.49% 91.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 70 0.44% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 80 0.51% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 90 0.57% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 36 0.23% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 39 0.25% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 57 0.36% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 48 0.30% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 35 0.22% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 177 1.12% 95.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.55% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 34 0.22% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 7 0.04% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 18 0.11% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 14 0.09% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 8 0.05% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 6 0.04% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 4 0.03% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 1 0.01% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.01% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 2 0.01% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.01% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 1 0.01% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.01% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 1 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.01% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.01% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.01% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 384 2.43% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.05% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 1 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 15781 # Bytes accessed per row activation +system.physmem.totQLat 1934459750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3605914750 # Sum of mem lat for all requests +system.physmem.totBusLat 498525000 # Total cycles spent in databus access +system.physmem.totBankLat 1172930000 # Total cycles spent in bank access +system.physmem.avgQLat 19401.83 # Average queueing delay per request +system.physmem.avgBankLat 11764.00 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40139.77 # Average memory access latency -system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 36165.84 # Average memory access latency +system.physmem.avgRdBW 3.46 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.46 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.17 # Average write queue length over time -system.physmem.readRowHits 99784 # Number of row buffer hits during reads -system.physmem.writeRowHits 34161 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.33 # Row buffer hit rate for writes -system.physmem.avgGap 11863829.65 # Average gap between requests -system.l2c.replacements 337457 # number of replacements -system.l2c.tagsinuse 65420.293999 # Cycle average of tags in use -system.l2c.total_refs 2475568 # Total number of references to valid blocks. -system.l2c.sampled_refs 402619 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.148662 # Average number of references to valid blocks. +system.physmem.readRowHits 93388 # Number of row buffer hits during reads +system.physmem.writeRowHits 35434 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.88 # Row buffer hit rate for writes +system.physmem.avgGap 12733243.98 # Average gap between requests +system.membus.throughput 19523449 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46002 # Transaction distribution +system.membus.trans_dist::ReadResp 45972 # Transaction distribution +system.membus.trans_dist::WriteReq 3749 # Transaction distribution +system.membus.trans_dist::WriteResp 3749 # Transaction distribution +system.membus.trans_dist::Writeback 44920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 46 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47 # Transaction distribution +system.membus.trans_dist::ReadExReq 56809 # Transaction distribution +system.membus.trans_dist::ReadExResp 56809 # Transaction distribution +system.membus.trans_dist::BadAddressError 30 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 192737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 206111 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 51863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 13314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 244600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 257974 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7047808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 7063555 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2208896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 9256704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9272451 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35965768 # Total data (bytes) +system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12475000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 520545500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 35000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 777595953 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 156419750 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.l2c.replacements 337378 # number of replacements +system.l2c.tagsinuse 65422.722236 # Cycle average of tags in use +system.l2c.total_refs 2472063 # Total number of references to valid blocks. +system.l2c.sampled_refs 402541 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.141146 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54855.924450 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2280.990805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2631.435167 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 619.089376 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 660.267485 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2247.126162 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2125.460555 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.837035 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.034805 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040153 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.009447 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.010075 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.034288 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032432 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998234 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 516823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491434 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83916 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 295941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 241655 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1756609 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836144 # number of Writeback hits -system.l2c.Writeback_hits::total 836144 # number of Writeback hits +system.l2c.occ_blocks::writebacks 54907.432737 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2460.754948 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2679.156770 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 579.419963 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 590.394247 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2099.377178 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 2106.186392 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.837821 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.037548 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.040881 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.008841 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.009009 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.032034 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.032138 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998272 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 520270 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493307 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124051 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83977 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 292923 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239241 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1753769 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835411 # number of Writeback hits +system.l2c.Writeback_hits::total 835411 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92196 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27303 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67454 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186953 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 516823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 583630 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 126840 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 111219 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 295941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 309109 # number of demand (read+write) hits -system.l2c.demand_hits::total 1943562 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 516823 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62303.576116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58932.120503 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -494,14 +629,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255737 # Cycle average of tags in use +system.iocache.tagsinuse 1.254871 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693878100000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255737 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078484 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078484 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1694871315000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.254871 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078429 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078429 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -510,14 +645,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4330975325 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4330975325 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4340153323 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4340153323 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4340153323 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4340153323 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9512963 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9512963 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4344125507 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4344125507 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4353638470 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4353638470 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4353638470 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4353638470 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -534,19 +669,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104230.249446 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104230.249446 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 104018.054476 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104018.054476 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 104018.054476 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104018.054476 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 117509 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54988.225434 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54988.225434 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104546.724755 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 104546.724755 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 104341.245536 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 104341.245536 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 113861 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11192 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11412 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.499375 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.977305 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -554,36 +689,36 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 16768 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 16768 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 16837 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3458522887 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3458522887 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3464112136 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3464112136 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3464112136 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3464112136 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17349 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5924213 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5924213 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3445287507 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3445287507 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3451211720 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3451211720 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3451211720 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3451211720 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 206257.328662 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 206257.328662 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85858.159420 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 85858.159420 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199380.064062 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199380.064062 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -601,22 +736,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4882934 # DTB read hits -system.cpu0.dtb.read_misses 6016 # DTB read misses -system.cpu0.dtb.read_acv 120 # DTB read access violations -system.cpu0.dtb.read_accesses 427387 # DTB read accesses -system.cpu0.dtb.write_hits 3510109 # DTB write hits -system.cpu0.dtb.write_misses 663 # DTB write misses -system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162920 # DTB write accesses -system.cpu0.dtb.data_hits 8393043 # DTB hits -system.cpu0.dtb.data_misses 6679 # DTB misses -system.cpu0.dtb.data_acv 202 # DTB access violations -system.cpu0.dtb.data_accesses 590307 # DTB accesses -system.cpu0.itb.fetch_hits 2747668 # ITB hits -system.cpu0.itb.fetch_misses 3002 # ITB misses -system.cpu0.itb.fetch_acv 100 # ITB acv -system.cpu0.itb.fetch_accesses 2750670 # ITB accesses +system.cpu0.dtb.read_hits 4916475 # DTB read hits +system.cpu0.dtb.read_misses 6063 # DTB read misses +system.cpu0.dtb.read_acv 126 # DTB read access violations +system.cpu0.dtb.read_accesses 427415 # DTB read accesses +system.cpu0.dtb.write_hits 3510632 # DTB write hits +system.cpu0.dtb.write_misses 668 # DTB write misses +system.cpu0.dtb.write_acv 84 # DTB write access violations +system.cpu0.dtb.write_accesses 162993 # DTB write accesses +system.cpu0.dtb.data_hits 8427107 # DTB hits +system.cpu0.dtb.data_misses 6731 # DTB misses +system.cpu0.dtb.data_acv 210 # DTB access violations +system.cpu0.dtb.data_accesses 590408 # DTB accesses +system.cpu0.itb.fetch_hits 2754785 # ITB hits +system.cpu0.itb.fetch_misses 3015 # ITB misses +system.cpu0.itb.fetch_acv 104 # ITB acv +system.cpu0.itb.fetch_accesses 2757800 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -629,51 +764,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928534019 # number of cpu cycles simulated +system.cpu0.numCycles 928378822 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33030135 # Number of instructions committed -system.cpu0.committedOps 33030135 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30904296 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 168660 # Number of float alu accesses -system.cpu0.num_func_calls 809909 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4463035 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30904296 # number of integer instructions -system.cpu0.num_fp_insts 168660 # number of float instructions -system.cpu0.num_int_register_reads 43221651 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22562663 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87082 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88661 # number of times the floating registers were written -system.cpu0.num_mem_refs 8422848 # number of memory refs -system.cpu0.num_load_insts 4904051 # Number of load instructions -system.cpu0.num_store_insts 3518797 # Number of store instructions -system.cpu0.num_idle_cycles 214028158129.505707 # Number of idle cycles -system.cpu0.num_busy_cycles -213099624110.505707 # Number of busy cycles -system.cpu0.not_idle_fraction -229.501149 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.501149 # Percentage of idle cycles +system.cpu0.committedInsts 33851772 # Number of instructions committed +system.cpu0.committedOps 33851772 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31712153 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169925 # Number of float alu accesses +system.cpu0.num_func_calls 812668 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4695347 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31712153 # number of integer instructions +system.cpu0.num_fp_insts 169925 # number of float instructions +system.cpu0.num_int_register_reads 44553309 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23136473 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87700 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89305 # number of times the floating registers were written +system.cpu0.num_mem_refs 8457205 # number of memory refs +system.cpu0.num_load_insts 4937806 # Number of load instructions +system.cpu0.num_store_insts 3519399 # Number of store instructions +system.cpu0.num_idle_cycles 213007832176.448029 # Number of idle cycles +system.cpu0.num_busy_cycles -212079453354.448029 # Number of busy cycles +system.cpu0.not_idle_fraction -228.440641 # Percentage of non-idle cycles +system.cpu0.idle_fraction 229.440641 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211352 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105677 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182552 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818574542500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39495500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 364949500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22741309000 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841720296500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819523663000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39251000 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365640000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22768477500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842697031500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694825 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815850 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -712,29 +847,29 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175295 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192206 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches +system.cpu0.kern.callpal::total 192238 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1907 system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322074 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.321965 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29798472500 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2570740000 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809351079500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29806042000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2607375500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810283609500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -767,372 +902,458 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 953317 # number of replacements -system.cpu0.icache.tagsinuse 511.202573 # Cycle average of tags in use -system.cpu0.icache.total_refs 42520473 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953828 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 44.578764 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10247489000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 251.172377 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 83.809654 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 176.220543 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.490571 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.163691 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.344181 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998443 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32512787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7733014 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2274672 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42520473 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32512787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7733014 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2274672 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42520473 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32512787 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7733014 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2274672 # number of overall hits -system.cpu0.icache.overall_hits::total 42520473 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 524229 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129219 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 317357 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970805 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 524229 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129219 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 317357 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970805 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 524229 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129219 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 317357 # number of overall misses -system.cpu0.icache.overall_misses::total 970805 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820764500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4451463485 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6272227985 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1820764500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4451463485 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6272227985 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1820764500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4451463485 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6272227985 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33037016 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7862233 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2592029 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43491278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33037016 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7862233 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2592029 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43491278 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33037016 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7862233 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2592029 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43491278 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015868 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016435 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122436 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022322 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015868 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016435 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122436 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022322 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015868 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016435 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122436 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022322 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14090.532352 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14026.674959 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6460.852576 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14090.532352 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14026.674959 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6460.852576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14090.532352 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14026.674959 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6460.852576 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7042 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 180 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 39.122222 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.toL2Bus.throughput 110454960 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 786209 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 786164 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371427 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150852 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133572 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 847417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1371009 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 2218426 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27116864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55346243 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 82463107 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203524040 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2135036000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1907460021 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2223763109 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1469142 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2977 # Transaction distribution +system.iobus.trans_dist::ReadResp 2977 # Transaction distribution +system.iobus.trans_dist::WriteReq 21029 # Transaction distribution +system.iobus.trans_dist::WriteResp 21029 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 48012 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15747 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1123115 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2707184 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 6219000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 1797000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 157278470 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 9565000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 17530000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.replacements 950939 # number of replacements +system.cpu0.icache.tagsinuse 511.192426 # Cycle average of tags in use +system.cpu0.icache.total_refs 43369559 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 951450 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 45.582594 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10375508000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 249.451681 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 99.242283 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 162.498462 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.487210 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.193833 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.317380 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998423 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 33330806 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7798498 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2240255 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43369559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 33330806 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7798498 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2240255 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43369559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 33330806 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7798498 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7567 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 152979 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 345859 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 498838 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 152979 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 345859 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 498838 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1973436500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4297066000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6270502500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1295329500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2136901128 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3432230628 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24853500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70377000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95230500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3268766000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6433967128 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9702733128 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3268766000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6433967128 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9702733128 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287559000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353651000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 641210000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356203000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 430620000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786823000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 643762000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 784271000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1428033000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087118 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088515 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041030 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045415 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021583 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099840 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 144505 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 341032 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 485537 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 144505 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341032 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 485537 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2060552500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4252408235 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6312960735 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1528691000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2589747290 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4118438290 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24153500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66206002 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90359502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 23000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 23000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3589243500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6842155525 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10431399025 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3589243500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6842155525 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10431399025 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295697000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311546500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607243500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 363354500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790734000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 659051500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 738926000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083742 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086377 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039510 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051114 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046891 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021691 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100373 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099599 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037310 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18847.946095 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16439.918892 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17128.636129 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26831.748695 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25295.057091 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25853.870875 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.134892 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12798.145117 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.765247 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032237 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032237 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20733.659013 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16820.503202 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17924.719500 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33878.310396 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29355.224833 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30885.816310 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11213.324048 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12230.925919 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11941.258359 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 23000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1147,22 +1368,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1221065 # DTB read hits -system.cpu1.dtb.read_misses 1489 # DTB read misses -system.cpu1.dtb.read_acv 40 # DTB read access violations -system.cpu1.dtb.read_accesses 143781 # DTB read accesses -system.cpu1.dtb.write_hits 929390 # DTB write hits -system.cpu1.dtb.write_misses 202 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 59266 # DTB write accesses -system.cpu1.dtb.data_hits 2150455 # DTB hits -system.cpu1.dtb.data_misses 1691 # DTB misses -system.cpu1.dtb.data_acv 64 # DTB access violations -system.cpu1.dtb.data_accesses 203047 # DTB accesses -system.cpu1.itb.fetch_hits 872017 # ITB hits -system.cpu1.itb.fetch_misses 756 # ITB misses -system.cpu1.itb.fetch_acv 43 # ITB acv -system.cpu1.itb.fetch_accesses 872773 # ITB accesses +system.cpu1.dtb.read_hits 1206143 # DTB read hits +system.cpu1.dtb.read_misses 1395 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 142828 # DTB read accesses +system.cpu1.dtb.write_hits 904590 # DTB write hits +system.cpu1.dtb.write_misses 190 # DTB write misses +system.cpu1.dtb.write_acv 23 # DTB write access violations +system.cpu1.dtb.write_accesses 58592 # DTB write accesses +system.cpu1.dtb.data_hits 2110733 # DTB hits +system.cpu1.dtb.data_misses 1585 # DTB misses +system.cpu1.dtb.data_acv 58 # DTB access violations +system.cpu1.dtb.data_accesses 201420 # DTB accesses +system.cpu1.itb.fetch_hits 862559 # ITB hits +system.cpu1.itb.fetch_misses 707 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 863266 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1175,28 +1396,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953614996 # number of cpu cycles simulated +system.cpu1.numCycles 953614983 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7860477 # Number of instructions committed -system.cpu1.committedOps 7860477 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7311992 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45303 # Number of float alu accesses -system.cpu1.num_func_calls 212165 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 960179 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7311992 # number of integer instructions -system.cpu1.num_fp_insts 45303 # number of float instructions -system.cpu1.num_int_register_reads 10165443 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5319467 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24490 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24717 # number of times the floating registers were written -system.cpu1.num_mem_refs 2158115 # number of memory refs -system.cpu1.num_load_insts 1226297 # Number of load instructions -system.cpu1.num_store_insts 931818 # Number of store instructions -system.cpu1.num_idle_cycles -703122010.262243 # Number of idle cycles -system.cpu1.num_busy_cycles 1656737006.262243 # Number of busy cycles -system.cpu1.not_idle_fraction 1.737323 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.737323 # Percentage of idle cycles +system.cpu1.committedInsts 7923216 # Number of instructions committed +system.cpu1.committedOps 7923216 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7378774 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44696 # Number of float alu accesses +system.cpu1.num_func_calls 212761 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1003934 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7378774 # number of integer instructions +system.cpu1.num_fp_insts 44696 # number of float instructions +system.cpu1.num_int_register_reads 10322317 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5366754 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24140 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24473 # number of times the floating registers were written +system.cpu1.num_mem_refs 2118035 # number of memory refs +system.cpu1.num_load_insts 1211092 # Number of load instructions +system.cpu1.num_store_insts 906943 # Number of store instructions +system.cpu1.num_idle_cycles -710985323.015638 # Number of idle cycles +system.cpu1.num_busy_cycles 1664600306.015638 # Number of busy cycles +system.cpu1.not_idle_fraction 1.745569 # Percentage of non-idle cycles +system.cpu1.idle_fraction -0.745569 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1214,35 +1435,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8370437 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7682240 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 128031 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6854257 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5743720 # Number of BTB hits +system.cpu2.branchPred.lookups 8997247 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8318296 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 124435 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7453298 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6389224 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 83.797850 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 284899 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 14987 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.723448 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 282371 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13443 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3211638 # DTB read hits -system.cpu2.dtb.read_misses 11756 # DTB read misses -system.cpu2.dtb.read_acv 123 # DTB read access violations -system.cpu2.dtb.read_accesses 216825 # DTB read accesses -system.cpu2.dtb.write_hits 1985602 # DTB write hits -system.cpu2.dtb.write_misses 2511 # DTB write misses -system.cpu2.dtb.write_acv 137 # DTB write access violations -system.cpu2.dtb.write_accesses 81903 # DTB write accesses -system.cpu2.dtb.data_hits 5197240 # DTB hits -system.cpu2.dtb.data_misses 14267 # DTB misses -system.cpu2.dtb.data_acv 260 # DTB access violations -system.cpu2.dtb.data_accesses 298728 # DTB accesses -system.cpu2.itb.fetch_hits 370869 # ITB hits -system.cpu2.itb.fetch_misses 5705 # ITB misses -system.cpu2.itb.fetch_acv 274 # ITB acv -system.cpu2.itb.fetch_accesses 376574 # ITB accesses +system.cpu2.dtb.read_hits 3184667 # DTB read hits +system.cpu2.dtb.read_misses 11563 # DTB read misses +system.cpu2.dtb.read_acv 122 # DTB read access violations +system.cpu2.dtb.read_accesses 218108 # DTB read accesses +system.cpu2.dtb.write_hits 2003168 # DTB write hits +system.cpu2.dtb.write_misses 2582 # DTB write misses +system.cpu2.dtb.write_acv 105 # DTB write access violations +system.cpu2.dtb.write_accesses 82984 # DTB write accesses +system.cpu2.dtb.data_hits 5187835 # DTB hits +system.cpu2.dtb.data_misses 14145 # DTB misses +system.cpu2.dtb.data_acv 227 # DTB access violations +system.cpu2.dtb.data_accesses 301092 # DTB accesses +system.cpu2.itb.fetch_hits 370432 # ITB hits +system.cpu2.itb.fetch_misses 5697 # ITB misses +system.cpu2.itb.fetch_acv 245 # ITB acv +system.cpu2.itb.fetch_accesses 376129 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1255,270 +1476,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30454355 # number of cpu cycles simulated +system.cpu2.numCycles 31194709 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8502723 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34791371 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8370437 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6028619 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8097928 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 618452 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9649671 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10614 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63437 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 88147 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 485 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2592037 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 89025 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26817742 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.297327 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.307851 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8336463 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36595534 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8997247 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6671595 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8714180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 607609 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9678498 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11323 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1980 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 64467 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 86613 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2554168 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 86055 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27288913 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.341040 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.295561 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18719814 69.80% 69.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 271918 1.01% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 439106 1.64% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4240914 15.81% 88.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 731900 2.73% 91.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 166811 0.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 194731 0.73% 92.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 431926 1.61% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1620622 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18574733 68.07% 68.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269160 0.99% 69.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 428961 1.57% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4866915 17.83% 88.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 754326 2.76% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165422 0.61% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 191254 0.70% 92.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 429367 1.57% 94.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1608775 5.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26817742 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.274852 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.142410 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8640997 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9744638 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7501940 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293665 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 390587 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 167981 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12867 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34389263 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40403 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 390587 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8994385 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2850333 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5733998 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7360278 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1242256 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33240737 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2380 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234906 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 409580 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22320164 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41423386 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41259446 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 163940 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20500425 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1819739 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 502711 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59638 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3682174 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3369954 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2075842 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 372990 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 254270 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30724821 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 626542 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30272457 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 30970 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2165066 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1087715 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 442386 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26817742 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.128822 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.564509 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27288913 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288422 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.173133 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8484758 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9763089 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8105885 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 306526 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 382761 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165822 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12764 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36197990 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39851 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 382761 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8844170 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2798398 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5770090 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7975185 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1272419 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35047656 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 232046 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 447152 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23489226 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43822690 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43659490 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 163200 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21694214 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1795012 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 501276 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59320 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3724979 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3343402 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2093050 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 368261 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 257932 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32557394 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 620599 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32107794 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 34091 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2143269 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1080696 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 438167 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27288913 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.176588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.573888 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15272797 56.95% 56.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3099841 11.56% 68.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1551477 5.79% 74.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5057037 18.86% 93.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 907037 3.38% 96.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 485633 1.81% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 283575 1.06% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141972 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18373 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15150790 55.52% 55.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3070151 11.25% 66.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1548988 5.68% 72.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5689584 20.85% 93.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 903005 3.31% 96.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480338 1.76% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 283929 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 143393 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18735 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26817742 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27288913 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34129 13.74% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 111357 44.84% 58.58% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 102854 41.42% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33803 13.75% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 111727 45.45% 59.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100297 40.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24602631 81.27% 81.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20294 0.07% 81.35% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8465 0.03% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3340354 11.03% 92.41% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2007868 6.63% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289173 0.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26449669 82.38% 82.39% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20147 0.06% 82.45% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8446 0.03% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3312033 10.32% 92.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2025467 6.31% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288360 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30272457 # Type of FU issued -system.cpu2.iq.rate 0.994027 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 248340 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008203 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87406741 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33405587 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29873950 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 235225 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114899 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 111509 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30395868 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122481 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 188565 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32107794 # Type of FU issued +system.cpu2.iq.rate 1.029271 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 245827 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 91550157 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35210267 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 31710626 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234262 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114809 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110859 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32229265 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121908 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186278 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 411297 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 939 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4131 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 160227 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 409987 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1098 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3916 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 156672 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4708 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 24260 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4171 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28368 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 390587 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2070216 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 210596 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32630441 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224813 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3369954 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2075842 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 556425 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 148713 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2116 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4131 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 65748 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 128933 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 194681 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30112166 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3231643 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 160291 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 382761 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2017515 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 205037 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34446466 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224960 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3343402 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2093050 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 551127 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 142834 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3916 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63764 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127616 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 191380 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31948816 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3204490 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 158978 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1279078 # number of nop insts executed -system.cpu2.iew.exec_refs 5224243 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6789433 # Number of branches executed -system.cpu2.iew.exec_stores 1992600 # Number of stores executed -system.cpu2.iew.exec_rate 0.988764 # Inst execution rate -system.cpu2.iew.wb_sent 30017965 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29985459 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17323993 # num instructions producing a value -system.cpu2.iew.wb_consumers 20546016 # num instructions consuming a value +system.cpu2.iew.exec_nop 1268473 # number of nop insts executed +system.cpu2.iew.exec_refs 5214665 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7427208 # Number of branches executed +system.cpu2.iew.exec_stores 2010175 # Number of stores executed +system.cpu2.iew.exec_rate 1.024174 # Inst execution rate +system.cpu2.iew.wb_sent 31853816 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31821485 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18500784 # num instructions producing a value +system.cpu2.iew.wb_consumers 21694431 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.984603 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.843180 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.020092 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.852790 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2350466 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 184156 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180720 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26427155 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.144119 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.849310 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2318994 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182432 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 176935 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26906152 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.192355 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846387 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16325181 61.77% 61.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2317842 8.77% 70.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1215370 4.60% 75.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4792789 18.14% 93.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 500443 1.89% 95.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186108 0.70% 95.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 178909 0.68% 96.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180996 0.68% 97.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 729517 2.76% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16157542 60.05% 60.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2331595 8.67% 68.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1218913 4.53% 73.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5433463 20.19% 93.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 503772 1.87% 95.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185469 0.69% 96.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 177448 0.66% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 178843 0.66% 97.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 719107 2.67% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26427155 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30235823 # Number of instructions committed -system.cpu2.commit.committedOps 30235823 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26906152 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32081688 # Number of instructions committed +system.cpu2.commit.committedOps 32081688 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4874272 # Number of memory references committed -system.cpu2.commit.loads 2958657 # Number of loads committed -system.cpu2.commit.membars 64665 # Number of memory barriers committed -system.cpu2.commit.branches 6641301 # Number of branches committed -system.cpu2.commit.fp_insts 110294 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28781664 # Number of committed integer instructions. -system.cpu2.commit.function_calls 230734 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 729517 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4869793 # Number of memory references committed +system.cpu2.commit.loads 2933415 # Number of loads committed +system.cpu2.commit.membars 63859 # Number of memory barriers committed +system.cpu2.commit.branches 7280639 # Number of branches committed +system.cpu2.commit.fp_insts 109636 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30638732 # Number of committed integer instructions. +system.cpu2.commit.function_calls 228563 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 719107 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58211181 # The number of ROB reads -system.cpu2.rob.rob_writes 65562875 # The number of ROB writes -system.cpu2.timesIdled 242498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3636613 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745370399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29064101 # Number of Instructions Simulated -system.cpu2.committedOps 29064101 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29064101 # Number of Instructions Simulated -system.cpu2.cpi 1.047834 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.047834 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.954350 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.954350 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39595533 # number of integer regfile reads -system.cpu2.int_regfile_writes 21195830 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68078 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68404 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4592506 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258747 # number of misc regfile writes +system.cpu2.rob.rob_reads 60513787 # The number of ROB reads +system.cpu2.rob.rob_writes 69183653 # The number of ROB writes +system.cpu2.timesIdled 245794 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3905796 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746583104 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 30918811 # Number of Instructions Simulated +system.cpu2.committedOps 30918811 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 30918811 # Number of Instructions Simulated +system.cpu2.cpi 1.008923 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.008923 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.991156 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.991156 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42017360 # number of integer regfile reads +system.cpu2.int_regfile_writes 22376128 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67819 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67985 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5215792 # number of misc regfile reads +system.cpu2.misc_regfile_writes 257331 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |